,2014.3" TimingSummary"PB_RTimingSummaryp 2012.4)Timing analysis from Implemented netlist. ,> 5`<5%Ob>&+,& 2014.3Zmin_maxbslackh p}IIqreport_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violationW -1Cmin_max (08@HX`hpx"  ReportTiming Summary Report  Design ngFEC_top ^ PartVDevice=xcku115 Package=flva2104 Speed=-1 (PRODUCTION 1.26 12-04-2018) Temperature=C T VersionIVivado v2020.2 (64-bit) SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 DateSat Mar 13 12:29:13 2021  Commandreport_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation*/ 9 DRPclk3@I@!(0:#@ > GBT_refclk0Ë>@n t@!(0:Ë>? Q gtwiz_userclk_rx_srcclk_out[0]y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_1y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_10y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_11y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_2y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_3y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_4y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_5y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_6y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_7y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_8y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_9y @"^@!( 0:y@ E qpll0outclk_out[0]Ë>?n @!(0:Ë>? H qpll0outrefclk_out[0]Ë>@n t@!(0:Ë>? E txoutclk_out[0]_49Ë>@n t@!(0:Ë>? > GBT_refclk1Ë>@n t@!(0:Ë>? T !gtwiz_userclk_rx_srcclk_out[0]_12y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_13y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_14y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_15y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_16y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_17y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_18y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_19y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_20y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_21y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_22y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_23y @"^@!(0:y@ > GBT_refclk2Ë>@n t@!(0:Ë>? T !gtwiz_userclk_rx_srcclk_out[0]_24y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_25y @"^@!( 0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_26y @"^@!(!0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_27y @"^@!("0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_28y @"^@!(#0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_29y @"^@!($0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_30y @"^@!(%0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_31y @"^@!(&0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_32y @"^@!('0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_33y @"^@!((0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_34y @"^@!()0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_35y @"^@!(*0:y@ > GBT_refclk3Ë>@n t@!(+0:Ë>? T !gtwiz_userclk_rx_srcclk_out[0]_36y @"^@!(,0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_37y @"^@!(-0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_38y @"^@!(.0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_39y @"^@!(/0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_40y @"^@!(00:y@ T !gtwiz_userclk_rx_srcclk_out[0]_41y @"^@!(10:y@ T !gtwiz_userclk_rx_srcclk_out[0]_42y @"^@!(20:y@ T !gtwiz_userclk_rx_srcclk_out[0]_43y @"^@!(30:y@ T !gtwiz_userclk_rx_srcclk_out[0]_44y @"^@!(40:y@ T !gtwiz_userclk_rx_srcclk_out[0]_45y @"^@!(50:y@ T !gtwiz_userclk_rx_srcclk_out[0]_46y @"^@!(60:y@ T !gtwiz_userclk_rx_srcclk_out[0]_47y @"^@!(70:y@ @ TTC_rx_refclkË>@n t@!(80:Ë>? E qpll1outclk_out[0]Ë>?n @!(90:Ë>? D rxoutclk_out[0]_1Ë>@n t@!(:0:Ë>? H qpll1outrefclk_out[0]Ë>@n t@!(;0:Ë>? ? TTC_rxusrclkË>@n t@!(<0:Ë>? @ fabric_clk_inË>8@n D@!(=0:Ë>(@ ; CLKFBOUTË>8@n D@!(>0:Ë>@yuȶ2@ A fabric_clk_dcmË>8@n D@!(?0:Ë>(@ A tx_wordclk_dcmy @"^@!(@0:y@ 9 clk125@@_@!(A0:@ 9 clk250@@o@!(B0:? = fabric_clkË>8@n D@!(C0:Ë>(@ : ipb_clk?@@?@!(D0:/@ < refclk125@@_@!(E0:@ = DRPclk_dcm3@I@!(F0:#@ = clk125_dcm@@_@!(G0:@ = clk250_dcm@@o@!(H0:? > ipb_clk_dcm?@@?@!(I0:/@ B rxoutclk_out[0]6@A!c@!(J0:6 @ E txoutclk_out[0]_486@A!c@!(K0:6 @ B axi_c2c_phy_clk6)@A!S@!(L0:6@ < rx_rcvclkË>@n t@!(M0:Ë>? = tx_wordclkM @F^@!(N0:M@2 checkTimingRpx" no_clockH" constant_clockH" pulse_width_clockH"$ unconstrained_internal_endpointsH"/ no_input_delayPorts with no input delay(H"1 no_output_delayPorts with no output delay(H" multiple_clockH" generated_clocksH" loopsH" partial_input_delayH" partial_output_delayH" latch_loopsH0 : checking no_clock checking constant_clock checking pulse_width_clock )checking unconstrained_internal_endpoints checking no_input_delay checking no_output_delay checking multiple_clock checking generated_clocks checking loops checking partial_input_delay checking partial_output_delay checking latch_loopsJ checking no_clock3 / There are 0 register/latch pins with no clock./V checking constant_clock9 5 There are 0 register/latch pins with constant_clock.5a checking pulse_width_clockA = There are 0 register/latch pins which need pulse_width check= )checking unconstrained_internal_endpointsA = There are 0 pins that are not constrained for maximum delay.=W S There are 0 pins that are not constrained for maximum delay due to constant clock.S checking no_input_delayC ? There are 34 input ports with no input delay specified. (HIGH)?V R There are 0 input ports with no input delay but user has a false path constraint.R" checking no_output_delay> : There are 28 ports with no output delay specified. (HIGH):P L There are 0 ports with no output delay but user has a false path constraintLk g There are 0 ports with no output delay but with a timing clock defined on it or propagating through itgW checking multiple_clock: 6 There are 0 register/latch pins with multiple clocks.6j checking generated_clocksK G There are 0 generated clocks that are not connected to a clock source.GG checking loops3 / There are 0 combinational loops in the design./b checking partial_input_delay@ < There are 0 input ports with partial input delay specified.<^ checking partial_output_delay; 7 There are 0 ports with partial output delay specified.7f checking latch_loopsL H There are 0 combinational latch loops in the design through latch inputH& ns"MHz(0Bcheck_timing reportB SlowYesYes FastYesYes# Enable Multi Corner AnalysisYes Enable Pessimism RemovalYes3 Pessimism Removal ResolutionNearest Common Node& Enable Input Delay Default ClockNo Enable Preset / Clear ArcsNo Disable Flight DelaysNo Ignore I/O PathsNo. (Timing Early Launch at Borrowing LatchesNo+ $Borrow Time for Max Delay ExceptionsYes Merge Timing ExceptionsYes"B Timing Configuration Reportns"MHz(0Bconfig timing reportR  !)19AIe,>hq}5`<5Ob>8@EHP7X`ZͶG  !gtwiz_userclk_rx_srcclk_out[0]_21 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[19].rx_frameclk_div2_reg[19]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  CLKFBOUTp Min Periodb -2V20"CLKFBOUT_bufg/I*n/a27 CLKFBOUTA@EA"fabric_clk_MMCM/CLKFBOUTy Min Periodk @2V2w̫0"fabric_clk_MMCM/CLKFBOUT*n/a27 CLKFBOUTA@EA"fabric_clk_MMCM/CLKFBOUTx Min Periodj @2V2w̫0"fabric_clk_MMCM/CLKFBIN*n/a27 CLKFBOUTA@EA"fabric_clk_MMCM/CLKFBOUT  !gtwiz_userclk_rx_srcclk_out[0]_43 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[72]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[74]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[80]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[82]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./";7SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./";7SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_32 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[74]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./".*SFP_GEN[30].ngCCM_gbt/RX_Clock_40MHz_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" Q 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" +o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_10 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"1-g_clock_rate_din[8].rx_frameclk_div2_reg[8]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Y TTC_rxusrclk Min Period 0VV1/1"i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period 0VV1/1"i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period o1VV1w̫0"!i_tcds2_if/bufgce_clk_40_rx/I*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period S01VV1.0"40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period S01VV1.0">:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period S01VV1.0"@:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C*Slow2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O" Low P0V0./"@:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C*Fast2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O* High R0V0./"@SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ͩ !gtwiz_userclk_rx_srcclk_out[0]_33 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[31].rx_data_ngccm_reg[31][32]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[31].rx_data_ngccm_reg[31][40]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[31].rx_frameclk_div2_reg[31]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[64]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[66]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCSFP_GEN[31].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_22 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_11 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"1-g_clock_rate_din[9].rx_frameclk_div2_reg[9]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  rxoutclk_out[0]_1 Min Period u0VV10"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 rxoutclk_out[0]_1G@?"i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_3 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C*Slow2 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0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 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.ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  txoutclk_out[0]_48 Min Period _110"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I*n/a2 txoutclk_out[0]_48@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK Min Period _110"tpi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I*n/a2 txoutclk_out[0]_48@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK2 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" // (0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Slow2 txoutclk_out[0]_48@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK2 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" R/XL/0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast2 txoutclk_out[0]_48@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK  clk250_dcmo Min Perioda %1_p10"i_clk250_bufg/I*n/a26 clk250_dcm@@"i_clk125_MMCM/CLKOUT3u Min Periodg <1_p1w̫0"i_clk125_MMCM/CLKOUT3*n/a26 clk250_dcm@@"i_clk125_MMCM/CLKOUT3  rxoutclk_out[0] Min Period 11/1"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period 11/1"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period pr111"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period _110"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ~O11^0"mii_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/SRLC32E_inst_4/CLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ~O11^0"xti_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1/CLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ~O11^0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1/CLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ~O11^0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1/CLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ~O11^0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1/CLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ~O11^0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[13].SRLC32E_inst_1/CLK*n/a2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low ɼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low ɼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low ˼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low ˼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low ;{1[1ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low ={1[1ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low zO-1[1^:0"xti_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1/CLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low zO-1[1^:0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1/CLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low zO-1[1^:0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1/CLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low zO-1[1^:0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1/CLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High ̼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High ̼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High ̼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High ̼ 1[1fT0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High :{1[1ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High ;{1[1ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High |O-1[1^:0"xti_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1/CLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High |O-1[1^:0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1/CLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High |O-1[1^:0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1/CLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High |O-1[1^:0"yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1/CLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0.o0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 9 0(-a0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" zn0(-;qr0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" e0.ل0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 rxoutclk_out[0]@L@"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  tx_wordclk Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" C0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" C0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" E0@-0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O  !gtwiz_userclk_rx_srcclk_out[0]_41 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[39].rx_test_comm_cnt_reg[39]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_30 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0] Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"@:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[10].ngccm_status_cnt_reg[10][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[10].ngccm_status_cnt_reg[10][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[10].ngccm_status_cnt_reg[10][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[10].rx_test_comm_cnt_reg[10]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  clk125_dcmp Min Periodb XY1_p 20"i_clk125_bufg/I*n/a27 clk125_dcmA@"i_clk125_MMCM/CLKFBOUTw Min Periodi 1_p 2w̫0"i_clk125_MMCM/CLKFBOUT*n/a27 clk125_dcmA@"i_clk125_MMCM/CLKFBOUT ֩ gtwiz_userclk_rx_srcclk_out[0]_2 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_5 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"{wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ɧ gtwiz_userclk_rx_srcclk_out[0]_6 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" [A0@F.o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0hU-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" l0hU-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" M0@F.ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_7 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/READY_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"{wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ŧ gtwiz_userclk_rx_srcclk_out[0]_8 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][6]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"1-g_clock_rate_din[6].rx_frameclk_div2_reg[6]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_9 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][6]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,g_clock_rate_din[7].rx_wordclk_div2_reg[7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"1-g_clock_rate_din[7].rx_frameclk_div2_reg[7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"+'SFP_GEN[7].ngccm_status_reg_reg[7][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./",(SFP_GEN[7].ngccm_status_reg_reg[7][16]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK R clk125 Min Period 0l1_p 21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Period 0l1_p 21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Period 0l1_p 21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*n/a2, clk125A@"i_clk125_bufg/O Min Period 0l1_p 21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Period S1_p 2m0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMA/CLK*n/a2, clk125A@"i_clk125_bufg/O Min Period S1_p 2m0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMB/CLK*n/a2, clk125A@"i_clk125_bufg/O Min Period S1_p 2m0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMC/CLK*n/a2, clk125A@"i_clk125_bufg/O Min Period S1_p 2m0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMD/CLK*n/a2, clk125A@"i_clk125_bufg/O Min Period S1_p 2m0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAME/CLK*n/a2, clk125A@"i_clk125_bufg/O Min Period S1_p 2m0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMF/CLK*n/a2, clk125A@"i_clk125_bufg/O" Low tQ1^p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O" Low tQ1^p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2, clk125A@"i_clk125_bufg/O" Low tQ1^p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O" Low tQ1_p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O" Low tQ1`p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O" Low tQ1`p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O" Low tQ1`p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O" Low tQ1`p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2, clk125A@"i_clk125_bufg/O" Low O\1]p1mY0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7/DP/CLK*Slow2, clk125A@"i_clk125_bufg/O" Low O\1]p1mY0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7/SP/CLK*Slow2, clk125A@"i_clk125_bufg/O* High tQ1^p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* High tQ1^p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* High tQ1^p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2, clk125A@"i_clk125_bufg/O* High tQ1_p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O* High tQ1_p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O* High tQ1_p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O* High tQ1`p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2, clk125A@"i_clk125_bufg/O* High tQ1`p1ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* High Q\1^p1mY0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7/DP/CLK*Fast2, clk125A@"i_clk125_bufg/O* High Q\1^p1mY0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7/SP/CLK*Fast2, clk125A@"i_clk125_bufg/O  !gtwiz_userclk_rx_srcclk_out[0]_45 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[81]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[43].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[43].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[43].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[12]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[43].rx_wordclk_div2_reg[43]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_34 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[32].rx_test_comm_cnt_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_23 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[21].rx_frameclk_div2_reg[21]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[22]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_12 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_46 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][7]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[44].rx_frameclk_div2_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[44].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_35 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./".*SFP_GEN[33].ngCCM_gbt/RX_Clock_40MHz_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"/+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"/+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"/+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_24 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[24].rx_test_comm_cnt_reg[24]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[20]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[22]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[24]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[25]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_13 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[22].rx_frameclk_div2_reg[22]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[22].rx_test_comm_cnt_reg[22]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_47 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[21]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[22]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[23]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[28]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[31]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ˬ !gtwiz_userclk_rx_srcclk_out[0]_36 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[36].rx_test_comm_cnt_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_25 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[34].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[34].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[34].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_14 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][7]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[23].rx_test_comm_cnt_reg[23]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[23].rx_wordclk_div2_reg[23]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"IEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0(-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" bm0(-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_37 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][7]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8SFP_GEN[46].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[16]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[19]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[20]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[21]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[22]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 4 0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0q-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \n0q-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" <0P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_26 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[35].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[35].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_15 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[13].rx_test_comm_cnt_reg[13]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_38 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"2.g_clock_rate_din[47].rx_wordclk_div2_reg[47]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./".*SFP_GEN[47].ngCCM_gbt/RX_Clock_40MHz_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[76]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[78]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[80]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ̩ !gtwiz_userclk_rx_srcclk_out[0]_27 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[25].rx_test_comm_cnt_reg[25]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ѧ !gtwiz_userclk_rx_srcclk_out[0]_16 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"2.g_clock_rate_din[14].rx_wordclk_div2_reg[14]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"2.g_clock_rate_din[14].rx_wordclk_div2_reg[14]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_39 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[56]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" U 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" /o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_28 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[68]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_17 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[15].rx_frameclk_div2_reg[15]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" [A0@F.o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0HU-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" l0HU-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" M0@F.ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ω !gtwiz_userclk_rx_srcclk_out[0]_29 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[27].rx_frameclk_div2_reg[27]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"2.g_clock_rate_din[27].rx_wordclk_div2_reg[27]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[27].rx_test_comm_cnt_reg[27]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_18 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_19 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_42 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40SFP_GEN[40].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40SFP_GEN[40].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0".*SFP_GEN[40].ngCCM_gbt/RX_Clock_40MHz_reg/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"/+SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[16]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[17]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[18]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./".*SFP_GEN[40].ngCCM_gbt/RX_Clock_40MHz_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_31 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[29].rx_frameclk_div2_reg[29]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ʧ !gtwiz_userclk_rx_srcclk_out[0]_20 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[18].rx_frameclk_div2_reg[18]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[18].rx_wordclk_div2_reg[18]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_40 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][7]/C*Slow2 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!gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  refclk125g Min PeriodY XY1_p 20"i_refclk125_bufg/I*n/a2+ refclk125A@" refclk125_pi Min Period[ 1_p 2w̫0"i_clk125_MMCM/CLKIN1*n/a2+ refclk125A@" refclk125_p"c Low\ 0^p1?$1"i_clk125_MMCM/CLKIN1*Slow2+ refclk125A@" refclk125_p"c Low\ 0^p1?$1"i_clk125_MMCM/CLKIN1*Fast2+ refclk125A@" refclk125_p*d High\ 0_p1?$1"i_clk125_MMCM/CLKIN1*Slow2+ refclk125A@" refclk125_p*d High\ 0`p1?$1"i_clk125_MMCM/CLKIN1*Fast2+ refclk125A@" refclk125_p u axi_c2c_phy_clk Min Period ,;2[21"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period ,;2[21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period ,;2[21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period ,;2[21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period ,;2[21"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period >D2[2^0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_rd_clk/stg5_reg_srl2/CLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period >D2[2^0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_rd_clk/stg30_reg_srl27/CLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period >D2[2^0"fbi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/lane_init_sm_i/SRLC32E_inst_0/CLK*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period tR2[2.0"d`i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/FSM_RESETDONE_j_reg/C*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O Min Period tR2[2.0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C*n/a2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O" Low 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O* High 111ׂ0"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O2i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK" @ 0B{/~m0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Slow2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O2i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK" HR0#/={0"i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Fast2 axi_c2c_phy_clkLA@"uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O  tx_wordclk_dcmw Min Periodi @120"tx_wordclk_bufg/I*n/a2< tx_wordclk_dcmA@"fabric_clk_MMCM/CLKOUT1} Min Periodo 12w̫0"fabric_clk_MMCM/CLKOUT1*n/a2< tx_wordclk_dcmA@"fabric_clk_MMCM/CLKOUT1  DRPclk_dcmo Min Perioda *2w̫20"i_DRPclk_bufg/I*n/a26 DRPclk_dcmA A"i_clk125_MMCM/CLKOUT0u Min Periodg 2w̫2w̫0"i_clk125_MMCM/CLKOUT0*n/a26 DRPclk_dcmA A"i_clk125_MMCM/CLKOUT0 , fabric_clk Min Period Z2V2je1"c_SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"c_SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"c_SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"c_SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"c_SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"c_SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O  fabric_clk_dcmw Min Periodi -2V20"fabric_clk_bufg/I*n/a2< fabric_clk_dcmAGA"fabric_clk_MMCM/CLKOUT0} Min Periodo @2V2w̫0"fabric_clk_MMCM/CLKOUT0*n/a2< fabric_clk_dcmAGA"fabric_clk_MMCM/CLKOUT0 fabric_clk_in Min Periods @2V2w̫0"fabric_clk_MMCM/CLKIN1*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Period{ 2V2.0""i_tcds2_if/BC0_early_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodz 2V2.0"!i_tcds2_if/BC0_late_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Period| 2V2.0"#i_tcds2_if/BC0_onTime_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodz 2V2.0"!i_tcds2_if/EvCntRes_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodz 2V2.0"!i_tcds2_if/QIEreset_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodu 2V2.0"i_tcds2_if/WTE_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periods 2V2.0"i_tcds2_if/WTE_i_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodu 2V2.0"i_tcds2_if/bcnt_reg[0]/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodv 2V2.0"i_tcds2_if/bcnt_reg[10]/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O"{ Lowt V1VV2V1"fabric_clk_MMCM/CLKIN1*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O"{ Lowt V1VV2V1"fabric_clk_MMCM/CLKIN1*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./".*i_tcds2_if/prbs_checker/data_r2_reg[114]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./".*i_tcds2_if/prbs_checker/data_r2_reg[115]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./"-)i_tcds2_if/prbs_checker/data_r2_reg[74]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./"-)i_tcds2_if/prbs_checker/data_r2_reg[75]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./"-)i_tcds2_if/prbs_checker/data_r2_reg[82]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./"-)i_tcds2_if/prbs_checker/data_r2_reg[83]/C*Slow2A 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Q2VV2./"i_tcds2_if/bcnt_reg[2]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O*~ Highv Q2VV2./"i_tcds2_if/bcnt_reg[3]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O*~ Highv Q2VV2./"i_tcds2_if/bcnt_reg[5]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O 0 ipb_clk Min Period A3_p 31"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"{wSFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"{wSFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period 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ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"tpSFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"tpSFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"tpSFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"{wSFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"tpSFP_GEN[7].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"tpSFP_GEN[1].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"{wSFP_GEN[1].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"uqSFP_GEN[40].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"vrSFP_GEN[40].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"}ySFP_GEN[40].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"}ySFP_GEN[40].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"|xSFP_GEN[40].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"tpSFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O  ipb_clk_dcmq Min Periodc r3_p 30"i_ipb_clk_bufg/I*n/a27 ipb_clk_dcmBA"i_clk125_MMCM/CLKOUT2v Min Periodh 3_p 3w̫0"i_clk125_MMCM/CLKOUT2*n/a27 ipb_clk_dcmBA"i_clk125_MMCM/CLKOUT28 Iq (08@HPX`hp Pulse Width Reportns"MHz(0:  ReportPulse Width Report  Design ngFEC_top ^ PartVDevice=xcku115 Package=flva2104 Speed=-1 (PRODUCTION 1.26 12-04-2018) Temperature=C T VersionIVivado v2020.2 (64-bit) SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 DateSat Mar 13 12:29:21 2021Bmin pulse width reporthpx DRPclkDRPclk!)#@13@9A#@I3@eAhq}@c=@23A  rise - rise rise - rise  `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/Ca]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ (CARRY8=4)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu`>}rV94>??c=ԼV>u=u>bx?'1>\?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1] Jnet (fo=2, routed)XhL= kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__30/S[1] JXhzr lhg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__30/CO[7]Prop_CARRY8_SLICEL_S[1]_CO[7] JCARRY8Xhzr= jfg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__30_n_0 Jnet (fo=1, routed)Xh ieg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__30/CI JXhzr lhg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__30/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< jfg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__30_n_0 Jnet (fo=1, routed)Xh jfg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__30/CI JXhzr mig_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__30/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__30_n_0 Jnet (fo=1, routed)Xh jfg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__30/CI JXhzr lhg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__30/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = lhg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__30_n_15 Jnet (fo=1, routed)Xh #< a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C JFDCEXhzr> Jclock pessimismXhԼ _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhr; J arrival timeXh/?/ JXh4 JslackXhc=i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu|?>} ̿{=R??{\=>\=v=u>?'1>H?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_tx_pll_and_datapath_dly Jnet (fo=3, routed)Xh-= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/FSM_sequential_sm_reset_tx[0]_i_1/I3 JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/FSM_sequential_sm_reset_tx[0]_i_1/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrQ8= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx__0[0] Jnet (fo=1, routed)Xho< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/drpclk_in[0] Jnet (fo=4215, routed)XhR?X2Y4 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/drpclk_in[0] Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]/C JFDREXhzr> Jclock pessimismXh>\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh{\=`\g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/Ca]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ (CARRY8=3)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu|>}J İ>P?İ?)#=zj<@>q=u>q?'1>R?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) `\g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8] Jnet (fo=2, routed)Xh9H= kgg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__17/S[0] JXhzr lhg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__17/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8XhzrE= jfg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__17_n_0 Jnet (fo=1, routed)Xh jfg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__17/CI JXhzr mig_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__17/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8Xhzro< kgg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__17_n_0 Jnet (fo=1, routed)Xh jfg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__17/CI JXhzr lhg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__17/O[0]Prop_CARRY8_SLICEM_CI_O[0] JCARRY8XhzrC = lhg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__17_n_15 Jnet (fo=1, routed)Xh #< a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhP?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] `\g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhİ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C JFDCEXhzr> Jclock pessimismXhzj< _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhJ ; J arrival timeXh+?/ JXh4 JslackXh)#=2 fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/FSM_sequential_sm_init_reg[0]/CZVg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuX94>} nĠ=y?n?)=  ף==u>Nbp?'1>Nb?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/FSM_sequential_sm_init_reg[0]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD= QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/sm_init[0] Jnet (fo=7, routed)Xh ף= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_i_1__34/I1 JXhzr ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_i_1__34/OProp_H6LUT_SLICEM_I1_O JLUT6Xhzro= `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_i_1__34_n_0 Jnet (fo=1, routed)Xho< ZVg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xhy?X2Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/FSM_sequential_sm_init_reg[0]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xhn?X2Y4 (CLOCK_ROOT) ZVg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C JFDREXhzr> Jclock pessimismXh  XTg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_regHold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXhp?/ JXh4 JslackXh)= YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg/CYUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu>}:HếL[=@5?H?-=.%=E=u>~?'1>Ԙ?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg/QProp_CFF2_SLICEM_C_Q JFDREXhzrD= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg_n_0 Jnet (fo=4, routed)Xh-= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_i_1__10/I1 JXhzr ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_i_1__10/OProp_A6LUT_SLICEM_I1_O JLUT6Xhzru< _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_i_1__10_n_0 Jnet (fo=1, routed)XhD< YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh@5?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)XhH?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg/C JFDREXhzr> Jclock pessimismXh. WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_regHold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh:; J arrival timeXh?/ JXh4 JslackXh-=i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuD>} ̿{=R??\/=>\=X9=u>?'1>H?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/QProp_EFF_SLICEL_C_Q JFDREXhzf9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_tx_pll_and_datapath_dly Jnet (fo=3, routed)Xh-= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/FSM_sequential_sm_reset_tx[1]_i_1/I1 JXhzf i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/FSM_sequential_sm_reset_tx[1]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT4XhzrGa= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx__0[1] Jnet (fo=1, routed)XhX94< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/drpclk_in[0] Jnet (fo=4215, routed)XhR?X2Y4 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/drpclk_in[0] Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]/C JFDREXhzr> Jclock pessimismXh>\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXhK?/ JXh4 JslackXh\/= XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg/CXTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu >}¿f=E??6=+o=v=u>P?'1>a?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg/QProp_CFF2_SLICEM_C_Q JFDREXhzrD= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg_n_0 Jnet (fo=4, routed)Xhw= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_i_1__19/I1 JXhzr \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_i_1__19/OProp_B6LUT_SLICEM_I1_O JLUT6Xhzro< ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_i_1__19_n_0 Jnet (fo=1, routed)Xhu< XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/aurora_init_clk Jnet (fo=4215, routed)XhE?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg/C JFDREXhzr> Jclock pessimismXh+ VRg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_regHold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh6^?/ JXh4 JslackXh6= a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CPLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu/>}j٪Jގ=??M9=iv=v=u>bx?'1>\?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/QProp_CFF_SLICEM_C_Q JFDCEXhzfD= _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18] Jnet (fo=3, routed)Xh-= UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_i_1__24/I1 JXhzf TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_i_1__24/OProp_D6LUT_SLICEL_I1_O JLUT6Xhzr< VRg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_i_1__24_n_0 Jnet (fo=1, routed)Xho< PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg/D JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT) PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg/C JFDPEXhzr> Jclock pessimismXhi NJg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_regHold_DFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXhj٪; J arrival timeXhף?/ JXh4 JslackXhM9= zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/Cxtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZj)DRPclk rise@0.000ns - DRPclk rise@0.000nsu/>}@Wq=-?W?|9=D=l=u>t?'1> ?a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/QProp_CFF2_SLICEM_C_Q JFDPEXhzrD= tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3 Jnet (fo=1, routed)Xhl= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xh-?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhW?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regHold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh@; J arrival timeXhd?/ JXh4 JslackXh|9= XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg/CYUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu-2>}8  R=!? ?rQ==Zv==u>g?'1>?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg/QProp_CFF_SLICEL_C_Q JFDREXhzrD= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg_n_0 Jnet (fo=3, routed)XhT= ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_i_1__0/I3 JXhzr \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_i_1__0/OProp_B6LUT_SLICEL_I3_O JLUT6Xhzr< ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_i_1__0_n_0 Jnet (fo=1, routed)Xhu< YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh!?X2Y4 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh ?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C JFDREXhzr> Jclock pessimismXhZ WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_regHold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh8 ; J arrival timeXh?/ JXh4 JslackXhrQ==XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg/CUQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg/D"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu(@}AAq=Jl%>O@q=J@A =А=k>A8Hs>T>c@t3?o#@A`%?a @a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDSE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfI > ZVg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg_n_0 Jnet (fo=4, routed)Xhz? ZVg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_2__16/I1 JXhzf YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_2__16/OProp_G6LUT_SLICEL_I1_O JLUT6Xhzr`P= OKg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr Jnet (fo=1, routed)Xhgf@ ZVg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_1__16/I1 JXhzr YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_1__16/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzrˡ> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_1__16_n_0 Jnet (fo=1, routed)Xh~j<= UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg/D JFDSEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/aurora_init_clk Jnet (fo=4215, routed)XhO@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/aurora_init_clk Jnet (fo=4215, routed)Xhq=J@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg/C JFDSEXhzr> Jclock pessimismXh8Hs>@ Jclock uncertaintyXh  SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_regSetup_HFF2_SLICEL_C_D JFDSEXho=/ JXh< J required timeXhA; J arrival timeXh / JXh4 JslackXhADa]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Cb^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu*N@}A2҃AV>c?(@t3?7@A`%?ף @a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzfV> _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] Jnet (fo=2, routed)Xh? eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/I2 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/OProp_A6LUT_SLICEL_I2_O JLUT4Xhzr> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 Jnet (fo=1, routed)Xhrh= eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/I2 JXhzr d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/OProp_C6LUT_SLICEL_I2_O JLUT6XhzfX9= fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 Jnet (fo=2, routed)Xh-> eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/I1 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrMb> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 Jnet (fo=26, routed)Xh%a? b^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhd@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhI@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh  _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh2҃AV>c?(@t3?7@A`%?ף @a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzfV> _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] Jnet (fo=2, routed)Xh? eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/I2 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/OProp_A6LUT_SLICEL_I2_O JLUT4Xhzr> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 Jnet (fo=1, routed)Xhrh= eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/I2 JXhzr d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/OProp_C6LUT_SLICEL_I2_O JLUT6XhzfX9= fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 Jnet (fo=2, routed)Xh-> eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/I1 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrMb> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 Jnet (fo=26, routed)Xh%a? b^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhd@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhI@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh  _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhA9>c?&@t3?7@A`%?c @a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzfV> _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] Jnet (fo=2, routed)Xh? eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/I2 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/OProp_A6LUT_SLICEL_I2_O JLUT4Xhzr> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 Jnet (fo=1, routed)Xhrh= eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/I2 JXhzr d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/OProp_C6LUT_SLICEL_I2_O JLUT6XhzfX9= fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 Jnet (fo=2, routed)Xh-> eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/I1 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrMb> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 Jnet (fo=26, routed)XhY? b^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhd@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhshI@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/C JFDCEXhzr> Jclock pessimismXh9>@ Jclock uncertaintyXh  _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhϺA; J arrival timeXhj/ JXh4 JslackXhADa]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Cb^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuL@}AϺAshId@shI@A =А=k>A9>c?&@t3?7@A`%?c @a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzfV> _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] Jnet (fo=2, routed)Xh? eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/I2 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/OProp_A6LUT_SLICEL_I2_O JLUT4Xhzr> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 Jnet (fo=1, routed)Xhrh= eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/I2 JXhzr d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/OProp_C6LUT_SLICEL_I2_O JLUT6XhzfX9= fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 Jnet (fo=2, routed)Xh-> eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/I1 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrMb> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 Jnet (fo=26, routed)XhY? b^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhd@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhshI@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/C JFDCEXhzr> Jclock pessimismXh9>@ Jclock uncertaintyXh  _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhϺA; J arrival timeXhj/ JXh4 JslackXhADa]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Cb^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuL@}AϺAshId@shI@A =А=k>A9>c?&@t3?7@A`%?c @a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzfV> _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] Jnet (fo=2, routed)Xh? eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/I2 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/OProp_A6LUT_SLICEL_I2_O JLUT4Xhzr> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 Jnet (fo=1, routed)Xhrh= eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/I2 JXhzr d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/OProp_C6LUT_SLICEL_I2_O JLUT6XhzfX9= fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 Jnet (fo=2, routed)Xh-> eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/I1 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrMb> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 Jnet (fo=26, routed)XhY? b^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhd@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhshI@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/C JFDCEXhzr> Jclock pessimismXh9>@ Jclock uncertaintyXh  _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhϺA; J arrival timeXhj/ JXh4 JslackXhADa]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Cb^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuL@}AϺAshId@shI@A =А=k>A9>c?&@t3?7@A`%?c @a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzfV> _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] Jnet (fo=2, routed)Xh? eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/I2 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/OProp_A6LUT_SLICEL_I2_O JLUT4Xhzr> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 Jnet (fo=1, routed)Xhrh= eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/I2 JXhzr d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/OProp_C6LUT_SLICEL_I2_O JLUT6XhzfX9= fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 Jnet (fo=2, routed)Xh-> eag_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/I1 JXhzf d`g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrMb> fbg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 Jnet (fo=26, routed)XhY? b^g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)Xhd@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk Jnet (fo=4215, routed)XhshI@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]/C JFDCEXhzr> Jclock pessimismXh9>@ Jclock uncertaintyXh  _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhϺA; J arrival timeXhj/ JXh4 JslackXhA<YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/CYUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuH@}A{ܷA3Y1L@3@A =А=k>KAu> >1,@t3?+@A`%?n @a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/QProp_AFF_SLICEM_C_Q JFDREXhzf)\> WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16] Jnet (fo=4, routed)Xh k? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/I5 JXhzf [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzre;_> ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1_n_0 Jnet (fo=1, routed)Xh> W? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/I1 JXhzr [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/OProp_E6LUT_SLICEL_I1_O JLUT3Xhzr-= OKg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr Jnet (fo=25, routed)Xhzn? YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]/CE JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1L@X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh3@X2Y4 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]/C JFDREXhzr> Jclock pessimismXhu>@ Jclock uncertaintyXh  VRg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh{ܷA; J arrival timeXhE/ JXh4 JslackXhKA<YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/CYUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuH@}A{ܷA3Y1L@3@A =А=k>KAu> >1,@t3?+@A`%?n @a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/QProp_AFF_SLICEM_C_Q JFDREXhzf)\> WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16] Jnet (fo=4, routed)Xh k? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/I5 JXhzf [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzre;_> ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1_n_0 Jnet (fo=1, routed)Xh> W? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/I1 JXhzr [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/OProp_E6LUT_SLICEL_I1_O JLUT3Xhzr-= OKg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr Jnet (fo=25, routed)Xhzn? YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]/CE JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1L@X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh3@X2Y4 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]/C JFDREXhzr> Jclock pessimismXhu>@ Jclock uncertaintyXh  VRg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]Setup_FFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh{ܷA; J arrival timeXhE/ JXh4 JslackXhKA<YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/CYUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]/CE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuH@}A{ܷA3Y1L@3@A =А=k>KAu> >1,@t3?+@A`%?n @a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/QProp_AFF_SLICEM_C_Q JFDREXhzf)\> WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16] Jnet (fo=4, routed)Xh k? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/I5 JXhzf [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzre;_> ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1_n_0 Jnet (fo=1, routed)Xh> W? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/I1 JXhzr [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/OProp_E6LUT_SLICEL_I1_O JLUT3Xhzr-= OKg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr Jnet (fo=25, routed)Xhzn? YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]/CE JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1L@X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh3@X2Y4 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]/C JFDREXhzr> Jclock pessimismXhu>@ Jclock uncertaintyXh  VRg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh{ܷA; J arrival timeXhE/ JXh4 JslackXhKA" gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]!)y@1y @9Ay@Iy @eg@hq} c= > rise - rise rise - rise  ag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C)%SFP_GEN[0].rx_data_ngccm_reg[0][79]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuD>}(B`ſz=Q?B`?c=q9H=n>*??|??&!?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[0][79] Jnet (fo=1, routed)Xhn>[ )%SFP_GEN[0].rx_data_ngccm_reg[0][79]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)XhA?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][79]/C JFDCEXhzr> Jclock pessimismXhqr '#SFP_GEN[0].rx_data_ngccm_reg[0][79]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh(; J arrival timeXha?/ JXh4 JslackXhc=kg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu^d;>}tXɿ=b?X?8,=d3=E=*?+?|??(?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhd3 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXht; J arrival timeXh|?/ JXh4 JslackXh8,=_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C)%SFP_GEN[0].rx_data_ngccm_reg[0][45]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuQ8>}&ɿ='1??0=d39H=$>*?l?|??r(?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=U rx_data[0][45] Jnet (fo=1, routed)Xh$>[ )%SFP_GEN[0].rx_data_ngccm_reg[0][45]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][45]/C JFDCEXhzr> Jclock pessimismXhd3r '#SFP_GEN[0].rx_data_ngccm_reg[0][45]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh&; J arrival timeXhe;?/ JXh4 JslackXh0=Yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C($SFP_GEN[0].rx_data_ngccm_reg[0][5]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuUb>}Weʿ '= ??5=w1TD=v=*?W ?|??+?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=T  rx_data[0][5] Jnet (fo=1, routed)Xhv=Z ($SFP_GEN[0].rx_data_ngccm_reg[0][5]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xhˡ?X3Y0 (CLOCK_ROOT)Z ($SFP_GEN[0].rx_data_ngccm_reg[0][5]/C JFDCEXhzr> Jclock pessimismXhw1Tq &"SFP_GEN[0].rx_data_ngccm_reg[0][5]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhWe; J arrival timeXhW?/ JXh4 JslackXh5=_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C)%SFP_GEN[0].rx_data_ngccm_reg[0][71]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuD>}ԸǿX=??g\8=\#0D=t>*?o?|??ˡ%?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[0][71] Jnet (fo=1, routed)Xht>[ )%SFP_GEN[0].rx_data_ngccm_reg[0][71]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh\?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][71]/C JFDCEXhzr> Jclock pessimismXh\#0r '#SFP_GEN[0].rx_data_ngccm_reg[0][71]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhԸ; J arrival timeXh?/ JXh4 JslackXhg\8=ag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C)%SFP_GEN[0].rx_data_ngccm_reg[0][33]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu>}K iͿJ=?i?^:=zT9H==*?Pb?|??th1?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[0][33] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[0].rx_data_ngccm_reg[0][33]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][33]/C JFDCEXhzr> Jclock pessimismXhzTr '#SFP_GEN[0].rx_data_ngccm_reg[0][33]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhK ; J arrival timeXh<߿?/ JXh4 JslackXh^:=vg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu~>} Xɿ1>$?X?zj<=qʡ={.>*?S?|??(?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[0] Jnet (fo=2, routed)XhR> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/OProp_B6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh= ?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhq g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXhzj<=sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT5=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuT>}@Ϳgi5=j??kC=_^=/]=*?<?|??-2?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzf9H= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh= ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0[20]_i_1__1/I1 JXhzf hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0[20]_i_1__1/OProp_C6LUT_SLICEL_I1_O JLUT5XhzrQ8= `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg00[20] Jnet (fo=1, routed)Xho< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhO?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhԸ?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzr> Jclock pessimismXh_^ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh@; J arrival timeXh*\?/ JXh4 JslackXhkC=)%SFP_GEN[0].rx_data_ngccm_reg[0][44]/C/+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsut>}mxɿ#=Ԩ?x?(D=W;\=L=*?;?|??L7)?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)v )%SFP_GEN[0].rx_data_ngccm_reg[0][44]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=u 2.g_gbt_bank[0].gbtbank/RX_Word_rx40_reg[78][20] Jnet (fo=1, routed)XhC =_ 1-g_gbt_bank[0].gbtbank/RX_Word_rx40[44]_i_1/I1 JXhzr 0,g_gbt_bank[0].gbtbank/RX_Word_rx40[44]_i_1/OProp_C6LUT_SLICEL_I1_O JLUT3XhzrQ8=v 3/SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] Jnet (fo=1, routed)Xho<a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh_?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][44]/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXhW;\w -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhm; J arrival timeXhC?/ JXh4 JslackXh(D=Zg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C($SFP_GEN[0].rx_data_ngccm_reg[0][6]/D"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu!>}*iͿV=I?i?K=xTD=G=*??|??th1?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=T  rx_data[0][6] Jnet (fo=1, routed)XhG=Z ($SFP_GEN[0].rx_data_ngccm_reg[0][6]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT)Z ($SFP_GEN[0].rx_data_ngccm_reg[0][6]/C JFDCEXhzr> Jclock pessimismXhxTq &"SFP_GEN[0].rx_data_ngccm_reg[0][6]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh*; J arrival timeXh?/ JXh4 JslackXhK=Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT5=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuI@}AL-;AHJ+@HJ@A=А=g@h>$?e@#?^@r?5^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh@> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr1,> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh"? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhsh1@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhL-;A; J arrival timeXhrh/ JXh4 JslackXhg@ Vg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT5=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu(@}Ac1;AHJ+@HJ@A=А=Qe@h>$?}?e@#?^@r?5^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh@> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr1,> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhsh1@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhc1;A; J arrival timeXhX/ JXh4 JslackXhQe@ 3!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=2 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuV@}Af;AK+@K@A=А=@$@WV>M?Z@#?^@r?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/I2 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 Jnet (fo=1, routed)Xh1= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/I5 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 Jnet (fo=2, routed)Xhk> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM2@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhWV>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhf;A; J arrival timeXh@5/ JXh4 JslackXh@$@ 3!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=2 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuV@}Af;AK+@K@A=А=@$@WV>M?Z@#?^@r?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/I2 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 Jnet (fo=1, routed)Xh1= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/I5 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 Jnet (fo=2, routed)Xhk> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM2@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhWV>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhf;A; J arrival timeXh@5/ JXh4 JslackXh@$@ Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT5=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu@}Aj:A#I+@#I@A=А=c)@}>$?-Z@#?^@r?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh@> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr1,> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhMb0@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh}>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhj:A; J arrival timeXht/ JXh4 JslackXhc)@ Vg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT5=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu~@}A:A#I+@#I@A=А=)@}>$?Y@#?^@r?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh@> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr1,> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> > tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhMb0@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh}>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh:A; J arrival timeXh/ JXh4 JslackXh)@ Vg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT5=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu~@}A:A#I+@#I@A=А=)@}>$?Y@#?^@r?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh@> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr1,> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> > tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhMb0@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh}>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh:A; J arrival timeXh/ JXh4 JslackXh)@ sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu@}Av9;AoK9+@oK@A=А={,@d> ?Y@#?^@r??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzfA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhv9;A; J arrival timeXhW9/ JXh4 JslackXh{,@ sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu@}Av9;AoK9+@oK@A=А={,@d> ?Y@#?^@r??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzfA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhv9;A; J arrival timeXhW9/ JXh4 JslackXh{,@ rg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuҝ@}A=;AoK9+@oK@A=А=A,@d> ?^Y@#?^@r??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] Jnet (fo=10, routed)Xh 3@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I2 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_C6LUT_SLICEL_I2_O JLUT4XhzfA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh > xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhf@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh=;A; J arrival timeXh-/ JXh4 JslackXhA,@ &  gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1!)y@1y @9Ay@Iy @e_@hq} &=  > rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*&SFP_GEN[10].rx_data_ngccm_reg[10][0]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu5,>}"sT=?5?"?&=YBD==X9>?x ?]"?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=U rx_data[10][0] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[10].rx_data_ngccm_reg[10][0]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)\ *&SFP_GEN[10].rx_data_ngccm_reg[10][0]/C JFDCEXhzr> Jclock pessimismXhYBr ($SFP_GEN[10].rx_data_ngccm_reg[10][0]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhF?/ JXh4 JslackXh&=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsut>}@5gi5=;ߏ?@5?K 3=UE=L=X9>l?x ?;(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__9/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__9/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĀ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhUE g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXhK 3=p0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/CB>SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu:A>}.=َ?.?d==m9H=*\>X9>B`?x ?'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)~ 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= EASFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] Jnet (fo=1, routed)Xh*\>t B>SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|?X4Y2 (CLOCK_ROOT)b 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT)t B>SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C JFDREXhzr> Jclock pessimismXhm @}k}{ƖV=?{?C=>=5^=X9>y?x ?r(?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_0 Jnet (fo=4, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/g_rx_rs_err[10].rx_rs_err_cnt[10]_i_1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/g_rx_rs_err[10].rx_rs_err_cnt[10]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzro<b g_gbt_bank[0].gbtbank_n_153 Jnet (fo=1, routed)Xho<] +'g_rx_rs_err[10].rx_rs_err_cnt_reg[10]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)] +'g_rx_rs_err[10].rx_rs_err_cnt_reg[10]/C JFDREXhzr> Jclock pessimismXh>s )%g_rx_rs_err[10].rx_rs_err_cnt_reg[10]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhk}; J arrival timeXh?/ JXh4 JslackXhC=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuz>}s3.K?)=v?.?KC=ME=`P=X9>+?x ?'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__9/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__9/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhME g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhs3; J arrival timeXhM?/ JXh4 JslackXhKC=l>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsui;=}:v֣;a?v?D=lgo=Q8=X9>x ?x ?L7)?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[3] Jnet (fo=9, routed)Xh+= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][3]_i_1/I0 JXhzr rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][3]_i_1/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru<m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_358 Jnet (fo=1, routed)XhD<p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xhʁ?X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)XhX?X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr> Jclock pessimismXhlg <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh:; J arrival timeXhٞ?/ JXh4 JslackXhD= h0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[17]/CGCSFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu #>}/>c=V?/?F==9H=S=X9>Z?x ?&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)~ 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[17]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=p -)SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/Q[1] Jnet (fo=5, routed)XhS=y GCSFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X4Y2 (CLOCK_ROOT)b 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[10].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)y GCSFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/C JFDREXhzr> Jclock pessimismXh= EASFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhТ?/ JXh4 JslackXhF=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu)>}󭿭o,=|??G=wH=Y=X9>?x ?'1(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__9/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__9/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNb?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhwH g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXhG=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[10].rx_data_ngccm_reg[10][68]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuR%>}מ*\Oi=Mb?*\?H="{=9H=l=X9>r?x ?+?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[10][68] Jnet (fo=1, routed)Xhl=] +'SFP_GEN[10].rx_data_ngccm_reg[10][68]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xhq=?X4Y2 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][68]/C JFDCEXhzr> Jclock pessimismXh"{=s )%SFP_GEN[10].rx_data_ngccm_reg[10][68]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhמ; J arrival timeXh?/ JXh4 JslackXhH=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu)>}7Tҭl?x ?'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__9/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__9/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĀ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhME g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh7T; J arrival timeXh!?/ JXh4 JslackXh.}K=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuZ@}Aک3Aw/>_{N@w/@A=А=_@>?3@-?/?A`?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/I2 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 Jnet (fo=1, routed)Xh!> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/I5 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/OProp_D6LUT_SLICEM_I5_O JLUT6XhzrGa= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE@X4Y2 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhک3A; J arrival timeXhZd/ JXh4 JslackXh_@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@}A3A/:^{N@/@A=А=i.e@>?v.@-?/?A`?K?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/I2 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 Jnet (fo=1, routed)Xh!> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/I5 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/OProp_D6LUT_SLICEM_I5_O JLUT6XhzrGa= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 Jnet (fo=2, routed)XhD> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV@X4Y2 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXhi.e@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu}?@}A3A/q3\{N@/@A=А=Dn@. >*?e;/@-?/?A`?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh9H> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X4Y2 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh. >@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXhI/ JXh4 JslackXhDn@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu}?@}A3A/q3\{N@/@A=А=Dn@. >*?e;/@-?/?A`?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh9H> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X4Y2 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh. >@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXhI/ JXh4 JslackXhDn@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu&@}A3A/q3\{N@/@A=А=#n@. >*?> /@-?/?A`?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh9H> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X4Y2 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh. >@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh3A; J arrival timeXh'1/ JXh4 JslackXh#n@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@}A3A(\?1@-?/?A`?l?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__10/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__10/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh33? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y2 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh3A; J arrival timeXhE/ JXh4 JslackXh**o@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsus@}A3A(\?x1@-?/?A`?l?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__10/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__10/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhn? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y2 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXhzo@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@}A3A|/"Lc{N@|/@A=А=,s@\>K?)@-?/?A`?罹?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzf"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh }yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/I0 JXhzf |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXh-/ JXh4 JslackXh,s@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@}A3A|/"Lc{N@|/@A=А=,s@\>K?)@-?/?A`?罹?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzf"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh }yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/I0 JXhzf |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXh-/ JXh4 JslackXh,s@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu\@}A3A|/"Lc{N@|/@A=А=Cs@\>K?x)@-?/?A`?罹?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhx@ qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I2 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzf"y> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh }yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/I0 JXhzf |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhb> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXhCs@ ( !gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!)y@1y @9Ay@Iy @eZkQ@hq}  = > rise - rise rise - rise  eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[23]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu5,>}~y閿n=tx?y? =AD==G>^ ?µ>9(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[23]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[23] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh5^Z?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]/C JFDCEXhzr> Jclock pessimismXhA c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh~; J arrival timeXhʑ?/ JXh4 JslackXh =g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}iWȖV=zt?Ȗ?=n=5^=G>ˡ?µ>r(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__7/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__7/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXhn g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhiW; J arrival timeXh?/ JXh4 JslackXh=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu]B>}A,=r?,?=f= =G>?µ>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister[1] Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__7/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__7/OProp_D5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhkT?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhsh?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhf g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhA; J arrival timeXhʑ?/ JXh4 JslackXh=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuv>>}t􌿍gf=zt?gf?"==j=G>ˡ?µ>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__7/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__7/OProp_H6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXht􌿐; J arrival timeXhJ ?/ JXh4 JslackXh"=mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[0]/Cmig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuX94>}ͪ1=u??ô7=fʡ==G>y?µ>%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[0]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD= XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/timer[0] Jnet (fo=7, routed)XhT= qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[1]_i_1__8/I0 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[1]_i_1__8/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzr< rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[1]_i_1__8_n_0 Jnet (fo=1, routed)Xho< mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhPW?X4Y3 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[0]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C JFDREXhzr> Jclock pessimismXhf kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhͪ; J arrival timeXhsh?/ JXh4 JslackXhô7=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsut>}tffQ,=u?ff?ay;=0=L=G>y?µ>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__7/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__7/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPW?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh0 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXht; J arrival timeXhO?/ JXh4 JslackXhay;=)%SFP_GEN[8].rx_data_ngccm_reg[8][25]/C/+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu]B>}A=X9t??;=D=sh>G>B`?µ>y&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)w )%SFP_GEN[8].rx_data_ngccm_reg[8][25]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD=v 3/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[83]_0[17] Jnet (fo=1, routed)Xhsh>a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[8] Jnet (fo=674, routed)XhV?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][25]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXhx -)SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhn?/ JXh4 JslackXh;=)%SFP_GEN[8].rx_data_ngccm_reg[8][27]/C/+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu]B>}A=X9t??;=D=rh>G>B`?µ>y&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)w )%SFP_GEN[8].rx_data_ngccm_reg[8][27]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrD=v 3/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[83]_0[19] Jnet (fo=1, routed)Xhrh>a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[8] Jnet (fo=674, routed)XhV?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][27]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXhx -)SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhn?/ JXh4 JslackXh;=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C)%SFP_GEN[8].rx_data_ngccm_reg[8][52]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu +>}zOm=? w?z?Q;=f9H==G>'1?µ> #?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[8][52] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[8].rx_data_ngccm_reg[8][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[8] Jnet (fo=674, routed)XhQ~?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][52]/C JFDCEXhzr> Jclock pessimismXhfq '#SFP_GEN[8].rx_data_ngccm_reg[8][52]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXha?/ JXh4 JslackXhQ;=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C($SFP_GEN[8].rx_data_ngccm_reg[8][6]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuC>}+ˡt=53s?ˡ?L <=!D=n>G>Z?µ>$&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=T  rx_data[8][6] Jnet (fo=1, routed)Xhn>Z ($SFP_GEN[8].rx_data_ngccm_reg[8][6]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhT?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)Z ($SFP_GEN[8].rx_data_ngccm_reg[8][6]/C JFDCEXhzr> Jclock pessimismXh!p &"SFP_GEN[8].rx_data_ngccm_reg[8][6]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh+; J arrival timeXhK ?/ JXh4 JslackXhL <=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuٖ@}A,A+|w4@+@A=А=ZkQ@|a>Mb?E@9??'?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 Jnet (fo=1, routed)Xh1= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 Jnet (fo=2, routed)Xh<> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh|a>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh,A; J arrival timeXha/ JXh4 JslackXhZkQ@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuٖ@}A,A+|w4@+@A=А=ZkQ@|a>Mb?E@9??'?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 Jnet (fo=1, routed)Xh1= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 Jnet (fo=2, routed)Xh<> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh|a>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh,A; J arrival timeXha/ JXh4 JslackXhZkQ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuQ@}A"-A[e4@@A=А=\_@La>?+G@9??'?s?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhLa>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh"-A; J arrival timeXh5^/ JXh4 JslackXh\_@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu'1@}Al-A[e4@@A=А=_@La>?yF@9??'?s?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhLa>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhl-A; J arrival timeXhq=/ JXh4 JslackXh_@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu@}Az,AyWq4@y@A=А=Mg@[la>?v>@9??'?< ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh[la>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhz,A; J arrival timeXh/ JXh4 JslackXhMg@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu ׋@}A,AyWq4@y@A=А=hg@[la>?@5>@9??'?< ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh7> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh[la>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXhT/ JXh4 JslackXhhg@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu ׋@}A,AyWq4@y@A=А=hg@[la>?@5>@9??'?< ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh7> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh[la>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXhT/ JXh4 JslackXhhg@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu @}Al,Ar4@@A=А=)i@na>?S>@9??'?w?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__8/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__8/OProp_H6LUT_SLICEM_I0_O JLUT6XhzrGa= b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh\> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhna>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhl,A; J arrival timeXhW/ JXh4 JslackXh)i@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu"@}A,A= N~o4@= @A=А=IIi@ga>?<@9??'?K?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhga>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh// JXh4 JslackXhIIi@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu @}A,A= N~o4@= @A=А=1i@ga>?D<@9??'?K?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhX9> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhga>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXhW/ JXh4 JslackXh1i@ ( !gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!)y@1y @9Ay@Iy @eI@hq} Z#=  >  rise - rise rise - rise  }g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][82]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu">}!= -r?!?Z#=\D=S=Ġ>?µ>A ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/QProp_GFF_SLICEM_C_Q JFDREXhzrD=U rx_data[9][82] Jnet (fo=1, routed)XhS=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][82]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh"{?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][82]/C JFDCEXhzr> Jclock pessimismXh\q '#SFP_GEN[9].rx_data_ngccm_reg[9][82]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhp?/ JXh4 JslackXhZ#=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu/>}1_t=o??='#'=`P=Ġ>?µ>o#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__8/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__8/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr/]= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhaP?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh'#' g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh1_; J arrival timeXhC?/ JXh4 JslackXh=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu #>}1_t=o??5='#'l=@=Ġ>?µ>o#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__8/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__8/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzro= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhaP?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh'#' g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh1_; J arrival timeXh1?/ JXh4 JslackXh5=V<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuP>}\Yi5={n?\?kC=.v=Ga=Ġ>>µ>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt_reg[9][7]_0[0] Jnet (fo=10, routed)Xhw= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt[9][1]_i_1/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt[9][1]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT6XhzrQ8=m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_345 Jnet (fo=1, routed)Xho<n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)XhGz?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C JFDCEXhzr> Jclock pessimismXh. :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhkC= {g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][46]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsut>}pM"=أp?M?HI=:'9H=[=Ġ>J ?µ>|?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[9][46] Jnet (fo=1, routed)Xh[=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][46]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhnR?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh5^z?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][46]/C JFDCEXhzr> Jclock pessimismXh:'r '#SFP_GEN[9].rx_data_ngccm_reg[9][46]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhp; J arrival timeXh?/ JXh4 JslackXhHI=~g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][54]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuw>} ]Ҿ+=أp?]?^GU=&9H==Ġ>J ?µ> ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[9][54] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][54]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhnR?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhIz?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][54]/C JFDCEXhzr> Jclock pessimismXh&r '#SFP_GEN[9].rx_data_ngccm_reg[9][54]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh ; J arrival timeXh[d?/ JXh4 JslackXh^GU=W<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu>}\Yi5={n?\?W=.=L=Ġ>>µ>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt_reg[9][7]_0[0] Jnet (fo=10, routed)Xhw= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt[9][2]_i_1/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt[9][2]_i_1/OProp_C5LUT_SLICEL_I3_O JLUT5XhzrGa=m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_344 Jnet (fo=1, routed)XhX94<n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)XhGz?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C JFDCEXhzr> Jclock pessimismXh. :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhW= ,(SFP_GEN[9].ngccm_status_reg_reg[9][24]/C,(SFP_GEN[9].ngccm_status_reg_reg[9][24]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsul=}> OF;*\?O?vY=ko=9H=Ġ> 0?µ>U?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)y ,(SFP_GEN[9].ngccm_status_reg_reg[9][24]/QProp_FFF_SLICEL_C_Q JFDPEXhzr9H= D@SFP_GEN[9].ngCCM_gbt/SFP_GEN[9].ngccm_status_reg_reg[9][24]_0[8] Jnet (fo=2, routed)XhP=p B>SFP_GEN[9].ngCCM_gbt/SFP_GEN[9].ngccm_status_reg[9][24]_i_2/I0 JXhzr A=SFP_GEN[9].ngCCM_gbt/SFP_GEN[9].ngccm_status_reg[9][24]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT2Xhzru<a SFP_GEN[9].ngCCM_gbt_n_393 Jnet (fo=1, routed)XhD<^ ,(SFP_GEN[9].ngccm_status_reg_reg[9][24]/D JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhA?X4Y3 (CLOCK_ROOT)^ ,(SFP_GEN[9].ngccm_status_reg_reg[9][24]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh'1?X4Y3 (CLOCK_ROOT)^ ,(SFP_GEN[9].ngccm_status_reg_reg[9][24]/C JFDPEXhzr> Jclock pessimismXhkt *&SFP_GEN[9].ngccm_status_reg_reg[9][24]Hold_FFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh> ; J arrival timeXhҝ?/ JXh4 JslackXhvY=]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_reg/Cb^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsul=}(|F;l??Y=L%=L=Ġ>j>µ>l?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzfD= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_to_bitSlipCtrller_9 Jnet (fo=10, routed)Xht= fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_inv_i_1__9/I0 JXhzf eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_inv_i_1__9/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzru< ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)XhA`e< b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhN?X4Y3 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv?X4Y3 (CLOCK_ROOT) b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXhL `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_invHold_GFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh(|; J arrival timeXh/݄?/ JXh4 JslackXhY= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuv>>} В$= p?В?1Z=q=j=Ġ>8?µ> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__8/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__8/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[d{?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhq g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh;ߏ?/ JXh4 JslackXh1Z=s!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuy@}AB,AZrnsh1@Z@A=А=I@rb>?gfF@5^:??(?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhn> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8/OProp_B5LUT_SLICEL_I2_O JLUT4XhzrC> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8_n_0 Jnet (fo=1, routed)Xh/ݤ> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrE= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8_n_0 Jnet (fo=2, routed)Xh-> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhrb>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhB,A; J arrival timeXh/ JXh4 JslackXhI@ s!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu\@}A9N,Azklsh1@z@A=А=J@Imb>?.E@5^:??(?8?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhn> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8/OProp_B5LUT_SLICEL_I2_O JLUT4XhzrC> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8_n_0 Jnet (fo=1, routed)Xh/ݤ> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrE= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8_n_0 Jnet (fo=2, routed)XhD> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhImb>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh9N,A; J arrival timeXhC/ JXh4 JslackXhJ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuL7@}A+ACsh1@C@A=А=%S@b>T?|G@5^:??(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE6? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh%S@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuL7@}A+ACsh1@C@A=А=%S@b>T?|G@5^:??(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE6? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh%S@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu@}A+ACsh1@C@A=А=uNT@b>T?KG@5^:??(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh5? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhuNT@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu@}A+ACsh1@C@A=А=uNT@b>T?KG@5^:??(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh5? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_FFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhuNT@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu@}A+ACsh1@C@A=А=uNT@b>T?KG@5^:??(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh5? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhuNT@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu‘@}A5,A(^}qsh1@(@A=А=[@bzb>T?u@@5^:??(?a?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhbzb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh5,A; J arrival timeXhv/ JXh4 JslackXh[@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu‘@}A5,A(^}qsh1@(@A=А=[@bzb>T?u@@5^:??(?a?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhbzb>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh5,A; J arrival timeXhv/ JXh4 JslackXh[@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu)\@}A\,Azsh1@@A=А=$h@b>S?W5@5^:??(?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhL7 @ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/OProp_B6LUT_SLICEL_I2_O JLUT4XhzfA`> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__9/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__9/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhX9?X4Y3 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh\,A; J arrival timeXhb/ JXh4 JslackXh$h@ &  gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2!)y@1y @9Ay@Iy @e@hq} W= > rise - rise rise - rise  fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuth>}]v@}K=g?v?W="D==>ˡ?">%?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[24] Jnet (fo=1, routed)Xh= fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhxI?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh!r?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXh" d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh]; J arrival timeXh?/ JXh4 JslackXhW=p0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/CHDSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuN%>}=i=L7i?i?!D#=9H=l=>+?">S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)~ 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H=q .*SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/Q[11] Jnet (fo=2, routed)Xhl=z HDSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh K?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhap?X4Y3 (CLOCK_ROOT)z HDSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C JFDREXhzr> Jclock pessimismXh FBSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]Hold_EFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXh=; J arrival timeXhX?/ JXh4 JslackXh!D#=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu/>}d;X='1h?d;?b9=#`=T=>$?">&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__10/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__10/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9t?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh·?/ JXh4 JslackXhb9=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[11].rx_data_ngccm_reg[11][72]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsur>} YvZ_=gff?v?>:=E"D=/=>Z?">%?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[11][72] Jnet (fo=1, routed)Xh/=] +'SFP_GEN[11].rx_data_ngccm_reg[11][72]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh!r?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][72]/C JFDCEXhzr> Jclock pessimismXhE"t )%SFP_GEN[11].rx_data_ngccm_reg[11][72]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh Y; J arrival timeXh+?/ JXh4 JslackXh>:=+'SFP_GEN[11].rx_data_ngccm_reg[11][16]/C0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuJ>}k=Te??;=}9H=t>> ?">l'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)x +'SFP_GEN[11].rx_data_ngccm_reg[11][16]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[83]_0[8] Jnet (fo=1, routed)Xht>b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=m RX_WORDCLK_O[11] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][16]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXh}x .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhk; J arrival timeXhI?/ JXh4 JslackXh;=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[11].rx_data_ngccm_reg[11][63]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuD>}H@5+W=d?@5?`<=D=t>>]?">$?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=V rx_data[11][63] Jnet (fo=1, routed)Xht>] +'SFP_GEN[11].rx_data_ngccm_reg[11][63]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhgfF?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][63]/C JFDCEXhzr> Jclock pessimismXhs )%SFP_GEN[11].rx_data_ngccm_reg[11][63]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhH; J arrival timeXhH?/ JXh4 JslackXh`<=Bg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu%>}ld;.?)=g?d;?.}K=/=Y=>T?">&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__10/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__10/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh^I?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9t?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh/ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhl; J arrival timeXhȆ?/ JXh4 JslackXh.}K=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C+'SFP_GEN[11].rx_data_ngccm_reg[11][50]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu3^:>}N팿^=ˡe?? M=,"9H='1>>?">I "?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[11][50] Jnet (fo=1, routed)Xh'1>] +'SFP_GEN[11].rx_data_ngccm_reg[11][50]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhlG?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xho?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][50]/C JFDCEXhzr> Jclock pessimismXh,"t )%SFP_GEN[11].rx_data_ngccm_reg[11][50]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhN; J arrival timeXh?/ JXh4 JslackXh M=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu">}d;X='1h?d;?M=#A`=@=>$?">&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__10/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__10/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzr%= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[8] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9t?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXhM=4+'SFP_GEN[11].rx_data_ngccm_reg[11][34]/C0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/D"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuw>}%̀|Q,=rh?|?CO=T.=Q8=>gf?">+'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)x +'SFP_GEN[11].rx_data_ngccm_reg[11][34]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] Jnet (fo=1, routed)XhC =_ 1-SFP_GEN[11].ngCCM_gbt/RX_Word_rx40[34]_i_1/I1 JXhzr 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40[34]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3XhzrGa=u 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xhq=J?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][34]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhjt?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXhT.y .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh%̀; J arrival timeXhK?/ JXh4 JslackXhCO=g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[11].rx_data_ngccm_reg[11][41]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu_p@}AS*A_7-@@A=А=@.W>>NbX@v??ף?M?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhy? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[11] Jnet (fo=76, routed)Xh#?^ ,(SFP_GEN[11].rx_data_ngccm_reg[11][41]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][41]/C JFDCEXhzr> Jclock pessimismXh.W>@ Jclock uncertaintyXhv )%SFP_GEN[11].rx_data_ngccm_reg[11][41]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhS*A; J arrival timeXhS/ JXh4 JslackXh@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[11].rx_data_ngccm_reg[11][40]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu7p@}A*A_7-@@A=А=%@.W>>'1X@v??ף?M?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhy? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[11] Jnet (fo=76, routed)Xhx?^ ,(SFP_GEN[11].rx_data_ngccm_reg[11][40]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][40]/C JFDCEXhzr> Jclock pessimismXh.W>@ Jclock uncertaintyXhu )%SFP_GEN[11].rx_data_ngccm_reg[11][40]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh*A; J arrival timeXhd;/ JXh4 JslackXh%@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[11].rx_data_ngccm_reg[11][66]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu7p@}A*A_7-@@A=А=%@.W>>'1X@v??ף?M?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhy? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[11] Jnet (fo=76, routed)Xhx?^ ,(SFP_GEN[11].rx_data_ngccm_reg[11][66]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][66]/C JFDCEXhzr> Jclock pessimismXh.W>@ Jclock uncertaintyXhu )%SFP_GEN[11].rx_data_ngccm_reg[11][66]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh*A; J arrival timeXhd;/ JXh4 JslackXh%@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuq@}AY*A9'@@A=А=u@|pW>$?y@v?!?ף??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhV? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I0 JXhzf qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp=?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh|pW>@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhY*A; J arrival timeXh/ JXh4 JslackXhu@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuAp@}A*A?5! @'@?5@A=А=i*@4W> -?+@v?!?ף?&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhV? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I0 JXhzf qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 Jnet (fo=1, routed)Xh"> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/I5 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 Jnet (fo=2, routed)XhO> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh4W>@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhi*@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuAp@}A*A?5! @'@?5@A=А=i*@4W> -?+@v?!?ף?&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhV? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I0 JXhzf qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 Jnet (fo=1, routed)Xh"> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/I5 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 Jnet (fo=2, routed)XhO> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh4W>@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhi*@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsun@}Av*AR7'@R@A=А=/@?kW>$?@v?!?ף?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhV? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I0 JXhzf qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh?kW>@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhv*A; J arrival timeXh+/ JXh4 JslackXh/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuvn@}A*AR7'@R@A=А=P@?kW>$?Zd@v?!?ף?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhV? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I0 JXhzf qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr)> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhy? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh?kW>@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh*A; J arrival timeXho/ JXh4 JslackXhP@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[11].rx_data_ngccm_reg[11][56]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsulg@}A&*Aw󜄾-@w@A=А=*@W>>yN@v??ף?W9?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhy? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[11] Jnet (fo=76, routed)Xhy?^ ,(SFP_GEN[11].rx_data_ngccm_reg[11][56]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[11] Jnet (fo=674, routed)XhC?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][56]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXhv )%SFP_GEN[11].rx_data_ngccm_reg[11][56]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh&*A; J arrival timeXh/ JXh4 JslackXh*@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[11].rx_data_ngccm_reg[11][60]/CE"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsulg@}A&*Aw󜄾-@w@A=А=*@W>>yN@v??ף?W9?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhy? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[11] Jnet (fo=76, routed)Xhy?^ ,(SFP_GEN[11].rx_data_ngccm_reg[11][60]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[11] Jnet (fo=674, routed)XhC?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][60]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXhv )%SFP_GEN[11].rx_data_ngccm_reg[11][60]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh&*A; J arrival timeXh/ JXh4 JslackXh*@L&  gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3!)y@1y @9Ay@Iy @e;Q@hq} b= > rise - rise rise - rise  ;)%SFP_GEN[1].rx_data_ngccm_reg[1][42]/C/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu&1>}`Sdl=?S?b= X9={=^ ?M??!?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)v )%SFP_GEN[1].rx_data_ngccm_reg[1][42]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[34] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[42]_i_1/I1 JXhzr /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[42]_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzrw=t 1-SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[42]_i_1_n_0 Jnet (fo=1, routed)XhD<a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][42]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXh x -)SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh`; J arrival timeXhC?/ JXh4 JslackXhb=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu#>} ׳ j=? ׳?Y?=?X?v==^ ?G??"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)XhC= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__0/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh?X? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhY?=<)%SFP_GEN[1].rx_data_ngccm_reg[1][79]/C/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuT>}gi5=??kC=ZnI=Q8=^ ?M??q#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)w )%SFP_GEN[1].rx_data_ngccm_reg[1][79]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[71] Jnet (fo=1, routed)XhC =^ 0,SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[78]_i_1/I0 JXhzr /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[78]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa=t 1-SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[78]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][79]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhٞ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXhZnIx -)SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhd?/ JXh4 JslackXhkC=)%SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/C)%SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsui;=}Mף;.ݔ?M?D=jffo=Q8=^ ???x?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)v )%SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/cntr_din[0] Jnet (fo=2, routed)Xh+= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/SFP_GEN[1].ngccm_rx_down_cnt[1]_i_1/I3 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/SFP_GEN[1].ngccm_rx_down_cnt[1]_i_1/OProp_A6LUT_SLICEM_I3_O JLUT4Xhzru<b g_gbt_bank[0].gbtbank_n_122 Jnet (fo=1, routed)XhD<[ )%SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh…?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh/?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/C JFDREXhzr> Jclock pessimismXhjffq '#SFP_GEN[1].ngccm_rx_down_cnt_reg[1]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhТ?/ JXh4 JslackXhD=;)%SFP_GEN[1].rx_data_ngccm_reg[1][46]/C/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuw>}gi5=??-G=ZnI=Q8=^ ?M??q#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)v )%SFP_GEN[1].rx_data_ngccm_reg[1][46]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[38] Jnet (fo=1, routed)XhC =^ 0,SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[46]_i_1/I1 JXhzr /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[46]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3XhzrGa=t 1-SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][46]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhٞ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXhZnIx -)SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh(1?/ JXh4 JslackXh-G=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuz>}ʱS"=k?ʱ?&8J=?9H==^ ?8??S?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[34] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhˡ?X3Y1 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]/C JFDCEXhzr> Jclock pessimismXh? c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhK?/ JXh4 JslackXh&8J=;)%SFP_GEN[1].rx_data_ngccm_reg[1][41]/C/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuz>}qS =}??S?K=/hH=`P=^ ?]??!?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)w )%SFP_GEN[1].rx_data_ngccm_reg[1][41]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] Jnet (fo=1, routed)Xh)\=^ 0,SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[40]_i_1/I0 JXhzr /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzrQ8=t 1-SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh$?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][41]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXh/hHw -)SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhq; J arrival timeXhΧ?/ JXh4 JslackXhK=]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuS=}@5֣;gf??L=rho=@=^ ?0??S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/ready_from_bitSlipCtrller_1 Jnet (fo=2, routed)Xh)\= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__0/I2 JXhzr `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__0/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__0_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X3Y1 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhrh [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh@5; J arrival timeXh?/ JXh4 JslackXhL=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C)%SFP_GEN[1].rx_data_ngccm_reg[1][62]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu:A>}AjZ=ש=ˡ?Z?%M= 9H=)\>^ ?S?? #?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[1][62] Jnet (fo=1, routed)Xh)\>[ )%SFP_GEN[1].rx_data_ngccm_reg[1][62]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh,?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xhd;?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][62]/C JFDCEXhzr> Jclock pessimismXh q '#SFP_GEN[1].rx_data_ngccm_reg[1][62]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhAj; J arrival timeXhҭ?/ JXh4 JslackXh%M=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu]B>}HX9ӫ=B`?X9?5M= = =^ ???#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__0/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__0/OProp_D5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhE?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhH; J arrival timeXh.?/ JXh4 JslackXh5M=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu@}AG4AF3 j@F3@A=А=;Q@1 >?X9l@?x??z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr|> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 Jnet (fo=1, routed)XhSc> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/OProp_H6LUT_SLICEM_I5_O JLUT6XhzrGa= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh1 >@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhG4A; J arrival timeXhS/ JXh4 JslackXh;Q@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsux@}A{4A 3j@ 3@A=А=@>?k@?x??j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr|> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 Jnet (fo=1, routed)XhSc> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/OProp_H6LUT_SLICEM_I5_O JLUT6XhzrGa= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^@X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh{4A; J arrival timeXhC/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu@}A5A(4ZCj@(4@A=А=&@>X9?^a@?x??A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh:? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh5A; J arrival timeXh| / JXh4 JslackXh&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu@}A5A(4ZCj@(4@A=А=&@>X9?^a@?x??A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh:? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh5A; J arrival timeXh| / JXh4 JslackXh&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu/@}A4AH2Tj@H2@A=А=[S&@;1> ?r`@?x??Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhף> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrZd> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh;1>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh4A; J arrival timeXh / JXh4 JslackXh[S&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu/@}A4AH2Tj@H2@A=А=[S&@;1> ?r`@?x??Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhף> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrZd> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh;1>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh4A; J arrival timeXh / JXh4 JslackXh[S&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuҡ@}A5A(4ZCj@(4@A=А=t`&@>X9?8a@?x??A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh5A; J arrival timeXhp / JXh4 JslackXht`&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuҡ@}A5A(4ZCj@(4@A=А=t`&@>X9?8a@?x??A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh5A; J arrival timeXhp / JXh4 JslackXht`&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu@}A4AH2Tj@H2@A=А=ޔ&@;1> ?A`@?x??Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhף> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrZd> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhS> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh;1>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh4A; J arrival timeXhp / JXh4 JslackXhޔ&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu@}A4AH2Tj@H2@A=А=ޔ&@;1> ?A`@?x??Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh-@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_D6LUT_SLICEL_I3_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhף> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrZd> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhS> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFK@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh;1>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh4A; J arrival timeXhp / JXh4 JslackXhޔ&@ &  gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4!)y@1y @9Ay@Iy @e\@hq} %= > rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuX9>}.3=v?.?%=.=-=> ??~*?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/OProp_G6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh. g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhy?/ JXh4 JslackXh%=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuv>>}󰠿٬=S??&:=0[=5^=>??r(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhP?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh0 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh󰠿; J arrival timeXh,?/ JXh4 JslackXh&:=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu|?>}.3=v?.?=->=.=5^=> ??~*?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzr@= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh. g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh=->=wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C)%SFP_GEN[2].rx_data_ngccm_reg[2][78]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu>}Toҭ=H=?ҭ?,@=t<D==>~ ??*?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[2][78] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[2].rx_data_ngccm_reg[2][78]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh:?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[2].rx_data_ngccm_reg[2][78]/C JFDCEXhzr> Jclock pessimismXht<q '#SFP_GEN[2].rx_data_ngccm_reg[2][78]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhTo; J arrival timeXht?/ JXh4 JslackXh,@=ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C)%SFP_GEN[2].rx_data_ngccm_reg[2][65]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu~>}QpҭT=?ҭ?-D=m<D=/=>^ ??*?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[2][65] Jnet (fo=1, routed)Xh/=[ )%SFP_GEN[2].rx_data_ngccm_reg[2][65]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh:?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[2].rx_data_ngccm_reg[2][65]/C JFDCEXhzr> Jclock pessimismXhm<r '#SFP_GEN[2].rx_data_ngccm_reg[2][65]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhQp; J arrival timeXh?/ JXh4 JslackXh-D=ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C)%SFP_GEN[2].rx_data_ngccm_reg[2][69]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuG>}|aV|=?V?%?F=SD=+>>^ ??+?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[2][69] Jnet (fo=1, routed)Xh+>[ )%SFP_GEN[2].rx_data_ngccm_reg[2][69]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[2] Jnet (fo=674, routed)XhL7?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[2].rx_data_ngccm_reg[2][69]/C JFDCEXhzr> Jclock pessimismXhSr '#SFP_GEN[2].rx_data_ngccm_reg[2][69]Hold_BFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh|a; J arrival timeXhu?/ JXh4 JslackXh%?F=)%SFP_GEN[2].rx_data_ngccm_reg[2][42]/C/+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuX94>}쟿m竿n8=v?m?JK=+E=-=> ??z&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)v )%SFP_GEN[2].rx_data_ngccm_reg[2][42]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]_0[34] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[2].ngCCM_gbt/RX_Word_rx40[42]_i_1/I1 JXhzr /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40[42]_i_1/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr #=t 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40[42]_i_1_n_0 Jnet (fo=1, routed)XhD<a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[2] Jnet (fo=674, routed)Xhף?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[2].rx_data_ngccm_reg[2][42]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXh+x -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh쟿; J arrival timeXhE?/ JXh4 JslackXhJK=D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CD@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuX9>}{~@=-?~?/L=Hrv=X9=>T??$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt_reg[2][0]_0[0] Jnet (fo=1, routed)Xht= xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].rx_clken_sr[2][1]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].rx_clken_sr[2][1]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT2XhzrQ8=m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_247 Jnet (fo=1, routed)Xho<v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)XhB`?X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C JFDCEXhzr> Jclock pessimismXhHr B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh{; J arrival timeXh/ݤ?/ JXh4 JslackXh/L=wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Cwsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuS=}#۩ף;/?#۩?L=A`o=@=>.??"?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] Jnet (fo=2, routed)Xh)\= {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__2/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__2/OProp_A6LUT_SLICEL_I5_O JLUT6Xhzru< |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__2_n_0 Jnet (fo=1, routed)XhD< wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(|?X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhA` uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhYd?/ JXh4 JslackXhL=ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C)%SFP_GEN[2].rx_data_ngccm_reg[2][24]/D"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuJ>}wplO=?p? O=!9H=u>>??)?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=U rx_data[2][24] Jnet (fo=1, routed)Xhu>[ )%SFP_GEN[2].rx_data_ngccm_reg[2][24]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[2] Jnet (fo=674, routed)XhQ?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[2].rx_data_ngccm_reg[2][24]/C JFDCEXhzr> Jclock pessimismXh!r '#SFP_GEN[2].rx_data_ngccm_reg[2][24]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXh O=g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuΧ@}AG2A+ l w_@+@A=А=\@(]>ʡ?l@1??c;?A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr֣p> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X3Y1 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh(]>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhG2A; J arrival timeXh / JXh4 JslackXh\@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuC@}A2A+ l w_@+@A=А=F@(]>ʡ?l@1??c;?A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr֣p> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhv> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X3Y1 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh(]>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh2A; J arrival timeXh / JXh4 JslackXhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuC@}A2A+ l w_@+@A=А=F@(]>ʡ?l@1??c;?A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr֣p> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhv> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X3Y1 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh(]>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh2A; J arrival timeXh / JXh4 JslackXhF@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu @}Aۅ2A"+}w_@"+@A=А=T@/n>?Ct@1??c;?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_G6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh#? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh/n>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhۅ2A; J arrival timeXhp / JXh4 JslackXhT@ ~g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu@}A2A,G w_@,@A=А=h@Z>?jt@1??c;?̡?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_G6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xho#? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh2A; J arrival timeXhrh / JXh4 JslackXhh@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu٦@}A2A,G w_@,@A=А=r@Z>?X9t@1??c;?̡?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_G6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhM"? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh2A; J arrival timeXh)\ / JXh4 JslackXhr@ l!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu=5@}A2A(,h w_@(,@A=А=Y@6Y>U?Te@1??c;?¥?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\B> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/OProp_D6LUT_SLICEL_I2_O JLUT4Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 Jnet (fo=1, routed)Xh"> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 Jnet (fo=2, routed)Xh}> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh6Y>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh2A; J arrival timeXh< / JXh4 JslackXhY@ l!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu=5@}A2A(,h w_@(,@A=А=Y@6Y>U?Te@1??c;?¥?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\B> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/OProp_D6LUT_SLICEL_I2_O JLUT4Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 Jnet (fo=1, routed)Xh"> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 Jnet (fo=2, routed)Xh}> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh6Y>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh2A; J arrival timeXh< / JXh4 JslackXhY@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu^@}A2AC+5w_@C+@A=А= @k>ʡ?f@1??c;??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhR> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh`> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhk>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh2A; J arrival timeXhMb / JXh4 JslackXh @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu^@}A2AC+5w_@C+@A=А= @k>ʡ?f@1??c;??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh?@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhR> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh`> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhXA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhk>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh2A; J arrival timeXhMb / JXh4 JslackXh @ &  gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5!)y@1y @9Ay@Iy @e@hq} =  >   rise - rise rise - rise  eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[35]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsun>} ᥿> P='1?> ?=BD=\=y?C ??1,?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[35]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[35] Jnet (fo=1, routed)Xh\= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]/C JFDCEXhzr> Jclock pessimismXhB c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ᥿; J arrival timeXh~?/ JXh4 JslackXh=)%SFP_GEN[3].rx_data_ngccm_reg[3][82]/C/+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu >}5}?Ry=}??}??^_$=JAD=d;=y?B`??r(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)v )%SFP_GEN[3].rx_data_ngccm_reg[3][82]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]_0[74] Jnet (fo=1, routed)Xhd;=a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh$?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[3].rx_data_ngccm_reg[3][82]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]/C JFDCEXhzr> Jclock pessimismXhJAw -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh5; J arrival timeXhX?/ JXh4 JslackXh^_$=sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Csog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu433>}µ{='1?µ?72=> ף=\=y?C ??x)?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xhʡ= xtg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__11/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__11/OProp_D6LUT_SLICEM_I0_O JLUT5Xhzr< _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter[2] Jnet (fo=1, routed)Xho< sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhף?X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzr> Jclock pessimismXh> qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh72=Ajfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/Cjfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu433>}Ȁ~?n=Η?~??6=M ף=\=y?~ ??r(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/QProp_GFF_SLICEL_C_Q JFDCEXhzfD= SOg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/Q[1] Jnet (fo=9, routed)Xhʡ= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[0]_i_1__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[0]_i_1__2/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzro= QMg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/D[0] Jnet (fo=1, routed)Xho< jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:?X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhM hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhȀ; J arrival timeXh?5?/ JXh4 JslackXh6= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuz>}^𧶿(8=u??{8=әBD==y?1 ??C+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[27] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X3Y1 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh8?X3Y1 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]/C JFDCEXhzr> Jclock pessimismXhәB c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh^; J arrival timeXh"?/ JXh4 JslackXh{8=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C)%SFP_GEN[3].rx_data_ngccm_reg[3][71]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuxh>}M=??LC=wfID==y? ??)?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_BFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[3][71] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[3].rx_data_ngccm_reg[3][71]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԈ?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[3] Jnet (fo=674, routed)Xha?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[3].rx_data_ngccm_reg[3][71]/C JFDCEXhzr> Jclock pessimismXhwfIr '#SFP_GEN[3].rx_data_ngccm_reg[3][71]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhM; J arrival timeXh?/ JXh4 JslackXhLC=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu)>}bۢ?)=gf??L}K=lJ[=T=y???'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__2/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__2/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<ߟ?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhlJ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhbۢ; J arrival timeXhL7?/ JXh4 JslackXhL}K=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuz>}ޘk =gf?k?K=~tJ=`P=y???l'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__2/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__2/OProp_H6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh~tJ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhޘ; J arrival timeXh?/ JXh4 JslackXhK=mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[2]/Cmig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuT>}񦿍xo,=5^?x?K=Mv=Ga=y???a0?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[2]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/timer[2] Jnet (fo=5, routed)Xhw= qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[3]_i_1__3/I1 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[3]_i_1__3/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrQ8= rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[3]_i_1__3_n_0 Jnet (fo=1, routed)Xho< mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X3Y1 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[2]/C JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X3Y1 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]/C JFDREXhzr> Jclock pessimismXhM kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh񦿐; J arrival timeXhO?/ JXh4 JslackXhK=o<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuS=}Nb𧶿֣;u??L=#ko=@=y?1 ??C+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gbtBank_Clk_gen[3].cnt_reg[3][7]_0[3] Jnet (fo=9, routed)Xh)\= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gbtBank_Clk_gen[3].cnt[3][3]_i_1/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gbtBank_Clk_gen[3].cnt[3][3]_i_1/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru<m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_253 Jnet (fo=1, routed)XhD<n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xhx?X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh8?X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXh#k :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhNb; J arrival timeXhȦ?/ JXh4 JslackXhL= zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu@}A4A31%@5n@3@A=А=@>W9?b@~?]@D?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ? njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/I1 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/OProp_G6LUT_SLICEL_I1_O JLUT6Xhzr`P= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh ? kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI @X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh4A; J arrival timeXh/ JXh4 JslackXh@ zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu< @}A4A3N%@5n@3@A=А=E@W>W9?@~?]@D??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ? njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/I1 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/OProp_G6LUT_SLICEL_I1_O JLUT6Xhzr`P= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 Jnet (fo=2, routed)Xhgf> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh4A; J arrival timeXhn/ JXh4 JslackXhE@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu|@}A4AI4"@5n@I4@A=А=+@>Mb?v@~?]@D??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)XhL7 ? vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh4A; J arrival timeXhK/ JXh4 JslackXh+@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu'\@}AZ5AI4"@5n@I4@A=А=@>Mb?+v@~?]@D??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh'1? vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhZ5A; J arrival timeXhc;/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu'\@}AZ5AI4"@5n@I4@A=А=@>Mb?+v@~?]@D??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh'1? vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhZ5A; J arrival timeXhc;/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuy@}Ad5A5|@5n@5@A=А=4@ulj>Mb?s@~?]@D?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzf> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhl> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhulj>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhd5A; J arrival timeXh/ JXh4 JslackXh4@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuz@}A5Ak4t @5n@k4@A=А=S@݉>Mb?p@~?]@D??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh'1? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh݉>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh5A; J arrival timeXh / JXh4 JslackXhS@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu}j@}Al5A5#@5n@5@A=А=@ĉ>Mb?֣p@~?]@D?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzf> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhG> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhĉ>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhl5A; J arrival timeXh / JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu}j@}Al5A5#@5n@5@A=А=@ĉ>Mb?֣p@~?]@D?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzf> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhG> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhĉ>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhl5A; J arrival timeXh / JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuQ@}Ap5A5#@5n@5@A=А=m@ĉ>Mb?rp@~?]@D?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhI@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzf> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhw> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhĉ>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhp5A; J arrival timeXhD / JXh4 JslackXhm@ &  gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6!)y@1y @9Ay@Iy @e6@hq} R33= 5>   rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][54]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu-2>}P刺=H??R33=]dD=%>(>x)? >iM?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=U rx_data[4][54] Jnet (fo=1, routed)Xh%>[ )%SFP_GEN[4].rx_data_ngccm_reg[4][54]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPw?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhВ?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][54]/C JFDCEXhzr> Jclock pessimismXh]dr '#SFP_GEN[4].rx_data_ngccm_reg[4][54]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhP; J arrival timeXh&?/ JXh4 JslackXhR33=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][48]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu^d;>} "N=/?"?\5=C9H=L7 >(>z.? >S?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=U rx_data[4][48] Jnet (fo=1, routed)XhL7 >[ )%SFP_GEN[4].rx_data_ngccm_reg[4][48]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(|?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][48]/C JFDCEXhzr> Jclock pessimismXhCr '#SFP_GEN[4].rx_data_ngccm_reg[4][48]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh\5=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsut>}_o,=??Dy;=SB=L=(>h-? >R?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__3/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__3/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhSB g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh_; J arrival timeXh)\?/ JXh4 JslackXhDy;=z.*SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/C@},CvZp=V?C?==^5D=l=(>-? >Y9T?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)| .*SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= D@SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[3] Jnet (fo=1, routed)Xhl=r @ IESFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$?X4Y2 (CLOCK_ROOT)r @ Jclock pessimismXh^5 >:SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]Hold_AFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh,; J arrival timeXh?/ JXh4 JslackXh==g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][79]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuj<>}. I=V? ?==D=C >(>-? >GS?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_GFF_SLICEM_C_Q JFDREXhzrD=U rx_data[4][79] Jnet (fo=1, routed)XhC >[ )%SFP_GEN[4].rx_data_ngccm_reg[4][79]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhl{?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][79]/C JFDCEXhzr> Jclock pessimismXhr '#SFP_GEN[4].rx_data_ngccm_reg[4][79]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh.; J arrival timeXh?/ JXh4 JslackXh==g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][47]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuj<>} B=/? ?A=CD=C >(>z.? >GS?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[4][47] Jnet (fo=1, routed)XhC >[ )%SFP_GEN[4].rx_data_ngccm_reg[4][47]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(|?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][47]/C JFDCEXhzr> Jclock pessimismXhCr '#SFP_GEN[4].rx_data_ngccm_reg[4][47]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhj?/ JXh4 JslackXhA=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[33]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuz>} $)=㥋??F=J5D==(> +? >XM?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[33]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[33] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhy?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh]?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]/C JFDCEXhzr> Jclock pessimismXhJ5 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh ; J arrival timeXh?5?/ JXh4 JslackXhF=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C($SFP_GEN[4].rx_data_ngccm_reg[4][3]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu >}6$Zd(=-?Zd?(G=6YCD=:=(>/? >zT?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=T  rx_data[4][3] Jnet (fo=1, routed)Xh:=Z ($SFP_GEN[4].rx_data_ngccm_reg[4][3]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhE?X4Y2 (CLOCK_ROOT)Z ($SFP_GEN[4].rx_data_ngccm_reg[4][3]/C JFDCEXhzr> Jclock pessimismXh6YCp &"SFP_GEN[4].rx_data_ngccm_reg[4][3]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh6$; J arrival timeXhOb?/ JXh4 JslackXh(G=mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuS=}&أ;X??L=aXo=@=(>ef&? >G?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh)\= qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__4/I0 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__4/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru< rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__4_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhzt?X4Y2 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh;ߏ?X4Y2 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhaX kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh&; J arrival timeXhO?/ JXh4 JslackXhL=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuT>}h䥫/? >T?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__3/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__3/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh.}?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh,?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhAC g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhh; J arrival timeXha?/ JXh4 JslackXhٕO=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu@}A,1A!*Hw=/5@!*@A=А=6@9e>!?}?@7??+'??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 Jnet (fo=1, routed)Xh^> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/OProp_H6LUT_SLICEM_I5_O JLUT6XhzrGa= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 Jnet (fo=2, routed)XhNb> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh,1A; J arrival timeXhA/ JXh4 JslackXh6@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu@}A,1A!*Hw=/5@!*@A=А=6@9e>!?}?@7??+'??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE6> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 Jnet (fo=1, routed)Xh^> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/OProp_H6LUT_SLICEM_I5_O JLUT6XhzrGa= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 Jnet (fo=2, routed)XhNb> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh,1A; J arrival timeXhA/ JXh4 JslackXh6@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu@}A[1A8)-=/5@8)@A=А=V=@9e>в?~z@7??+'?D?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhL> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__4/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__4/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhl? vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh[1A; J arrival timeXhE/ JXh4 JslackXhV=@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu"۩@}Ar1A8)-=/5@8)@A=А=j=@9e>в?Mz@7??+'?D?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhL> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__4/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__4/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhr1A; J arrival timeXhX9/ JXh4 JslackXhj=@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu©@}AB1Ax)m)=/5@x)@A=А=ͨ=@9e>E?Nbx@7??+'?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzfQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhB1A; J arrival timeXh-/ JXh4 JslackXhͨ=@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu©@}AB1Ax)m)=/5@x)@A=А=ͨ=@9e>E?Nbx@7??+'?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzfQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhB1A; J arrival timeXh-/ JXh4 JslackXhͨ=@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu@}AZ1Ax)m)=/5@x)@A=А=P=@9e>E?(1x@7??+'?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzfQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh%? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhZ1A; J arrival timeXh / JXh4 JslackXhP=@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu@}AZ1Ax)m)=/5@x)@A=А=P=@9e>E?(1x@7??+'?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzfQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh%? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhZ1A; J arrival timeXh / JXh4 JslackXhP=@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu~?@}A1AX)R!=/5@X)@A=А=+>@9e>E?(\w@7??+'?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzfQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh[d> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh;@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh+>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu @}A1A^)):=/5@^)@A=А=\kC@9e>+?nz@7??+'??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh K@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGa= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh$? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh9e>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh\kC@ &  gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7!)y@1y @9Ay@Iy @eJ,@hq} c=  >   rise - rise rise - rise  eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[24]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsut>}C|V=rh?|?c=0 ;9H=\= ף>!2?X>dX?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[24]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[24] Jnet (fo=1, routed)Xh\= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh6^?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXh0 ; c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhC; J arrival timeXh ף?/ JXh4 JslackXhc=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[27]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuz>}ᾞI=rh??'=/;D== ף>!2?X>KW?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[27]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[27] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]/C JFDCEXhzr> Jclock pessimismXh/; c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhᾞ; J arrival timeXh?/ JXh4 JslackXh'=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[33]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuw>}ᾞI=rh??7=/;9H== ף>!2?X>KW?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[33]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[33] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]/C JFDCEXhzr> Jclock pessimismXh/; c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhᾞ; J arrival timeXhz?/ JXh4 JslackXh7=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C)%SFP_GEN[5].rx_data_ngccm_reg[5][70]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu >}<߯(R=?<߯?}:=#:D=> = ף>F3?X>X?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[5][70] Jnet (fo=1, routed)Xh> =[ )%SFP_GEN[5].rx_data_ngccm_reg[5][70]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhЂ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][70]/C JFDCEXhzr> Jclock pessimismXh#:q '#SFP_GEN[5].rx_data_ngccm_reg[5][70]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh}:=H)%SFP_GEN[5].rx_data_ngccm_reg[5][45]/C/+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuX94>}}f=-??@=( ף== ף>X94?X>KW?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)v )%SFP_GEN[5].rx_data_ngccm_reg[5][45]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40g_gbt_bank[0].gbtbank/RX_Word_rx40_reg[78]_0[21] Jnet (fo=1, routed)Xh ף=b 40g_gbt_bank[0].gbtbank/RX_Word_rx40[44]_i_1__0/I0 JXhzr 3/g_gbt_bank[0].gbtbank/RX_Word_rx40[44]_i_1__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr<v 3/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] Jnet (fo=1, routed)Xho<a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xho?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][45]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXh(w -)SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh}; J arrival timeXh:?/ JXh4 JslackXh@=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C)%SFP_GEN[5].rx_data_ngccm_reg[5][53]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuv>}<߯(R=?<߯?wF=#:9H="= ף>F3?X>X?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[5][53] Jnet (fo=1, routed)Xh"=[ )%SFP_GEN[5].rx_data_ngccm_reg[5][53]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhЂ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][53]/C JFDCEXhzr> Jclock pessimismXh#:q '#SFP_GEN[5].rx_data_ngccm_reg[5][53]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhwF=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu)>})\o,=&?)\?G=kF=Y= ף>-2?X>W?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister[0] Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__4/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__4/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[17] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhq=?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhkF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhG=`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu)>})\o,=&?)\?G=kF=Y= ף>-2?X>W?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/feedbackRegister[0] Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__4/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__4/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhq=?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhkF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhG=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C)%SFP_GEN[5].rx_data_ngccm_reg[5][20]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu0>}.x(=$??zK=kF9H=:= ף>1?X>KW?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[5][20] Jnet (fo=1, routed)Xh:=[ )%SFP_GEN[5].rx_data_ngccm_reg[5][20]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][20]/C JFDCEXhzr> Jclock pessimismXhkFq '#SFP_GEN[5].rx_data_ngccm_reg[5][20]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh.x; J arrival timeXh ף?/ JXh4 JslackXhzK=]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuS=}> ̬ף;d;?̬?L=lgo=@= ף>V.?X>!R?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/ready_from_bitSlipCtrller_5 Jnet (fo=2, routed)Xh)\= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__4/I2 JXhzr `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__4/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__4_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X4Y2 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhlg [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh> ; J arrival timeXhp?/ JXh4 JslackXhL=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu|@}A2A/-e=c8@/-@A=А=J,@%g>?1@Yd;?ˡ?q=*?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh ף> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4_n_0 Jnet (fo=1, routed)Xh1= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF@X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh2A; J arrival timeXhx/ JXh4 JslackXhJ,@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu|@}A2A/-e=c8@/-@A=А=J,@%g>?1@Yd;?ˡ?q=*?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh ף> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4_n_0 Jnet (fo=1, routed)Xh1= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF@X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh2A; J arrival timeXhx/ JXh4 JslackXhJ,@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu@}AeZ2Aj,ɗ4=c8@j,@A=А=!0@%g>(\?Ā@Yd;?ˡ?q=*??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhy> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr1,> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh ? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXheZ2A; J arrival timeXhQ/ JXh4 JslackXh!0@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuz@}A}^2Aj,ɗ4=c8@j,@A=А=s0@%g>(\?أ@Yd;?ˡ?q=*??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhy> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr1,> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh}^2A; J arrival timeXhA/ JXh4 JslackXhs0@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu@}A){2A,5\U=c8@,@A=А=5@%g>(\?Z9|@Yd;?ˡ?q=*??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhy> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr1,> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh){2A; J arrival timeXh/ JXh4 JslackXh5@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuʭ@}Af2A,+M=c8@,@A=А=5@%g>?{@Yd;?ˡ?q=*?6?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr&1> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh+> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS@X4Y2 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhf2A; J arrival timeXhy/ JXh4 JslackXh5@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu"ۭ@}A@2A,5\U=c8@,@A=А=Z66@%g>(\?2|@Yd;?ˡ?q=*??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhy> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr1,> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh@2A; J arrival timeXh/ JXh4 JslackXhZ66@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu"ۭ@}A@2A,5\U=c8@,@A=А=Z66@%g>(\?2|@Yd;?ˡ?q=*??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhy> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr1,> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh@2A; J arrival timeXh/ JXh4 JslackXhZ66@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu.@}Ar2A,+M=c8@,@A=А=$W6@%g>?[d{@Yd;?ˡ?q=*?6?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr&1> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS@X4Y2 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhr2A; J arrival timeXh// JXh4 JslackXh$W6@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu.@}Ar2A,+M=c8@,@A=А=$W6@%g>?[d{@Yd;?ˡ?q=*?6?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhFK@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr&1> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS@X4Y2 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh%g>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhr2A; J arrival timeXh// JXh4 JslackXh$W6@ &  gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8!)y@1y @9Ay@Iy @et@hq} s#=  >   rise - rise rise - rise  ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C)%SFP_GEN[6].rx_data_ngccm_reg[6][54]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu}&>}{I'1ꡋ=?'1?s#=H9H=x=M>'?Q>I?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[6][54] Jnet (fo=1, routed)Xhx=[ )%SFP_GEN[6].rx_data_ngccm_reg[6][54]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xho?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][54]/C JFDCEXhzr> Jclock pessimismXhHr '#SFP_GEN[6].rx_data_ngccm_reg[6][54]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh{I; J arrival timeXhOb?/ JXh4 JslackXhs#=lg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C($SFP_GEN[6].rx_data_ngccm_reg[6][1]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuS>}F뜿/`q=?5?/?c $=v;D="=M>W-?Q>S?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=T  rx_data[6][1] Jnet (fo=1, routed)Xh"=Z ($SFP_GEN[6].rx_data_ngccm_reg[6][1]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)Z ($SFP_GEN[6].rx_data_ngccm_reg[6][1]/C JFDCEXhzr> Jclock pessimismXhv;p &"SFP_GEN[6].rx_data_ngccm_reg[6][1]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhF뜿; J arrival timeXhI ?/ JXh4 JslackXhc $=mg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C($SFP_GEN[6].rx_data_ngccm_reg[6][3]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuS>}F뜿/`q=?5?/?c $=v;D="=M>W-?Q>S?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=T  rx_data[6][3] Jnet (fo=1, routed)Xh"=Z ($SFP_GEN[6].rx_data_ngccm_reg[6][3]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)Z ($SFP_GEN[6].rx_data_ngccm_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhv;p &"SFP_GEN[6].rx_data_ngccm_reg[6][3]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhF뜿; J arrival timeXhI ?/ JXh4 JslackXhc $=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu)>}uL7=?L7?ñ.=bʡ=-=M>)?Q>2L?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[0] Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__5/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__5/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"{?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhb g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhu; J arrival timeXh?/ JXh4 JslackXhñ.=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[86]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu>}DL=I??!8=G:9H==M>L7)?Q>hM?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[86]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[86] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh5^z?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[86]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/ݔ?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]/C JFDCEXhzr> Jclock pessimismXhG: c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh|?/ JXh4 JslackXh!8=)%SFP_GEN[6].rx_data_ngccm_reg[6][40]/C/+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu/>}URm竿sF=?m?J=>`=T=M>E,?Q>shQ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR)v )%SFP_GEN[6].rx_data_ngccm_reg[6][40]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] Jnet (fo=1, routed)Xht=^ 0,SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[40]_i_1/I1 JXhzr /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrY=t 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh.}?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][40]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXh>w -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhUR; J arrival timeXh?/ JXh4 JslackXhJ=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsut>}H"=?"?V=[ E=L=M>E,?Q> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh[ E g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhH; J arrival timeXhNb?/ JXh4 JslackXhV=sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/Csog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsux=}䥫֣;-?䥫?Y=~jo=L=M>1,?Q>aP?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= TPg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/sel0[4] Jnet (fo=3, routed)Xh)\= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__6/I5 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__6/OProp_B6LUT_SLICEL_I5_O JLUT6Xhzru< xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__6_n_0 Jnet (fo=1, routed)Xhu< sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh,?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh~j qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhY=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuz>}ܘL7{p=/?L7?S3\=u%;D==M> +?Q>2L?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[35] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(|?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]/C JFDCEXhzr> Jclock pessimismXhu%; c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhܘ; J arrival timeXhv?/ JXh4 JslackXhS3\=eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu =}t'1ף;㥋?'1?/]=d;_o=`P=M>'?Q>I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/rxslide_in[0] Jnet (fo=2, routed)Xh)\= ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__5/I2 JXhzr hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__5/OProp_D6LUT_SLICEL_I2_O JLUT3Xhzru< jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__5_n_0 Jnet (fo=1, routed)Xho< eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhd;_ c_g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_regHold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXht; J arrival timeXh5^?/ JXh4 JslackXh/]=j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuO@}A@2A(,˿=z4@(,@A=А=t@e>V?I @5^:??)?Mb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhB`? njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 Jnet (fo=1, routed)Xhw= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@2A; J arrival timeXh / JXh4 JslackXht@ j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuO@}A@2A(,˿=z4@(,@A=А=t@e>V?I @5^:??)?Mb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhB`? njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 Jnet (fo=1, routed)Xhw= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@2A; J arrival timeXh / JXh4 JslackXht@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu+@}AW#2AF+u=z4@F+@A=А={@e>n?ff@5^:??)?|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhW#2A; J arrival timeXh9 / JXh4 JslackXh{@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsus@}A@2A(,˿=z4@(,@A=А=I^@e>n?Ώ@5^:??)?Mb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhv> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh@2A; J arrival timeXhrh / JXh4 JslackXhI^@ |g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuP@}A5H2AI,,=z4@I,@A=А=S5@e>n?@5^:??)?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh5H2A; J arrival timeXhz / JXh4 JslackXhS5@ |g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu[@}A5H2AI,,=z4@I,@A=А==@e>n?ʍ@5^:??)?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh@5> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh5H2A; J arrival timeXhff / JXh4 JslackXh=@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu@}AML2AI,,=z4@I,@A=А==@e>n?ҍ@5^:??)?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhR> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhML2A; J arrival timeXh~j / JXh4 JslackXh=@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsun@}AML2AI,,=z4@I,@A=А=&@e>n?@5^:??)?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh(> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhML2A; J arrival timeXhV / JXh4 JslackXh&@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsun@}AML2AI,,=z4@I,@A=А=&@e>n?@5^:??)?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh(> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhML2A; J arrival timeXhV / JXh4 JslackXh&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu@}A+2A +-=z4@ +@A=А=.@e>r?@5^:??)?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzf"y> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh<> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__6/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__6/OProp_H6LUT_SLICEL_I0_O JLUT6Xhzre;_> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhL7> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^@X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+2A; J arrival timeXhn/ JXh4 JslackXh.@ &  gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9!)y@1y @9Ay@Iy @eb@hq} S= >   rise - rise rise - rise  wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][52]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsut>}U㕿s7O=s?U?S=m+9H=[=c>^ ?>r=*?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[7][52] Jnet (fo=1, routed)Xh[=[ )%SFP_GEN[7].rx_data_ngccm_reg[7][52]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhĀ?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][52]/C JFDCEXhzr> Jclock pessimismXhm+r '#SFP_GEN[7].rx_data_ngccm_reg[7][52]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhj?/ JXh4 JslackXhS=D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CD@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu9H>}!= .=ts?= ??5===c>L7 ?>C,?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/QProp_GFF_SLICEM_C_Q JFDCEXhzrD= rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt_reg[7][0]_0[0] Jnet (fo=1, routed)Xh ף= xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].rx_clken_sr[7][1]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].rx_clken_sr[7][1]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT2XhzrT=m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_322 Jnet (fo=1, routed)Xho<v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh}?U?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh!; J arrival timeXhВ?/ JXh4 JslackXh?5=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuv>>}=s??;6==j=c>^ ?>~*?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__6/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__6/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhʑ?/ JXh4 JslackXh;6=X/+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[25]/CFBSFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsun>}R헿'1ľ+=Zd?'1?b8=v;9H==c>E,?>N?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)| /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[25]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=o ,(SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/Q[9] Jnet (fo=2, routed)Xh=x FBSFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhvx?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[7].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y2 (CLOCK_ROOT)x FBSFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/C JFDREXhzr> Jclock pessimismXhv; D@SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhR헿; J arrival timeXh.?/ JXh4 JslackXhb8=wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][31]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsut>}+=}?u??Z A=E*,9H=[=c>  ?>x)?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[7][31] Jnet (fo=1, routed)Xh[=[ )%SFP_GEN[7].rx_data_ngccm_reg[7][31]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> W?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhNb?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][31]/C JFDCEXhzr> Jclock pessimismXhE*,r '#SFP_GEN[7].rx_data_ngccm_reg[7][31]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXhZ A=)%SFP_GEN[7].rx_data_ngccm_reg[7][63]/C/+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu|?>}ˡD=s?ˡ?F=x=1=c>^ ?>^)?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)v )%SFP_GEN[7].rx_data_ngccm_reg[7][63]/QProp_GFF_SLICEM_C_Q JFDCEXhzrD=v 3/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[55] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[62]_i_1/I0 JXhzr /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[62]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa=t 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[62]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][63]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr> Jclock pessimismXhxx -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhF=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[32]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuz>}򆿍y閿#%=}?u?y?-G= 99H==c>  ?>I,?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[32]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[32] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXh 9 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh򆿐; J arrival timeXh/?/ JXh4 JslackXh-G=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuC>}=s??J==-=c>^ ?>~*?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__6/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__6/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhn?/ JXh4 JslackXhJ=)%SFP_GEN[7].rx_data_ngccm_reg[7][58]/C/+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu@>}ˡD=s?ˡ?J=x=1=c>^ ?>^)?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)v )%SFP_GEN[7].rx_data_ngccm_reg[7][58]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[50] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[58]_i_1/I1 JXhzr /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[58]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3XhzrGa=t 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][58]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXhxx -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXhJ=tg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][26]/D"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu)>}(ˡľ+=u?ˡ?%M=,9H=9=c>C ?>^)?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[7][26] Jnet (fo=1, routed)Xh9=[ )%SFP_GEN[7].rx_data_ngccm_reg[7][26]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKW?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][26]/C JFDCEXhzr> Jclock pessimismXh,r '#SFP_GEN[7].rx_data_ngccm_reg[7][26]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh(; J arrival timeXhh?/ JXh4 JslackXh%M=l!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu33@}A>+Aoa.@o@A=А=b@Y>?[:@h-??-?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhn> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 Jnet (fo=1, routed)Xh^> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/OProp_G6LUT_SLICEM_I5_O JLUT6XhzrZd> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 Jnet (fo=2, routed)Xh)\> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh>+A; J arrival timeXh/ JXh4 JslackXhb@ l!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu33@}A>+Aoa.@o@A=А=b@Y>?[:@h-??-?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhn> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 Jnet (fo=1, routed)Xh^> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/OProp_G6LUT_SLICEM_I5_O JLUT6XhzrZd> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 Jnet (fo=2, routed)Xh)\> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh>+A; J arrival timeXh/ JXh4 JslackXhb@ ~g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu@}A]+AJ q.@J @A=А=m@Y>̼?t3@h-??-?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhff? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh]+A; J arrival timeXhQ/ JXh4 JslackXhm@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsü@}Au+AJ q.@J @A=А=m@Y>̼?233@h-??-?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhB`? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhu+A; J arrival timeXh'1/ JXh4 JslackXhm@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuT@}AM+A"$`.@"@A=А=ֵt@Y>!?n2@h-??-?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__7/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__7/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS?X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhM+A; J arrival timeXhG/ JXh4 JslackXhֵt@ ~g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsul@}Aܰ+ARh.@@A=А=!y@ Y>̼?r(@h-??-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhj> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh Y>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhܰ+A; J arrival timeXh/ JXh4 JslackXh!y@ ~g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsul@}Aܰ+ARh.@@A=А=!y@ Y>̼?r(@h-??-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhj> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh Y>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhܰ+A; J arrival timeXh/ JXh4 JslackXh!y@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuS@}A+ARh.@@A=А=+cy@ Y>̼?A(@h-??-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh33> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh Y>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh+A; J arrival timeXhR/ JXh4 JslackXh+cy@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuS@}A+ARh.@@A=А=+cy@ Y>̼?A(@h-??-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh33> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh Y>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh+A; J arrival timeXhR/ JXh4 JslackXh+cy@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuS@}A+ARh.@@A=А=+cy@ Y>̼?A(@h-??-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I3 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr(> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh33> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhNb@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh Y>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh+A; J arrival timeXhR/ JXh4 JslackXh+cy@   txoutclk_out[0]_49txoutclk_out[0]_49!)Ë>?1Ë>@9AË>?IË>@e >hq} c= ѣ> rise - rise rise - rise  2/+i_tcds2_if/prbs_generator/data_o_reg[102]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu'>}(I,쥛=+?I,?c=Oʡ={=q=F>=.>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/prbs_generator/data_o_reg[102]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=r /+i_tcds2_if/txdatapath_inst/UPS/FEC5L1/Q[34] Jnet (fo=1, routed)Xh)\=s EAi_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData[44]_i_1__1/I2 JXhzr D@i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData[44]_i_1__1/OProp_B6LUT_SLICEL_I2_O JLUT6Xhzr< FBi_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData[44]_i_1__1_n_0 Jnet (fo=1, routed)Xhu<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]/D JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh>X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[102]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L1/CLK Jnet (fo=539, routed)XhJ ?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]/C JFDREXhzr> Jclock pessimismXhO ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh(; J arrival timeXh&1?/ JXh4 JslackXhc=.*i_tcds2_if/prbs_generator/node_ff_reg[2]/C/+i_tcds2_if/prbs_generator/data_o_reg[136]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu+>}(I,奛=+?I,?9\=Ov=E=q=F>=,>k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR){ .*i_tcds2_if/prbs_generator/node_ff_reg[2]/QProp_HFF_SLICEL_C_Q JFDSEXhzrD=u 1-i_tcds2_if/prbs_generator/node_array[1]_15[1] Jnet (fo=47, routed)Xh=^ 0,i_tcds2_if/prbs_generator/data_o[136]_i_1/I1 JXhzr /+i_tcds2_if/prbs_generator/data_o[136]_i_1/OProp_G6LUT_SLICEL_I1_O JLUT6Xhzr<v 3/i_tcds2_if/prbs_generator/node_array[134]_23[2] Jnet (fo=1, routed)XhA`e<a /+i_tcds2_if/prbs_generator/data_o_reg[136]/D JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh>X5Y0 (CLOCK_ROOT)` .*i_tcds2_if/prbs_generator/node_ff_reg[2]/C JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)XhI ?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[136]/C JFDREXhzr> Jclock pessimismXhOw -)i_tcds2_if/prbs_generator/data_o_reg[136]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh(; J arrival timeXh1?/ JXh4 JslackXh9\=/1/+i_tcds2_if/prbs_generator/data_o_reg[119]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu)>}L7)D, ='1?D,?6=Oʡ=-=q=µ>=@5>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/prbs_generator/data_o_reg[119]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=q .*i_tcds2_if/txdatapath_inst/UPS/FEC5H0/Q[2] Jnet (fo=2, routed)Xhrh=s EAi_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData[42]_i_1__0/I1 JXhzr D@i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData[42]_i_1__0/OProp_H6LUT_SLICEL_I1_O JLUT6Xhzr< FBi_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData[42]_i_1__0_n_0 Jnet (fo=1, routed)Xho<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]/D JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh>X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[119]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5H0/CLK Jnet (fo=539, routed)XhM?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]/C JFDREXhzr> Jclock pessimismXhO ?;i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhL7); J arrival timeXh 2?/ JXh4 JslackXh6=@}#D,l=?D,?~$=ϥo=Q=q=!>=@5>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR) @X5Y0 (CLOCK_ROOT)r @ -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)XhM?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[40]/C JFDSEXhzr> Jclock pessimismXhϥ ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[40]Hold_DFF_SLICEL_C_D JFDSEXhA`e=/ JXh< J required timeXh#; J arrival timeXh|.?/ JXh4 JslackXh~$=A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[14]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu>}$,0H=L7 ?,?'=u2%==q=η>=S>k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR) A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[14]/QProp_HFF_SLICEL_C_Q JFDSEXhzrD= EAi_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[59]_0[11] Jnet (fo=6, routed)Xhrh=p B>i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[53]_i_1/I5 JXhzr A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[53]_i_1/OProp_A6LUT_SLICEL_I5_O JLUT6Xhzru< C?i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[53]_i_1_n_0 Jnet (fo=1, routed)XhD<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]/D JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= -)i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK Jnet (fo=539, routed)Xh>X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[14]/C JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK Jnet (fo=539, routed)Xh]?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]/C JFDSEXhzr> Jclock pessimismXhu2 ?;i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]Hold_AFF_SLICEL_C_D JFDSEXhA`e=/ JXh< J required timeXh$; J arrival timeXh.?/ JXh4 JslackXh'=i0,i_tcds2_if/txgearbox_inst/dataWord_reg[28]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[28]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuS>}0#uff?#?'==I9H=!>q=->=Ը>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[28]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[28] Jnet (fo=1, routed)Xh!> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[28] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)XhMb>X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[28]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)Xhe;>X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh=I i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[28] J GTHE3_CHANNELXhX9>/ JXh< J required timeXh0; J arrival timeXhYd;?/ JXh4 JslackXh'=2/+i_tcds2_if/prbs_generator/data_o_reg[192]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu+>}+'~*-\=y?~*?'=Ov=E=q=33>=>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/prbs_generator/data_o_reg[192]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=r /+i_tcds2_if/txdatapath_inst/UPS/FEC5H1/Q[12] Jnet (fo=2, routed)Xh-=s EAi_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[57]_i_1__0/I1 JXhzr D@i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[57]_i_1__0/OProp_E6LUT_SLICEL_I1_O JLUT6Xhzr< FBi_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[57]_i_1__0_n_0 Jnet (fo=1, routed)XhD<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]/D JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xhsh>X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[192]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK Jnet (fo=539, routed)XhA?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]/C JFDREXhzr> Jclock pessimismXhO ?;i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]Hold_EFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh+'; J arrival timeXh1?/ JXh4 JslackXh'=)/+i_tcds2_if/prbs_generator/data_o_reg[192]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT4=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu1,>}+'~*-\=y?~*?5,=Ov=Q=q=33>=>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/prbs_generator/data_o_reg[192]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=r /+i_tcds2_if/txdatapath_inst/UPS/FEC5H1/Q[12] Jnet (fo=2, routed)Xhw=p B>i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[18]_i_1/I1 JXhzr A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[18]_i_1/OProp_F6LUT_SLICEL_I1_O JLUT4Xhzr< C?i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[18]_i_1_n_0 Jnet (fo=1, routed)XhD<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]/D JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xhsh>X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[192]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK Jnet (fo=539, routed)XhA?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]/C JFDSEXhzr> Jclock pessimismXhO ?;i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]Hold_FFF_SLICEL_C_D JFDSEXhA`e=/ JXh< J required timeXh+'; J arrival timeXh1?/ JXh4 JslackXh5,=)/+i_tcds2_if/prbs_generator/data_o_reg[214]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu >}$&x) q=9?x)?5,=Oo=v=q=ȶ>=b>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/prbs_generator/data_o_reg[214]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=r /+i_tcds2_if/txdatapath_inst/UPS/FEC5H1/Q[31] Jnet (fo=1, routed)Xh-=p B>i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[40]_i_1/I2 JXhzr A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[40]_i_1/OProp_C6LUT_SLICEL_I2_O JLUT6Xhzru< C?i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[40]_i_1_n_0 Jnet (fo=1, routed)Xho<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]/D JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh>X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[214]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK Jnet (fo=539, routed)Xhv>X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]/C JFDSEXhzr> Jclock pessimismXhO ?;i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]Hold_CFF_SLICEL_C_D JFDSEXhA`e=/ JXh< J required timeXh$&; J arrival timeXh`0?/ JXh4 JslackXh5,=}A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[28]/C@}r=*i-|h=^ ?i-? 0=Oʡ=5^=q=Ը>=A>k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR) A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[28]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[59]_0[23] Jnet (fo=7, routed)Xhʡ=o A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[9]_i_1/I2 JXhzr @i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[9]_i_1_n_0 Jnet (fo=1, routed)XhD<r @ >X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[28]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK Jnet (fo=539, routed)XhS?X5Y0 (CLOCK_ROOT)r @ Jclock pessimismXhO >:i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[9]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhr=*; J arrival timeXh~?5?/ JXh4 JslackXh 0=WXTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C0,i_tcds2_if/txgearbox_inst/dataWord_reg[23]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu@}G@X]@?E??G@=А= >; =V>'1@x=u?=zT?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>h #i_tcds2_if/txgearbox_inst/SR[0] Jnet (fo=273, routed)Xh'1@b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[23]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)XhOm?X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[23]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXhy .*i_tcds2_if/txgearbox_inst/dataWord_reg[23]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhX]@; J arrival timeXhX9|/ JXh4 JslackXh >XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]/S"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuL7@}G@O@r=x齵E?r=?G@=А=>; =V>Q@x=u?=U?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>t /+i_tcds2_if/txdatapath_inst/UPS/FEC5L0/SR[0] Jnet (fo=273, routed)XhQ@s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]/S JFDSEXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)Xhn?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]/C JFDSEXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXh ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]Setup_DFF_SLICEL_C_S JFDSEXhĽ/ JXh< J required timeXhO@; J arrival timeXhZ|/ JXh4 JslackXh>XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuL7@}G@O@r=x齵E?r=?G@=А=>; =V>Q@x=u?=U?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>t /+i_tcds2_if/txdatapath_inst/UPS/FEC5L0/SR[0] Jnet (fo=273, routed)XhQ@s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)Xhn?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXh ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]Setup_CFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhO@; J arrival timeXhZ|/ JXh4 JslackXh>XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuL7@}G@O@r=x齵E?r=?G@=А=>; =V>Q@x=u?=U?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>t /+i_tcds2_if/txdatapath_inst/UPS/FEC5L0/SR[0] Jnet (fo=273, routed)XhQ@s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)Xhn?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXh ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]Setup_BFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhO@; J arrival timeXhZ|/ JXh4 JslackXh>XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]/S"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuL7@}G@O@r=x齵E?r=?G@=А=>; =V>Q@x=u?=U?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>t /+i_tcds2_if/txdatapath_inst/UPS/FEC5L1/SR[0] Jnet (fo=273, routed)XhQ@s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]/S JFDSEXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L1/CLK Jnet (fo=539, routed)Xhn?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]/C JFDSEXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXh ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]Setup_AFF_SLICEL_C_S JFDSEXhĽ/ JXh< J required timeXhO@; J arrival timeXhZ|/ JXh4 JslackXh>WXTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C0,i_tcds2_if/txgearbox_inst/dataWord_reg[27]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuMb@}G@(U@XE?X?G@=А=)>; =V>|@x=u?=S?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>h #i_tcds2_if/txgearbox_inst/SR[0] Jnet (fo=273, routed)Xh|@b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[27]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xhl?X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[27]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXhy .*i_tcds2_if/txgearbox_inst/dataWord_reg[27]Setup_HFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh(U@; J arrival timeXh{/ JXh4 JslackXh)>XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Ci_tcds2_if/tx_div_reg[1]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu@}G@ @c$E?c?G@=А=:?; =V>;@x=u?=shQ?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>\ i_tcds2_if/tx_reset Jnet (fo=273, routed)Xh;@P i_tcds2_if/tx_div_reg[1]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>t i_tcds2_if/txusrclk_out Jnet (fo=539, routed)Xhq=j?X5Y0 (CLOCK_ROOT)P i_tcds2_if/tx_div_reg[1]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXhg i_tcds2_if/tx_div_reg[1]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh @; J arrival timeXhls/ JXh4 JslackXh:?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Ci_tcds2_if/tx_div_reg[0]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu@}G@@c$E?c?G@=А=D?; =V>;@x=u?=shQ?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>\ i_tcds2_if/tx_reset Jnet (fo=273, routed)Xh;@P i_tcds2_if/tx_div_reg[0]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>t i_tcds2_if/txusrclk_out Jnet (fo=539, routed)Xhq=j?X5Y0 (CLOCK_ROOT)P i_tcds2_if/tx_div_reg[0]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXhh i_tcds2_if/tx_div_reg[0]Setup_CFF2_SLICEL_C_R JFDREXhv/ JXh< J required timeXh@; J arrival timeXhls/ JXh4 JslackXhD?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Ci_tcds2_if/tx_div_reg[2]/R"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_18_CLK_OUT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu@}G@@c$E?c?G@=А=D?; =V>;@x=u?=shQ?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>\ i_tcds2_if/tx_reset Jnet (fo=273, routed)Xh;@P i_tcds2_if/tx_div_reg[2]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>t i_tcds2_if/txusrclk_out Jnet (fo=539, routed)Xhq=j?X5Y0 (CLOCK_ROOT)P i_tcds2_if/tx_div_reg[2]/C JFDREXhzr> Jclock pessimismXh; =@ Jclock uncertaintyXhh i_tcds2_if/tx_div_reg[2]Setup_DFF2_SLICEL_C_R JFDREXhv/ JXh< J required timeXh@; J arrival timeXhls/ JXh4 JslackXhD?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C@E@x=u?=Q?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>t /+i_tcds2_if/txdatapath_inst/UPS/FEC5L1/SR[0] Jnet (fo=273, routed)XhE@r @ ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhx?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L1/CLK Jnet (fo=539, routed)Xh~j?X5Y0 (CLOCK_ROOT)r @ Jclock pessimismXh; =@ Jclock uncertaintyXh >:i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[1]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh;@; J arrival timeXhMr/ JXh4 JslackXh?( !gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!)y@1y @9Ay@Iy @e"@hq} *\= ># rise - rise rise - rise  m0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/CGCSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>} kn#1>R@n@*\=433"=/>…?D?M?K@z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)} 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/QProp_AFF_SLICEM_C_Q JFDCEXhzr"=p -)SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/Q[6] Jnet (fo=5, routed)Xh/>y GCSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&9@X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhrP@X4Y6 (CLOCK_ROOT)y GCSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/C JFDREXhzr> Jclock pessimismXh433 EASFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]Hold_GFF2_SLICEL_C_D JFDREXho>/ JXh< J required timeXh k; J arrival timeXh{n@/ JXh4 JslackXh*\=s0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[29]/CHDSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuV>}ƿpͿ=İ?p?E="۽9H= #>>lG?C ?B`e?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)~ 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[29]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/Q[13] Jnet (fo=2, routed)Xh #>z HDSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y6 (CLOCK_ROOT)z HDSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C JFDREXhzr> Jclock pessimismXh"۽ FBSFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]Hold_EFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXhƿ; J arrival timeXh?/ JXh4 JslackXhE=@+'SFP_GEN[12].rx_data_ngccm_reg[12][57]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}ƿ/Ϳ(>5^?/?`="۽l=+>>:?C ?1d?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)y +'SFP_GEN[12].rx_data_ngccm_reg[12][57]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[49] Jnet (fo=1, routed)Xh$>_ 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[56]_i_1/I0 JXhzr 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[56]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr=u 2.SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[56]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)XhC?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][57]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXh"۽x .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhƿ; J arrival timeXh?/ JXh4 JslackXh`=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}ɿ пJ>? ?`="۽ʡ="[>>d8?C ?j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)XhJ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/OProp_D6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh"۽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhɿ; J arrival timeXh?/ JXh4 JslackXh`=+'SFP_GEN[12].rx_data_ngccm_reg[12][28]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuGa>}+ǿ.Ϳ= ?.?#="۽D= 0>>$F?C ?Ve?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)y +'SFP_GEN[12].rx_data_ngccm_reg[12][28]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrD=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] Jnet (fo=1, routed)Xh 0>b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh%?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][28]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXh"۽x .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh+ǿ; J arrival timeXhI?/ JXh4 JslackXh#=+'SFP_GEN[12].rx_data_ngccm_reg[12][31]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuMb>}+ǿ.Ϳ= ?.?'="۽D=&1>>$F?C ?Ve?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)y +'SFP_GEN[12].rx_data_ngccm_reg[12][31]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[23] Jnet (fo=1, routed)Xh&1>b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh%?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][31]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr> Jclock pessimismXh"۽x .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh+ǿ; J arrival timeXhj?/ JXh4 JslackXh'=A+'SFP_GEN[12].rx_data_ngccm_reg[12][38]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu(\>}~?ſ˿=??'="۽> => C?C ?L b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)y +'SFP_GEN[12].rx_data_ngccm_reg[12][38]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[30] Jnet (fo=1, routed)XhP=_ 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[38]_i_1/I1 JXhzr 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[38]_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3XhzrT=u 2.SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[38]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh<ߟ?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][38]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh"۽y .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh~?ſ; J arrival timeXh~?/ JXh4 JslackXh'=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu^d;>} п=p? ?e*= >=E=>@?C ?j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__11/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__11/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh1?/ JXh4 JslackXhe*=3*&SFP_GEN[12].rx_data_ngccm_reg[12][0]/C/+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu_>}"˿ѿp=>I??,="۽=y&>>v>?C ?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)w *&SFP_GEN[12].rx_data_ngccm_reg[12][0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] Jnet (fo=1, routed)Xh+>^ 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[0]_i_1/I1 JXhzr /+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[0]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3Xhzrrh=t 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh/?X4Y6 (CLOCK_ROOT)\ *&SFP_GEN[12].rx_data_ngccm_reg[12][0]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhD?X4Y6 (CLOCK_ROOT)a /+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh"۽w -)SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh"˿; J arrival timeXh?/ JXh4 JslackXh,=?+'SFP_GEN[12].rx_data_ngccm_reg[12][41]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]/D"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuGa>}gfƿ̿=??D,="۽[=>>E?C ?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)x +'SFP_GEN[12].rx_data_ngccm_reg[12][41]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] Jnet (fo=1, routed)Xhe;=_ 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[40]_i_1/I0 JXhzr 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<=u 2.SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][41]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhη?X4Y6 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXh"۽x .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhgfƿ; J arrival timeXh?/ JXh4 JslackXhD,=t!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu@}A}Rp?Q@M??…?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzre;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/OProp_D5LUT_SLICEL_I2_O JLUT4Xhzr= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 Jnet (fo=1, routed)XhI > okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr)> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 Jnet (fo=2, routed)Xh(> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh}Rp?Q@M??…?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzre;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/OProp_D5LUT_SLICEL_I2_O JLUT4Xhzr= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 Jnet (fo=1, routed)XhI > okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr)> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 Jnet (fo=2, routed)Xh(> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh}R?@M??…?u?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzfe;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhP> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzrgff> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+7@X4Y6 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhf?@M??…?u?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzfe;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhP> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzrgff> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+7@X4Y6 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhf?`@M??…?u?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzfe;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhP> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzrgff> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh-> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+7@X4Y6 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhAs?`@M??…?u?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzfe;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhP> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzrgff> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh-> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+7@X4Y6 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhAs?`@M??…?u?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzfe;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhP> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzrgff> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh-> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+7@X4Y6 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_FFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhAs?Ā@M??…??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzre;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrgff> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7@X4Y6 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhr{?@M??…??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzre;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrgff> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh > vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7@X4Y6 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh?@M??…??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] Jnet (fo=10, routed)XhuX@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_A6LUT_SLICEL_I1_O JLUT4Xhzre;_> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrgff> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh > vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhFC@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7@X4Y6 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh' rise - rise rise - rise  0,SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[30]/CHDSFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu)>}-=&q?-?;$=P9H==Т>8?η>@5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)} 0,SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[30]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=q .*SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/Q[14] Jnet (fo=2, routed)Xh=z HDSFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhR?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[22].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz?X4Y9 (CLOCK_ROOT)z HDSFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C JFDREXhzr> Jclock pessimismXhP FBSFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhҍ?/ JXh4 JslackXh;$=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsut>}Tk~,= -r?k?Dy;=1=L=Т>\?η>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__21/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__21/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhDy;=]*&SFP_GEN[22].rx_data_ngccm_reg[22][5]/C/+SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu|.>}O-f܆= -r?-?8E=F ף=Q=Т>\?η>@5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)w *&SFP_GEN[22].rx_data_ngccm_reg[22][5]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[83]_0[5] Jnet (fo=1, routed)XhP=^ 0,SFP_GEN[22].ngCCM_gbt/RX_Word_rx40[4]_i_1/I0 JXhzr /+SFP_GEN[22].ngCCM_gbt/RX_Word_rx40[4]_i_1/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzr<t 1-SFP_GEN[22].ngCCM_gbt/RX_Word_rx40[4]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhS?X4Y9 (CLOCK_ROOT)\ *&SFP_GEN[22].rx_data_ngccm_reg[22][5]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz?X4Y9 (CLOCK_ROOT)a /+SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXhFw -)SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhO; J arrival timeXhَ?/ JXh4 JslackXh8E=eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[3]/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu433>}茈J =&q?J ?xM=&SX9=-=Т>8?η>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[3]/QProp_FFF2_SLICEL_C_Q JFDCEXhzrD= fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/Q[3] Jnet (fo=11, routed)Xh= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/I1 JXhzr uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/OProp_H5LUT_SLICEM_I1_O JLUT5Xhzr #= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_I Jnet (fo=1, routed)XhD< |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhR?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh$y?X4Y9 (CLOCK_ROOT) |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh&S zvg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regHold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh茈; J arrival timeXh?/ JXh4 JslackXhxM= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuw>}Tk~,= -r?k?%O=1=Q8=Т>\?η>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__21/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhT; J arrival timeXh(?/ JXh4 JslackXh%O=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[22].rx_data_ngccm_reg[22][31]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu)>}qM'=أp?M?Q=&9H=9=Т>%?η>v?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[22][31] Jnet (fo=1, routed)Xh9=] +'SFP_GEN[22].rx_data_ngccm_reg[22][31]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhnR?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)Xh5^z?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[22].rx_data_ngccm_reg[22][31]/C JFDCEXhzr> Jclock pessimismXh&t )%SFP_GEN[22].rx_data_ngccm_reg[22][31]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhq; J arrival timeXh"?/ JXh4 JslackXhQ=>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsul=}nף;Nbp?n?T=Lo=9H=Т>?η>R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[7] Jnet (fo=5, routed)XhP= vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][7]_i_2__0/I4 JXhzr uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][7]_i_2__0/OProp_A6LUT_SLICEL_I4_O JLUT6Xhzru<m *&g_gbt_bank[1].gbtbank/i_gbt_bank_n_366 Jnet (fo=1, routed)XhD<p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh-R?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xhz?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr> Jclock pessimismXhL <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh阮?/ JXh4 JslackXhT=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsut>}LS=&q?S?V=1=L=Т>8?η> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__21/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhL; J arrival timeXh ?/ JXh4 JslackXhV=>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsux=}nף;Nbp?n?vY=Lo=L=Т>?η>R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[6] Jnet (fo=6, routed)Xh)\= vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][6]_i_1__0/I0 JXhzr uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][6]_i_1__0/OProp_B6LUT_SLICEL_I0_O JLUT5Xhzru<m *&g_gbt_bank[1].gbtbank/i_gbt_bank_n_367 Jnet (fo=1, routed)Xhu<p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh-R?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xhz?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXhL <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhȆ?/ JXh4 JslackXhvY=h,(SFP_GEN[22].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuQ>}ם=~??s\=5l=j=Т>A`%?η>{N?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)y ,(SFP_GEN[22].ngCCM_gbt/pwr_good_pre_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=i &"SFP_GEN[22].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)Xh㥛=_ 1-SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_i_1__42/I1 JXhzr 0,SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_i_1__42/OProp_C6LUT_SLICEL_I1_O JLUT4Xhzro=u 2.SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_i_1__42_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv?X4Y9 (CLOCK_ROOT)^ ,(SFP_GEN[22].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)^ ,(SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXh5t *&SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_regHold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhם; J arrival timeXhk?/ JXh4 JslackXhs\=$fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1 LUT6=4)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A.A1a+@1@A=А= Z@gy^>X?jm@9??r(?`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/QProp_CFF2_SLICEL_C_Q JFDCEXhzrV> rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxencdata_s[10]_52[85] Jnet (fo=10, routed)Xh c? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_17__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_17__21/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_17__21_n_0 Jnet (fo=1, routed)XhR> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_3__21/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_3__21/OProp_E6LUT_SLICEM_I2_O JLUT6Xhzr"y> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/s2_from_syndromes[2] Jnet (fo=36, routed)Xh? ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/i___38_i_1__21/I1 JXhzr hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/i___38_i_1__21/OProp_C6LUT_SLICEM_I1_O JLUT4Xhzf +> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_5__21_0 Jnet (fo=22, routed)Xh> qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__43/I5 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__43/OProp_A6LUT_SLICEM_I5_O JLUT6Xhzr> rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__43_n_0 Jnet (fo=1, routed)Xh(? yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__43/I3 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__43/OProp_D6LUT_SLICEM_I3_O JLUT6Xhzrgff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)Xh*\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh}? @X4Y9 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhgy^>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regSetup_DFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh.A; J arrival timeXh/ JXh4 JslackXh Z@$4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuZ@}A-AL.5@@A=А=i@+\>+?U@9?K ?r(? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[12]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[12] J GTHE3_CHANNELXhzr+? ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/D[14] Jnet (fo=6, routed)XhU@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X4Y9 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]/C JFDCEXhzr> Jclock pessimismXh+\>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]Setup_BFF_SLICEM_C_D JFDCEXh}=/ JXh< J required timeXh-A; J arrival timeXh43/ JXh4 JslackXhi@g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A,AH.5@@A=А=J"s@X&\>֣?y@9?K ?r(?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh^I> yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__22/I3 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__22/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzrgff> _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh-> uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhX&\>@ Jclock uncertaintyXh rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXhv/ JXh4 JslackXhJ"s@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu|@}A,AH.5@@A=А=2ts@X&\>֣?@9?K ?r(?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh^I> yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__22/I3 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__22/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzrgff> _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhX&\>@ Jclock uncertaintyXh rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXhV/ JXh4 JslackXh2ts@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuS@}AH,A1A.5@1@A=А=t@\>?@9?K ?r(?`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrj= qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 Jnet (fo=1, routed)Xh = plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 Jnet (fo=2, routed)XhZ> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhH,A; J arrival timeXh-/ JXh4 JslackXht@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuS@}AH,A1A.5@1@A=А=t@\>?@9?K ?r(?`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrj= qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 Jnet (fo=1, routed)Xh = plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 Jnet (fo=2, routed)XhZ> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhH,A; J arrival timeXh-/ JXh4 JslackXht@ 2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu)\@}A$.Ak.5@k@A=А=%t@[> ?L7I@9?K ?r(?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)XhL7I@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X4Y9 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]Setup_HFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh$.A; J arrival timeXh@5/ JXh4 JslackXh%t@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A+AL.5@@A=А=t@+\>= ?!@9?K ?r(? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/I5 JXhzr zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhb> wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X4Y9 (CLOCK_ROOT) vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh+\>@ Jclock uncertaintyXh tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXht@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A+AL.5@@A=А=t@+\>= ?_!@9?K ?r(? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/I5 JXhzr zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X4Y9 (CLOCK_ROOT) vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh+\>@ Jclock uncertaintyXh tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXhx/ JXh4 JslackXht@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A+AL.5@@A=А=t@+\>= ?_!@9?K ?r(? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhb? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/I5 JXhzr zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X4Y9 (CLOCK_ROOT) vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh+\>@ Jclock uncertaintyXh tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXhx/ JXh4 JslackXht@ ( !gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!)y@1y @9Ay@Iy @e/$J@hq}  =  >+ rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*&SFP_GEN[23].rx_data_ngccm_reg[23][1]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}e;Ͽ@l=?e;? =XYD==Q>>? ?rh?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=U rx_data[23][1] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[23].rx_data_ngccm_reg[23][1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)\ *&SFP_GEN[23].rx_data_ngccm_reg[23][1]/C JFDCEXhzr> Jclock pessimismXhXYs ($SFP_GEN[23].rx_data_ngccm_reg[23][1]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXh =E+'SFP_GEN[23].rx_data_ngccm_reg[23][68]/C0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu/>}1%?5οV=I??5?Y;=Y`=T=Q>@5>? ?gff?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)x +'SFP_GEN[23].rx_data_ngccm_reg[23][68]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[60] Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[68]_i_1/I1 JXhzr 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[68]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrY=u 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[68]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[23].rx_data_ngccm_reg[23][68]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXhYx .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1%; J arrival timeXh?/ JXh4 JslackXhY;=E+'SFP_GEN[23].rx_data_ngccm_reg[23][32]/C0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu/>}ϿXQ=??@=X=`P=Q>7A? ?N7i?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)x +'SFP_GEN[23].rx_data_ngccm_reg[23][32]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[32]_i_1/I1 JXhzr 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[32]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzr/]=u 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[32]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xhٞ?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[23].rx_data_ngccm_reg[23][32]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhXx .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh@=E+'SFP_GEN[23].rx_data_ngccm_reg[23][44]/C0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuz>}v<Ͽ>)=|?A? ?_i?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)x +'SFP_GEN[23].rx_data_ngccm_reg[23][44]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[44]_i_1/I1 JXhzr 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[44]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT3XhzrQ8=u 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[23].rx_data_ngccm_reg[23][44]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXhCdx .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhv; J arrival timeXhأ?/ JXh4 JslackXhNLC=U.*SFP_GEN[23].ngccm_status_reg_reg[23][23]/C.*SFP_GEN[23].ngccm_status_reg_reg[23][23]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsui;=}ff|Ͽ֣;?|?D=&o=Q8=Q>B? ?h?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR){ .*SFP_GEN[23].ngccm_status_reg_reg[23][23]/QProp_AFF_SLICEM_C_Q JFDPEXhzr9H= GCSFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg_reg[23][24]_0[7] Jnet (fo=2, routed)Xh+=s EASFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg[23][23]_i_1/I0 JXhzr D@SFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg[23][23]_i_1/OProp_A6LUT_SLICEM_I0_O JLUT2Xhzru<b SFP_GEN[23].ngCCM_gbt_n_394 Jnet (fo=1, routed)XhD<` .*SFP_GEN[23].ngccm_status_reg_reg[23][23]/D JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh|?X4Y8 (CLOCK_ROOT)` .*SFP_GEN[23].ngccm_status_reg_reg[23][23]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh5^?X4Y8 (CLOCK_ROOT)` .*SFP_GEN[23].ngccm_status_reg_reg[23][23]/C JFDPEXhzr> Jclock pessimismXh&v ,(SFP_GEN[23].ngccm_status_reg_reg[23][23]Hold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXhff; J arrival timeXhD?/ JXh4 JslackXhD=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsun>}bַOͿp~=l?O?K=$e=9H=Q>p=? ?d?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__22/OProp_E6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh̜?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh$e g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_EFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhbַ; J arrival timeXh>5?/ JXh4 JslackXhK=^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/C^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuS=}ffף;'1?ff?L=?lo=@=Q>? ?6?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/ready_from_bitSlipCtrller_11 Jnet (fo=2, routed)Xh)\= c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_i_1__22/I2 JXhzr b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_i_1__22/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< d`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_i_1__22_n_0 Jnet (fo=1, routed)XhD< ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= TPg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> TPg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK Jnet (fo=674, routed)XhG?X4Y8 (CLOCK_ROOT) ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh?l \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhff?/ JXh4 JslackXhL=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuT>}h\Ϳ.?)=l??ٕO=f e=/]=Q>p=? ?̡e?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__22/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh̜?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhf e g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhh\; J arrival timeXhپ?/ JXh4 JslackXhٕO=u0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[27]/CHDSFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuw>}ɹ@5ο)=O?@5?%S= \9H==Q>A@? ?iff?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)} 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[27]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/Q[11] Jnet (fo=2, routed)Xh=z HDSFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[23].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)z HDSFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C JFDREXhzr> Jclock pessimismXh \ FBSFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhɹ; J arrival timeXhNb?/ JXh4 JslackXh%S=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuz>}bַOͿp~=l?O? T=$e=`P=Q>p=? ?d?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__22/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__22/OProp_H6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh̜?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh$e g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhbַ; J arrival timeXhv?/ JXh4 JslackXh T={!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuZ@}A6A:@sף`@:@A=А=/$J@>?&I@?6?E?1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhk @ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr/> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 Jnet (fo=1, routed)Xh@5^> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr`P= qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh&!@X4Y8 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh6A; J arrival timeXhV/ JXh4 JslackXh/$J@ {!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuZ@}A6A:@sף`@:@A=А=/$J@>?&I@?6?E?1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhk @ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr/> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 Jnet (fo=1, routed)Xh@5^> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr`P= qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh&!@X4Y8 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh6A; J arrival timeXhV/ JXh4 JslackXh/$J@ 5"fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[94]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=3)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu̔@}A8A:2(l@:@A=А=2M@> -r?Vm@?I@E?1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[94]/QProp_FFF2_SLICEL_C_Q JFDCEXhzrO > rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxencdata_s[11]_51[25] Jnet (fo=11, routed)Xh!> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_12__22/I4 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_12__22/OProp_G6LUT_SLICEL_I4_O JLUT6Xhzre;_> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_12__22_n_0 Jnet (fo=1, routed)Xhv> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_2__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_2__22/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`> ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[92]_0[0] Jnet (fo=43, routed)Xhv@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__22/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__22/OProp_C6LUT_SLICEM_I1_O JLUT4Xhzr> rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__22_n_0 Jnet (fo=1, routed)Xh> yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__46/I2 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__46/OProp_H6LUT_SLICEM_I2_O JLUT6Xhzrgff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_3 Jnet (fo=1, routed)Xh*\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhM@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[94]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK Jnet (fo=674, routed)Xh&!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_regSetup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh8A; J arrival timeXhp/ JXh4 JslackXh2M@+Q$fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[80]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=4)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu~?@}A9Ao;cyTm@o;@A=А=S@ >…?_@?@E??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[80]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrO > ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/Q[32] Jnet (fo=11, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__22/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__22/OProp_C6LUT_SLICEL_I1_O JLUT6Xhzr(> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__22_n_0 Jnet (fo=1, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__22/OProp_C6LUT_SLICEM_I0_O JLUT6XhzrA`e> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/s1_from_syndromes[0] Jnet (fo=33, routed)Xh@ rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__22/OProp_C6LUT_SLICEM_I2_O JLUT4XhzfA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__22_n_0 Jnet (fo=1, routed)XhI> qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__45/I4 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__45/OProp_G6LUT_SLICEL_I4_O JLUT6Xhzr+> rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__45_n_0 Jnet (fo=1, routed)Xh/$> yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__45/I3 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__45/OProp_B6LUT_SLICEL_I3_O JLUT6Xhzr+> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)Xh+= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|O@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[80]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regSetup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXh9A; J arrival timeXh/ JXh4 JslackXhS@!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu/ݠ@}A&>AwOr<ף`@wO@A=А=;V@w<>O?o{@?6?E?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[0] Jnet (fo=10, routed)Xho{@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhE6@X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]/C JFDCEXhzr> Jclock pessimismXhw<>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]Setup_HFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh&>A; J arrival timeXh/ JXh4 JslackXh;V@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu@}A=AgfN! <ף`@gfN@A=А= Z@w<> ?)v@?6?E??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xh)v@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh4@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXhw<>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh=A; J arrival timeXh+/ JXh4 JslackXh Z@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu{?@}A.>AO? s@?6?E?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[0] Jnet (fo=10, routed)Xh s@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhff6@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]/C JFDCEXhzr> Jclock pessimismXhw<>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh.>A; J arrival timeXh/ JXh4 JslackXh]@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu-@}A6AM:ף`@M:@A=А= ]@>A`?9@?6?E?Zd?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhk @ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh1,> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/I5 JXhzr zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh:? wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh6A; J arrival timeXh~/ JXh4 JslackXh ]@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu@}A =A{Nl`;ף`@{N@A=А=.^@w<>?Tm@?6?E??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)XhTm@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh4@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr> Jclock pessimismXhw<>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh =A; J arrival timeXh?5/ JXh4 JslackXh.^@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuH @}A6AM:ף`@M:@A=А=n^@>A`?th9@?6?E?Zd?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhk @ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh1,> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/I5 JXhzr zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhq=B@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh6A; J arrival timeXh5^/ JXh4 JslackXhn^@ ( !gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!)y@1y @9Ay@Iy @eV@hq} =  >. rise - rise rise - rise  "rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/Cb^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuv>}`^W\=?W?=>o=j= >$?A`?~*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/QProp_HFF2_SLICEM_C_Q JFDCEXhzfD= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnt[1] Jnet (fo=6, routed)Xh㥛= gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_inv_i_1__13/I2 JXhzf fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_inv_i_1__13/OProp_D6LUT_SLICEM_I2_O JLUT6Xhzro< ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xho< b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y6 (CLOCK_ROOT) rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXh> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_invHold_DFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh`^; J arrival timeXh`?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuj<>}àp `=ҍ?p?==Q= >?A`?C+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__12/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__12/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhà; J arrival timeXhA`?/ JXh4 JslackXh=$eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuQ8>}:@&=??.=9H=$> >(1?A`?r=*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[30] Jnet (fo=1, routed)Xh$> eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhΗ?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh:@; J arrival timeXh?/ JXh4 JslackXh.=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[13].rx_data_ngccm_reg[13][43]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu|?>}y.|=?.?v=D=V> >(1?A`?+?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_GFF_SLICEM_C_Q JFDREXhzrD=V rx_data[13][43] Jnet (fo=1, routed)XhV>] +'SFP_GEN[13].rx_data_ngccm_reg[13][43]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh.}?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xhu?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][43]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[13].rx_data_ngccm_reg[13][43]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhy; J arrival timeXhU?/ JXh4 JslackXhv=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu|?>}àp `=ҍ?p?r==1= >?A`?C+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__12/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__12/OProp_C5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhà; J arrival timeXh¥?/ JXh4 JslackXhr=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuj<>}`W0=ҍ?W?I==Q= >?A`?~*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__12/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__12/OProp_H6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh`; J arrival timeXhA`?/ JXh4 JslackXhI=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[13].rx_data_ngccm_reg[13][37]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuw>}.H_^=?.?ڦ"=*>9H== >p= ?A`?+?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[13][37] Jnet (fo=1, routed)Xh=] +'SFP_GEN[13].rx_data_ngccm_reg[13][37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xhu?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][37]/C JFDCEXhzr> Jclock pessimismXh*>t )%SFP_GEN[13].rx_data_ngccm_reg[13][37]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXhڦ"=esog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu>}OU=َ?O?W3=R>o=X9= > ?A`? +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] Jnet (fo=29, routed)Xht= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[21]_i_1__11/I2 JXhzr ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[21]_i_1__11/OProp_D6LUT_SLICEL_I2_O JLUT5Xhzru< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[21] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|?X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]/C JFDCEXhzr> Jclock pessimismXhR> c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXhW3=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C+'SFP_GEN[13].rx_data_ngccm_reg[13][54]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu >}/jV=S?/?6=(>9H== >_ ?A`?*?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[13][54] Jnet (fo=1, routed)Xh=] +'SFP_GEN[13].rx_data_ngccm_reg[13][54]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xhc?X4Y6 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][54]/C JFDCEXhzr> Jclock pessimismXh(>s )%SFP_GEN[13].rx_data_ngccm_reg[13][54]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXh6=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu]B>}`W0=ҍ?W?{8== = >?A`?~*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__12/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__12/OProp_H5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh`; J arrival timeXh$?/ JXh4 JslackXh{8=}!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsur@}APZ2A"+Io#I@"+@A=А=V@{>2?I:@~?j?p}??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 Jnet (fo=1, routed)XhT= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/OProp_E6LUT_SLICEM_I5_O JLUT6Xhzr{.> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y6 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh{>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhPZ2A; J arrival timeXhB`/ JXh4 JslackXhV@ }!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsur@}APZ2A"+Io#I@"+@A=А=V@{>2?I:@~?j?p}??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 Jnet (fo=1, routed)XhT= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/OProp_E6LUT_SLICEM_I5_O JLUT6Xhzr{.> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y6 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh{>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhPZ2A; J arrival timeXhB`/ JXh4 JslackXhV@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuc@}A]^2A33+Ӈn#I@33+@A=А=}W@${>-?> ?@~?j?p}?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh{> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh${>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh]^2A; J arrival timeXh/ JXh4 JslackXh}W@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuc@}A]^2A33+Ӈn#I@33+@A=А=}W@${>-?> ?@~?j?p}?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh{> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh${>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh]^2A; J arrival timeXh/ JXh4 JslackXh}W@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}Aub2A33+Ӈn#I@33+@A=А=W@${>-?>@~?j?p}?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhC> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh${>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhub2A; J arrival timeXh_/ JXh4 JslackXhW@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}Aub2A33+Ӈn#I@33+@A=А=W@${>-?>@~?j?p}?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhC> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh${>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhub2A; J arrival timeXh_/ JXh4 JslackXhW@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}Aub2A33+Ӈn#I@33+@A=А=W@${>-?>@~?j?p}?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhC> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh${>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhub2A; J arrival timeXh_/ JXh4 JslackXhW@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuC@}A12A(,R_#I@(,@A=А=x Z@{>-?p=@~?j?p}?罹?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhG> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh{>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh12A; J arrival timeXh&1/ JXh4 JslackXhx Z@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu"@}AI2A(,R_#I@(,@A=А=^\Z@{>-?/=@~?j?p}?罹?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh{>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhI2A; J arrival timeXhb/ JXh4 JslackXh^\Z@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsum@}A%N2A*ߕr#I@*@A=А=_@|>#۹?GB@~?j?p}?X9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhʡ> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/OProp_H6LUT_SLICEL_I0_O JLUT6XhzrY= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhI ? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht+@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx@X4Y6 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh|>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh%N2A; J arrival timeXh/ JXh4 JslackXh_@ ( !gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!)y@1y @9Ay@Iy @e5?hq} = >1 rise - rise rise - rise  Feag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuxh>}eİY=n?İ?=M<D== ף>k4?X>Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[28] Jnet (fo=1, routed)Xh= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh䥛?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]/C JFDCEXhzr> Jclock pessimismXhM< c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhe; J arrival timeXh?/ JXh4 JslackXh=Feag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsut>}eİY=n?İ?=M<9H=[= ף>k4?X>Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[29] Jnet (fo=1, routed)Xh[= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh䥛?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]/C JFDCEXhzr> Jclock pessimismXhM< c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhe; J arrival timeXh/ݤ?/ JXh4 JslackXh=sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsucP>}va尿+=*\?a?F =#%=Mb> ף>.?X>IZ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF_SLICEL_C_Q JFDCEXhzfD= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh> jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[38]_i_1__12/I0 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[38]_i_1__12/OProp_C6LUT_SLICEL_I0_O JLUT5Xhzru< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg00[38] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/C JFDCEXhzr> Jclock pessimismXh# c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhv; J arrival timeXhx?/ JXh4 JslackXhF =sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuQ>}va尿+=*\?a?{_$=#%=rh> ף>.?X>IZ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF_SLICEL_C_Q JFDCEXhzfD= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh%> jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[36]_i_1__12/I0 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[36]_i_1__12/OProp_D6LUT_SLICEL_I0_O JLUT5Xhzru< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg00[36] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzr> Jclock pessimismXh# c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh{_$=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu/>}T̬ =;ߏ?̬?0-= ף=5^= ף>/?X>!R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__13/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__13/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĀ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhT; J arrival timeXh¥?/ JXh4 JslackXh0-=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[14].rx_data_ngccm_reg[14][55]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}]Zp;5R=v?p?;='99H== ף>(\/?X>S?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[14][55] Jnet (fo=1, routed)Xh=] +'SFP_GEN[14].rx_data_ngccm_reg[14][55]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_44 Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[14].rx_data_ngccm_reg[14][55]/C JFDCEXhzr> Jclock pessimismXh'9t )%SFP_GEN[14].rx_data_ngccm_reg[14][55]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh]Z; J arrival timeXh33?/ JXh4 JslackXh;=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuX94>}T̬ =;ߏ?̬?1B=E=-= ף>/?X>!R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__13/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__13/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĀ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhT; J arrival timeXhff?/ JXh4 JslackXh1B=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuz>}j&.?)=o?&?LC= TF=`P= ף>6?X>[d[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__13/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__13/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh TF g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhj; J arrival timeXhˡ?/ JXh4 JslackXhLC=_[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress_reg[2]/C]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@>}V} q=C? ?C=} ף=/= ף>(?X>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress_reg[2]/QProp_HFF2_SLICEM_C_Q JFDCEXhzfD= YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress[2] Jnet (fo=8, routed)Xhj= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_i_1__13/I3 JXhzf a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_i_1__13/OProp_H6LUT_SLICEM_I3_O JLUT6Xhzro= WSg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd Jnet (fo=1, routed)Xho< ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhGz?X4Y7 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X4Y7 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXh} [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_regHold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhV}; J arrival timeXh?/ JXh4 JslackXhC=<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsui;=}q=<߯ף;n?<߯?D=cffo=Q8= ף>k4?X>X?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt_reg[2][7]_0[3] Jnet (fo=9, routed)Xh+= sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt[2][3]_i_1__0/I0 JXhzr rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt[2][3]_i_1__0/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru<m *&g_gbt_bank[1].gbtbank/i_gbt_bank_n_250 Jnet (fo=1, routed)XhD<n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C JFDCEXhzr> Jclock pessimismXhcff :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhq=; J arrival timeXhNb?/ JXh4 JslackXhD= !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuK7@}Ar2Ak,^@0=r8@k,@A=А=5?gtg>(\?A`@Yd;?ff?q=*?sh?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhu> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr +> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 Jnet (fo=2, routed)Xh<> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhr2A; J arrival timeXhQ/ JXh4 JslackXh5? !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuK7@}Ar2Ak,^@0=r8@k,@A=А=5?gtg>(\?A`@Yd;?ff?q=*?sh?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhu> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr +> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 Jnet (fo=2, routed)Xh<> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhr2A; J arrival timeXhQ/ JXh4 JslackXh5? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}Ak2AC+$<r8@C+@A=А=?gtg>Mb?@Yd;?ff?q=*?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh33> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhk2A; J arrival timeXh/ JXh4 JslackXh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}A2AC+$<r8@C+@A=А=?gtg>Mb?h@Yd;?ff?q=*?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh2A; J arrival timeXh/ JXh4 JslackXh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}Aj2A,',=r8@,@A=А=?gtg>Mb?@Yd;?ff?q=*?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhr> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhj2A; J arrival timeXh/ JXh4 JslackXh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}An2A,',=r8@,@A=А=ʗ?gtg>Mb?a@Yd;?ff?q=*?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhx> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhn2A; J arrival timeXh/ JXh4 JslackXhʗ? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}An2A,',=r8@,@A=А=ʗ?gtg>Mb?a@Yd;?ff?q=*?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhx> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhn2A; J arrival timeXh/ JXh4 JslackXhʗ? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu^@}A%Z2A,(=r8@,@A=А='@gtg>Mb?ˡ@Yd;?ff?q=*?&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh!> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh%Z2A; J arrival timeXh/ JXh4 JslackXh'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsun@}AI2A(, c =r8@(,@A=А= @gtg>Mb?@Yd;?ff?q=*?A?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/ݤ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_G6LUT_SLICEM_I3_O JLUT5XhzrZd> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh'1> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhI2A; J arrival timeXh/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuS@}A 2A+<r8@+@A=А=ߟ @gtg>?@Yd;?ff?q=*??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhQx@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__14/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__14/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrx> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh#۹> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI @X4Y7 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhgtg>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh 2A; J arrival timeXhx/ JXh4 JslackXhߟ @ ( !gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!)y@1y @9Ay@Iy @eBQ@hq}  = 5>4 rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuK7>}Qu=Qx?u? =4v= =M>?Q>*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/OProp_A6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhQ; J arrival timeXhp?/ JXh4 JslackXh =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu^d;>}Qu=Qx?u?5=4=E=M>?Q>*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhQ; J arrival timeXh?/ JXh4 JslackXh5=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][66]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu^d;>}scQt=tx?Q?XZ*=D=p= >M>L7 ?Q>p=*?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[15][66] Jnet (fo=1, routed)Xhp= >] +'SFP_GEN[15].rx_data_ngccm_reg[15][66]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^Z?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh33?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][66]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[15].rx_data_ngccm_reg[15][66]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhsc; J arrival timeXhF?/ JXh4 JslackXhXZ*=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuǡE>};c =u??/=([=9=M>$?Q>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__14/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__14/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKW?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhЂ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh;; J arrival timeXht?/ JXh4 JslackXh/="eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[29]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuE6>}彊k֠=r?k?t0=EL 9H=>M>?Q>o#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[29]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[29] Jnet (fo=1, routed)Xh> eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhkT?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]/C JFDCEXhzr> Jclock pessimismXhEL  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh彊; J arrival timeXhA?/ JXh4 JslackXht0=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsut>}"OB`vi5=r?B`?K 3= 1=L=M>?Q>Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__14/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__14/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhkT?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh 1 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh"O; J arrival timeXhm?/ JXh4 JslackXhK 3=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsut>}Drgi5=Qx?r?K 3=y4=L=M>?Q>~*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__14/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__14/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhy4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhD; J arrival timeXh?/ JXh4 JslackXhK 3="eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[30]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu;^:>}</ݔ~ǩ= -r?/ݔ?C4=Q D=L7 >M>?Q>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[30]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[30] Jnet (fo=1, routed)XhL7 > eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[30]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]/C JFDCEXhzr> Jclock pessimismXhQ  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh<; J arrival timeXhNb?/ JXh4 JslackXhC4=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][52]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuv>}orMB[=x?r?CW>=p)9H="=M>x ?Q>~*?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[15][52] Jnet (fo=1, routed)Xh"=] +'SFP_GEN[15].rx_data_ngccm_reg[15][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)XhS?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][52]/C JFDCEXhzr> Jclock pessimismXhp)s )%SFP_GEN[15].rx_data_ngccm_reg[15][52]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXho; J arrival timeXhNb?/ JXh4 JslackXhCW>=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][76]/D""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuv>}F cMB[=bx?c?CW>=p)9H="=M>:?Q>^)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[15][76] Jnet (fo=1, routed)Xh"=] +'SFP_GEN[15].rx_data_ngccm_reg[15][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$Y?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][76]/C JFDCEXhzr> Jclock pessimismXhp)s )%SFP_GEN[15].rx_data_ngccm_reg[15][76]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhF ; J arrival timeXh?/ JXh4 JslackXhCW>=g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][66]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu@}AU-A>F;@@A=А=BQ@Z\>n>+@5^:?p?)?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)XhV?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][66]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)XhU?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][66]/C JFDCEXhzr> Jclock pessimismXhZ\>@ Jclock uncertaintyXhv )%SFP_GEN[15].rx_data_ngccm_reg[15][66]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhU-A; J arrival timeXh8/ JXh4 JslackXhBQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][70]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu@}AU-A>F;@@A=А=BQ@Z\>n>+@5^:?p?)?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)XhV?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][70]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)XhU?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][70]/C JFDCEXhzr> Jclock pessimismXhZ\>@ Jclock uncertaintyXhv )%SFP_GEN[15].rx_data_ngccm_reg[15][70]Setup_BFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhU-A; J arrival timeXh8/ JXh4 JslackXhBQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][65]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuE@}AR-AQ3F;@Q@A=А=xRQ@A\>n>\@5^:?p?)?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)Xhv?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][65]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh,?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][65]/C JFDCEXhzr> Jclock pessimismXhA\>@ Jclock uncertaintyXhv )%SFP_GEN[15].rx_data_ngccm_reg[15][65]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhR-A; J arrival timeXhh/ JXh4 JslackXhxRQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][69]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuE@}AR-AQ3F;@Q@A=А=xRQ@A\>n>\@5^:?p?)?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)Xhv?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh,?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][69]/C JFDCEXhzr> Jclock pessimismXhA\>@ Jclock uncertaintyXhv )%SFP_GEN[15].rx_data_ngccm_reg[15][69]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhR-A; J arrival timeXhh/ JXh4 JslackXhxRQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][73]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuE@}AR-AQ3F;@Q@A=А=xRQ@A\>n>\@5^:?p?)?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)Xhv?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][73]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh,?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][73]/C JFDCEXhzr> Jclock pessimismXhA\>@ Jclock uncertaintyXhv )%SFP_GEN[15].rx_data_ngccm_reg[15][73]Setup_GFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhR-A; J arrival timeXhh/ JXh4 JslackXhxRQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][77]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuƓ@}A%-AA6F;@A@A=А=RQ@\>n>@5^:?p?)?u?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)XhR?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][77]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xhi?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][77]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXhv )%SFP_GEN[15].rx_data_ngccm_reg[15][77]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh%-A; J arrival timeXhʡ/ JXh4 JslackXhRQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][41]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuْ@}A,AVkF;@V@A=А=WQ@,]>n>,@5^:?p?)?k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)Xh ?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][41]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh^?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][41]/C JFDCEXhzr> Jclock pessimismXh,]>@ Jclock uncertaintyXhu )%SFP_GEN[15].rx_data_ngccm_reg[15][41]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh,A; J arrival timeXh9/ JXh4 JslackXhWQ@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][75]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu@}A)-AA6F;@A@A=А=(Q@\>n>+@5^:?p?)?u?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)XhV?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][75]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xhi?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][75]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXhu )%SFP_GEN[15].rx_data_ngccm_reg[15][75]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh)-A; J arrival timeXh8/ JXh4 JslackXh(Q@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][64]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuP@}Al-A>F;@@A=А=̔Q@Z\>n>ff@5^:?p?)?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][64]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)XhU?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][64]/C JFDCEXhzr> Jclock pessimismXhZ\>@ Jclock uncertaintyXhu )%SFP_GEN[15].rx_data_ngccm_reg[15][64]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhl-A; J arrival timeXhsh/ JXh4 JslackXh̔Q@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[15].rx_data_ngccm_reg[15][68]/CE""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuP@}Al-A>F;@@A=А=̔Q@Z\>n>ff@5^:?p?)?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT%@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+>Y rx_data_ngccm[15] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[15].rx_data_ngccm_reg[15][68]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)XhU?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][68]/C JFDCEXhzr> Jclock pessimismXhZ\>@ Jclock uncertaintyXhu )%SFP_GEN[15].rx_data_ngccm_reg[15][68]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhl-A; J arrival timeXhsh/ JXh4 JslackXh̔Q@L( !gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!)y@1y @9Ay@Iy @e~,@hq} = >6 rise - rise rise - rise  Kg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}٘r#~=^?r?=O6o=-=G>$?µ>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/feedbackRegister[1] Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__15/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__15/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?u?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhO6 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh٘; J arrival timeXhV?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}痿X=??I(=7=9H=G>%?µ>p=J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh+= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__15/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__15/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrT= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh7 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh痿; J arrival timeXh/?/ JXh4 JslackXhI(=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuS>}byf= ??.=B6=/]=G>+'?µ>WM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__15/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__15/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrT= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhB6 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhb; J arrival timeXhٞ?/ JXh4 JslackXh.=@+'SFP_GEN[16].rx_data_ngccm_reg[16][33]/C0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsut>} #۩vi5=I?#۩?K 3=0?=L=G>^)?µ>N?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)x +'SFP_GEN[16].rx_data_ngccm_reg[16][33]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[83]_0[25] Jnet (fo=1, routed)XhC =_ 1-SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[32]_i_1/I0 JXhzr 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[32]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[32]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xh5^z?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][33]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh0?x .*SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXhR?/ JXh4 JslackXhK 3=}xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuz>}ZY>.=Q?Z?L>=4%==G>!?µ>C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/QProp_FFF2_SLICEL_C_Q JFDCEXhzfD= {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[2] Jnet (fo=5, routed)Xh)\= jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__15/I0 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__15/OProp_F6LUT_SLICEL_I0_O JLUT3Xhzru< kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__15_n_0 Jnet (fo=1, routed)XhD< eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhnr?X4Y8 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhd;?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXh4 c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_regHold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhL>=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu~>}痿X=??~A=7A`=X94=G>%?µ>p=J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh+= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__15/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__15/OProp_C5LUT_SLICEM_I2_O JLUT3Xhzr%= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[9] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr> Jclock pessimismXh7 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh痿; J arrival timeXh?/ JXh4 JslackXh~A=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[16].rx_data_ngccm_reg[16][53]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsun>}$=·??C=59H==G> ?µ>J B?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[16][53] Jnet (fo=1, routed)Xh=] +'SFP_GEN[16].rx_data_ngccm_reg[16][53]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhshq?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xhv?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][53]/C JFDCEXhzr> Jclock pessimismXh5t )%SFP_GEN[16].rx_data_ngccm_reg[16][53]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhC=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu +>}٘r#~=^?r?H=O6ʡ=X9=G>$?µ>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__15/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__15/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?u?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhO6 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh٘; J arrival timeXh?/ JXh4 JslackXhH=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu(>}c'1^@v=^?'1?h6H=2&6 ף={=G>$?µ>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhO= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__15/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__15/OProp_H6LUT_SLICEM_I2_O JLUT3Xhzro= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?u?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh2&6 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhc; J arrival timeXhٞ?/ JXh4 JslackXhh6H=4*&SFP_GEN[16].rx_data_ngccm_reg[16][1]/C/+SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu)>}-}[=T=G>L7)?µ>WM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)w *&SFP_GEN[16].rx_data_ngccm_reg[16][1]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[83]_0[1] Jnet (fo=1, routed)Xht=^ 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[0]_i_1/I0 JXhzr /+SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[0]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<=t 1-SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xh$y?X4Y8 (CLOCK_ROOT)\ *&SFP_GEN[16].rx_data_ngccm_reg[16][1]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)a /+SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh">w -)SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh-}; J arrival timeXhٞ?/ JXh4 JslackXh.}K=g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuT@}AA3A'1( =D4@'1(@A=А=~,@ h> ?"@9?|?&1(?X?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xh"@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhR@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]Setup_DFF2_SLICEM_C_D JFDCEXhL7=/ JXh< J required timeXhA3A; J arrival timeXh{/ JXh4 JslackXh~,@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsul@}Ay13A'1( =D4@'1(@A=А=a1@ h> ?@9?|?&1(?X?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xh@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhR@X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhy13A; J arrival timeXh/ JXh4 JslackXha1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuC@}A3A)tp=D4@)@A=А=M;@ h>p=?:@9?|?&1(?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xh@ jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[21]_i_1__21/I3 JXhzr ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[21]_i_1__21/OProp_D6LUT_SLICEM_I3_O JLUT5Xhzr"y> `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[21] Jnet (fo=1, routed)Xh*\= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ@X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXhM;@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuI @}A.%1A|'=#<D4@|'@A=А=C@ h>"?+f@9?|?&1(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhNb0@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/OProp_B5LUT_SLICEM_I2_O JLUT4Xhzrj<> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 Jnet (fo=1, routed)Xhw> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 Jnet (fo=2, routed)Xh? kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh.%1A; J arrival timeXh(/ JXh4 JslackXhC@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuI @}A.%1A|'=#<D4@|'@A=А=C@ h>"?+f@9?|?&1(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhNb0@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/OProp_B5LUT_SLICEM_I2_O JLUT4Xhzrj<> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 Jnet (fo=1, routed)Xhw> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 Jnet (fo=2, routed)Xh? kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh.%1A; J arrival timeXh(/ JXh4 JslackXhC@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu4^@}Aj3A)B=D4@)@A=А=cL@ h> ?@9?|?&1(?"?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xh@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhj3A; J arrival timeXhQ/ JXh4 JslackXhcL@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu@}A`-3A (a=D4@ (@A=А=1(M@ h>O?-@9?|?&1(?K7?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[0] Jnet (fo=10, routed)Xh-@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]Setup_HFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh`-3A; J arrival timeXh/ JXh4 JslackXh1(M@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsur@}A J3A(=D4@(@A=А=W@ h>?"{@9?|?&1(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[8]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[8] J GTHE3_CHANNELXhzr? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[10] Jnet (fo=6, routed)Xh"{@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= @X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]Setup_GFF_SLICEM_C_D JFDCEXho=/ JXh< J required timeXh J3A; J arrival timeXhR/ JXh4 JslackXhW@g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuٞ@}A`-3Ac(n=D4@c(@A=А=xZ@ h>O?= w@9?|?&1(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[0] Jnet (fo=10, routed)Xh= w@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]Setup_HFF2_SLICEM_C_D JFDCEXho=/ JXh< J required timeXh`-3A; J arrival timeXh/ JXh4 JslackXhxZ@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu@}A53AA( =D4@A(@A=А=[@ h> ?w@9?|?&1(?x?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xhw@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/C JFDCEXhzr> Jclock pessimismXh h>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]Setup_DFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh53A; J arrival timeXh0/ JXh4 JslackXh[@ ( !gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!)y@1y @9Ay@Iy @e-8@hq} y*=  >7 rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu/>}'f=Đ??y*=s8=`P=G>!2?µ>Y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__16/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__16/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr/]= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhs8 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh'; J arrival timeXhz?/ JXh4 JslackXhy*=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C*&SFP_GEN[17].rx_data_ngccm_reg[17][5]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsut>}͗䥫6=S?䥫?1=99H=\=G>.?µ>-R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[17][5] Jnet (fo=1, routed)Xh\=\ *&SFP_GEN[17].rx_data_ngccm_reg[17][5]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_74 Jnet (fo=674, routed)Xh,?X4Y8 (CLOCK_ROOT)\ *&SFP_GEN[17].rx_data_ngccm_reg[17][5]/C JFDCEXhzr> Jclock pessimismXh9s ($SFP_GEN[17].rx_data_ngccm_reg[17][5]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh͗; J arrival timeXh&?/ JXh4 JslackXh1=eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[32]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu(>}ɞ 4=d;? ?} 2=9H=i=G>/?µ>aP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[32]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[32] Jnet (fo=1, routed)Xhi= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh ?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhɞ; J arrival timeXhZ?/ JXh4 JslackXh} 2=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[17].rx_data_ngccm_reg[17][63]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuj<>}(I ت=p??6=79H=p= >G>1,?µ>Q?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[17][63] Jnet (fo=1, routed)Xhp= >] +'SFP_GEN[17].rx_data_ngccm_reg[17][63]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh |?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_74 Jnet (fo=674, routed)Xhff?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[17].rx_data_ngccm_reg[17][63]/C JFDCEXhzr> Jclock pessimismXh7t )%SFP_GEN[17].rx_data_ngccm_reg[17][63]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh(I; J arrival timeXh?/ JXh4 JslackXh6=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsut>}󘝿,=$??&y;=Y_D=L=G>233?µ>X?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__16/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__16/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh#ۙ?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhY_D g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh󘝿; J arrival timeXht?/ JXh4 JslackXh&y;=`+'SFP_GEN[17].rx_data_ngccm_reg[17][61]/C0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu/>}Xы=p??h?=_ ף=5^=G>1,?µ>zN?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)x +'SFP_GEN[17].rx_data_ngccm_reg[17][61]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[83]_0[53] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[60]_i_1/I0 JXhzr 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[60]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr<u 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[60]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_74 Jnet (fo=674, routed)Xh |?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[17].rx_data_ngccm_reg[17][61]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr> Jclock pessimismXh_x .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhX; J arrival timeXhS?/ JXh4 JslackXhh?=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu #>}'f=Đ?? C=s8l=@=G>!2?µ>Y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__16/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__16/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzro= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhs8 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh'; J arrival timeXh}??/ JXh4 JslackXh C=heag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/Csog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuT>}1Λ`,=d;??K=SBv=Ga=G>/?µ>kT?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut Jnet (fo=5, routed)Xhw= xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter[1]_i_1__21/I0 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter[1]_i_1__21/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ8= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/cnter[1] Jnet (fo=1, routed)Xho< sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh ?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhΗ?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzr> Jclock pessimismXhSB qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1Λ; J arrival timeXh-?/ JXh4 JslackXhK=heag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/Csog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuT>}1Λ`,=d;??K=SBv=Ga=G>/?µ>kT?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut Jnet (fo=5, routed)Xhw= xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__21/I1 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__21/OProp_C6LUT_SLICEL_I1_O JLUT5XhzrQ8= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/cnter[2] Jnet (fo=1, routed)Xho< sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh ?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhΗ?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzr> Jclock pessimismXhSB qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1Λ; J arrival timeXh-?/ JXh4 JslackXhK=sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/Csog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuS=}gfm竿ף;?m?L=@`eo=@=G>V.?µ>!R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= TPg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/sel0[4] Jnet (fo=3, routed)Xh)\= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__17/I5 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__17/OProp_A6LUT_SLICEL_I5_O JLUT6Xhzru< yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__17_n_0 Jnet (fo=1, routed)XhD< sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh~?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhȖ?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh@`e qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhgf; J arrival timeXh̜?/ JXh4 JslackXhL=g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsun@}A1AH*x|=2@H*@A=А=-8@gDi>?6y@9?D?'??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhw> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh"? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh-8@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuV@}A/2AH*x|=2@H*@A=А= o8@gDi>?Xy@9?D?'??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhw> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh5^? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh/2A; J arrival timeXhm/ JXh4 JslackXh o8@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsur=@}A@2Am+A=2@m+@A=А=A@gDi>Mb?Il@9?D?'?%?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xhn@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@2A; J arrival timeXh#/ JXh4 JslackXhA@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsur=@}A@2Am+A=2@m+@A=А=A@gDi>Mb?Il@9?D?'?%?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xhn@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@2A; J arrival timeXh#/ JXh4 JslackXhA@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuV@}AH2A+WM=2@+@A=А=D@gDi>K?vn@9?D?'?&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh"> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh~@X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhH2A; J arrival timeXhC/ JXh4 JslackXhD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuV@}AH2A1,Y=2@1,@A=А=D@gDi>K?vn@9?D?'?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh"> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh\@X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhH2A; J arrival timeXhC/ JXh4 JslackXhD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuV@}AH2A1,Y=2@1,@A=А=D@gDi>K?vn@9?D?'?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh"> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh\@X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhH2A; J arrival timeXhC/ JXh4 JslackXhD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}AL2A1,Y=2@1,@A=А=fD@gDi>K??5n@9?D?'?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh\@X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhL2A; J arrival timeXh33/ JXh4 JslackXhfD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}AL2A1,Y=2@1,@A=А=fD@gDi>K??5n@9?D?'?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh\@X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhL2A; J arrival timeXh33/ JXh4 JslackXhfD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu'1@}AD2A+WM=2@+@A=А=E@gDi>?Um@9?D?'?&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh>@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhw> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhn> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh~@X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhgDi>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhD2A; J arrival timeXh/ JXh4 JslackXhE@ ( !gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!)y@1y @9Ay@Iy @ei?hq} =  >: rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][51]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuxh>}셿FE=shq?F?=w&D==Ġ>?µ>M"?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[18][51] Jnet (fo=1, routed)Xh=] +'SFP_GEN[18].rx_data_ngccm_reg[18][51]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33S?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh/}?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][51]/C JFDCEXhzr> Jclock pessimismXhw&t )%SFP_GEN[18].rx_data_ngccm_reg[18][51]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh셿; J arrival timeXhH?/ JXh4 JslackXh=4g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu 0>}0񒿭#=shq??{0=u_ ף=j=Ġ>?µ> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)Xh㥛= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__17/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__17/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33S?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhu_ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh0; J arrival timeXhR?/ JXh4 JslackXh{0=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>}†DX=53s??0=&=`P=Ġ>?µ>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__17/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__17/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrT= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh†; J arrival timeXhV?/ JXh4 JslackXh0=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][18]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu)>}=Q??;1=9H==Ġ>J "?µ>D?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[18][18] Jnet (fo=1, routed)Xh=] +'SFP_GEN[18].rx_data_ngccm_reg[18][18]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh|?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][18]/C JFDCEXhzr> Jclock pessimismXhs )%SFP_GEN[18].rx_data_ngccm_reg[18][18]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhi?/ JXh4 JslackXh;1=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C*&SFP_GEN[18].rx_data_ngccm_reg[18][5]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu >}aÇ_=ts??1=?&9H==Ġ>/?µ>T%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[18][5] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[18].rx_data_ngccm_reg[18][5]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?U?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT)\ *&SFP_GEN[18].rx_data_ngccm_reg[18][5]/C JFDCEXhzr> Jclock pessimismXh?&s ($SFP_GEN[18].rx_data_ngccm_reg[18][5]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhaÇ; J arrival timeXhO?/ JXh4 JslackXh1=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu/>}*•DX=zt?•?#9=&=`P=Ġ>U?µ>ef&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__17/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__17/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhEV?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh*; J arrival timeXh?/ JXh4 JslackXh#9=6mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsui;=}أ33ף;q?33?D=Mo=Q8=Ġ>o?µ>G!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh+= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__18/I0 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__18/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru< sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__18_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK Jnet (fo=674, routed)XhtS?X4Y8 (CLOCK_ROOT) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh(|?X4Y8 (CLOCK_ROOT) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhM kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhأ; J arrival timeXhȆ?/ JXh4 JslackXhD=<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuG=}ף;O??#H=cffo=j<=Ġ>2,?µ>MbP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][7]_0[3] Jnet (fo=9, routed)XhC = sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][4]_i_1__0/I2 JXhzr rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][4]_i_1__0/OProp_A6LUT_SLICEL_I2_O JLUT6Xhzru<m *&g_gbt_bank[1].gbtbank/i_gbt_bank_n_309 Jnet (fo=1, routed)XhD<n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhj|?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhˡ?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C JFDCEXhzr> Jclock pessimismXhcff :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhZd?/ JXh4 JslackXh#H= <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuT>}#Q,=V??K=SB=/]=Ġ>+?µ>MbP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][7]_0[0] Jnet (fo=10, routed)Xhw= sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][3]_i_1__0/I1 JXhzr rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][3]_i_1__0/OProp_B6LUT_SLICEL_I1_O JLUT6XhzrQ8=m *&g_gbt_bank[1].gbtbank/i_gbt_bank_n_310 Jnet (fo=1, routed)Xhu<n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhˡ?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhSB :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh#; J arrival timeXh?/ JXh4 JslackXhK= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuR%>}~?Sc=!r?~??N=jf& ף==Ġ>?µ>B`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xh+= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__17/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__17/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhzT?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXhjf& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh{?/ JXh4 JslackXhN=ng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu@}Av,AB`(\G1@B`@A=А=i?Mb>$?}?@5^:?u?(?S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhMb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhv,A; J arrival timeXhE / JXh4 JslackXhi? mg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu@}A,AB`(\G1@B`@A=А= ?Mb>$?&@5^:?u?(?S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhMb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh / JXh4 JslackXh ? mg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuS@}Aj,A>bG1@@A=А=@]b>$?ʍ@5^:?u?(?[?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh= ?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh]b>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhj,A; J arrival timeXh / JXh4 JslackXh@ mg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuS@}Aj,A>bG1@@A=А=@]b>$?ʍ@5^:?u?(?[?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh= ?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh]b>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhj,A; J arrival timeXh / JXh4 JslackXh@ mg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu13@}Av,A7`G1@@A=А=[-@MXb>$?@5^:?u?(?Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)XhK?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhMXb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhv,A; J arrival timeXh / JXh4 JslackXh[-@ ng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu@}A5,A(koG1@(@A=А=@b>$?@5^:?u?(?a?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+v? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)XhB`?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh5,A; J arrival timeXhu / JXh4 JslackXh@ mg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuLb@}A:,A(koG1@(@A=А=@b>$?ي@5^:?u?(?a?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhu? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)XhB`?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh:,A; J arrival timeXh / JXh4 JslackXh@ `!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu¹@}A/1AP'=G1@P'@A=А=@$i>?…@5^:?u?(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhVn? okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17/OProp_G6LUT_SLICEM_I2_O JLUT4Xhzrl{> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17_n_0 Jnet (fo=1, routed)XhT%> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17_n_0 Jnet (fo=2, routed)Xh? kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh{@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh$i>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh/1A; J arrival timeXh33 / JXh4 JslackXh@ `!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu¹@}A/1AP'=G1@P'@A=А=@$i>?…@5^:?u?(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhA`%@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhVn? okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17/OProp_G6LUT_SLICEM_I2_O JLUT4Xhzrl{> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17_n_0 Jnet (fo=1, routed)XhT%> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17_n_0 Jnet (fo=2, routed)Xh? kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh{@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh$i>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh/1A; J arrival timeXh33 / JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]/D""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuʥ@}AM.A>bG1@@A=А=Z<@]b>?y@5^:?u?(?[?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[8]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[8] J GTHE3_CHANNELXhzr? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[10] Jnet (fo=6, routed)Xhy@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh= ?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]/C JFDCEXhzr> Jclock pessimismXh]b>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhM.A; J arrival timeXhn/ JXh4 JslackXhZ<@( !gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!)y@1y @9Ay@Iy @efJ@hq} s9= > rise - rise rise - rise  /sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu(>}\h=g?h?s9=y%=`=>T?">S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_CFF_SLICEM_C_Q JFDCEXhzfD= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh = jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[39]_i_2__18/I1 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[39]_i_2__18/OProp_C6LUT_SLICEM_I1_O JLUT5Xhzru< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg00[39] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh_p?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzr> Jclock pessimismXhy c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh\; J arrival timeXh?/ JXh4 JslackXhs9=?+'SFP_GEN[19].rx_data_ngccm_reg[19][74]/C0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@>}Ņ=A`e??`==1=>S?">$&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)x +'SFP_GEN[19].rx_data_ngccm_reg[19][74]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[66] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[74]_i_1/I1 JXhzr 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[74]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3XhzrGa=u 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[74]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)Xh+G?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][74]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhFs?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXhy .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhŅ; J arrival timeXh?/ JXh4 JslackXh`=?+'SFP_GEN[19].rx_data_ngccm_reg[19][73]/C0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuaB>}Ņ=A`e??M'==E=>S?">$&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)y +'SFP_GEN[19].rx_data_ngccm_reg[19][73]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD=w 40SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[65] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[72]_i_1/I0 JXhzr 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[72]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrY=u 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[72]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)Xh+G?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][73]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhFs?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXhx .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhŅ; J arrival timeXh ?/ JXh4 JslackXhM'=sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Csog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu~j<>}4c1\=$f??M'=ʡ=> =>?">A`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] Jnet (fo=29, routed)XhE= xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__19/I2 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__19/OProp_C6LUT_SLICEM_I2_O JLUT5Xhzr< _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/cnter[2] Jnet (fo=1, routed)Xho< sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzr> Jclock pessimismXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh4c; J arrival timeXh?/ JXh4 JslackXhM'=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuC>}慿r=ˡe??+=`=E=>?">ff&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__18/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__18/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhlG?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhs?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh慿; J arrival timeXhC?/ JXh4 JslackXh+=sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Csog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuv>>}4c1\=$f??h/= ף==>?">A`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] Jnet (fo=29, routed)XhQ= xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter[1]_i_1__19/I1 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter[1]_i_1__19/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr< _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/cnter[1] Jnet (fo=1, routed)Xho< sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzr> Jclock pessimismXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh4c; J arrival timeXhH?/ JXh4 JslackXhh/=wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/Cwsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu>}みX=g??J5=#o=E=>T?">ff&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[0] Jnet (fo=6, routed)Xh= |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__19/I1 JXhzr {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__19/OProp_C6LUT_SLICEM_I1_O JLUT6Xhzru< }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__19_n_0 Jnet (fo=1, routed)Xho< wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xhs?X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh# uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhみ; J arrival timeXhP?/ JXh4 JslackXhJ5=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C+'SFP_GEN[19].rx_data_ngccm_reg[19][78]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsux.>}tA7=lg??%@=qD="=>B`?">7!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[19][78] Jnet (fo=1, routed)Xh"=] +'SFP_GEN[19].rx_data_ngccm_reg[19][78]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)Xho?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][78]/C JFDCEXhzr> Jclock pessimismXhqt )%SFP_GEN[19].rx_data_ngccm_reg[19][78]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXht; J arrival timeXhx?/ JXh4 JslackXh%@=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuX->}1j =+g?j?@= ף=E=>?">%!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__18/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__18/OProp_B6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh1; J arrival timeXhL7?/ JXh4 JslackXh@=?+'SFP_GEN[19].rx_data_ngccm_reg[19][53]/C0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu+$>}􀿍{ Mg=e?{?YF=U"ʡ==>o?">Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)y +'SFP_GEN[19].rx_data_ngccm_reg[19][53]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[45] Jnet (fo=1, routed)Xh+=_ 1-SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[52]_i_1/I0 JXhzr 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[52]_i_1/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzr<u 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)XhyF?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][53]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXhU"x .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh􀿐; J arrival timeXh+?/ JXh4 JslackXhYF=D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu}?@}A*Ad;>@d;@A=А=fJ@a>rh>@v?_?ף?23?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh*A; J arrival timeXh֣/ JXh4 JslackXhfJ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu&@}A*Ad;>@d;@A=А=J@a>rh>U@v?_?ף?23?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhC? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh*A; J arrival timeXhD/ JXh4 JslackXhJ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuT@}A+A(>@@A=А=Y@)`>rh>@v?_?ף??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh?5? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXh)`>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXhG/ JXh4 JslackXhY@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuT@}A+A(>@@A=А=Y@)`>rh>@v?_?ף??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh?5? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXh)`>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXhG/ JXh4 JslackXhY@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuʉ@}A`!+A(>@@A=А=J'Z@)`>rh>,@v?_?ף??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhҭ? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh)`>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh`!+A; J arrival timeXh// JXh4 JslackXhJ'Z@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuʉ@}A`!+A(>@@A=А=J'Z@)`>rh>,@v?_?ף??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhҭ? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh)`>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh`!+A; J arrival timeXh// JXh4 JslackXhJ'Z@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A*APV>@P@A=А="a@a>rh>}@v?_?ף? ף?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhR? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh*A; J arrival timeXhsh/ JXh4 JslackXh"a@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A*APV>@P@A=А="a@a>rh>}@v?_?ף? ף?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhR? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Setup_FFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh*A; J arrival timeXhsh/ JXh4 JslackXh"a@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A*APV>@P@A=А="a@a>rh>}@v?_?ף? ף?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhR? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh*A; J arrival timeXhsh/ JXh4 JslackXh"a@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A +APV>@P@A=А=oa@a>rh>O}@v?_?ף? ף?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh$.@ okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/I1 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhV? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhMb @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh +A; J arrival timeXhO/ JXh4 JslackXhoa@( !gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!)y@1y @9Ay@Iy @eQhd@hq} $= >  rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[20].rx_data_ngccm_reg[20][39]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuth>}>~D@<=0d?D?$=:!D==$>?>I "?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[20][39] Jnet (fo=1, routed)Xh=] +'SFP_GEN[20].rx_data_ngccm_reg[20][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][39]/C JFDCEXhzr> Jclock pessimismXh:!t )%SFP_GEN[20].rx_data_ngccm_reg[20][39]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh>~; J arrival timeXh?/ JXh4 JslackXh$=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[20].rx_data_ngccm_reg[20][69]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}Zh_=0d?h?W-=!D== =$>?>$?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[20][69] Jnet (fo=1, routed)Xh= =] +'SFP_GEN[20].rx_data_ngccm_reg[20][69]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xh_p?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][69]/C JFDCEXhzr> Jclock pessimismXh!s )%SFP_GEN[20].rx_data_ngccm_reg[20][69]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhZ; J arrival timeXh?/ JXh4 JslackXhW-=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C*&SFP_GEN[20].rx_data_ngccm_reg[20][6]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu+>}Wj=yf?j?/=D=F=$>ˡ?>!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[20][6] Jnet (fo=1, routed)XhF=\ *&SFP_GEN[20].rx_data_ngccm_reg[20][6]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT)\ *&SFP_GEN[20].rx_data_ngccm_reg[20][6]/C JFDCEXhzr> Jclock pessimismXhr ($SFP_GEN[20].rx_data_ngccm_reg[20][6]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhW; J arrival timeXhԈ?/ JXh4 JslackXh/=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C+'SFP_GEN[20].rx_data_ngccm_reg[20][61]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}RhX=A`e?h?J5=!9H==$>?>$?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[20][61] Jnet (fo=1, routed)Xh=] +'SFP_GEN[20].rx_data_ngccm_reg[20][61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+G?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xh_p?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][61]/C JFDCEXhzr> Jclock pessimismXh!s )%SFP_GEN[20].rx_data_ngccm_reg[20][61]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhR; J arrival timeXhE?/ JXh4 JslackXhJ5=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuϡE>}cEVȼ=d?V?77==E=$>S?>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xhw= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__19/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__19/OProp_D5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhgfF?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhcE; J arrival timeXh ?/ JXh4 JslackXh77=p0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/CHDSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu\I>}[Nb='1h?Nb?J>=Ջ9H=P>$>y?>^)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)~ 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/Q[14] Jnet (fo=2, routed)XhP>z HDSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+v?X4Y9 (CLOCK_ROOT)z HDSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C JFDREXhzr> Jclock pessimismXhՋ FBSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh[; J arrival timeXhO?/ JXh4 JslackXhJ>=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*&SFP_GEN[20].rx_data_ngccm_reg[20][4]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu/>}Wj=yf?j?k@=D=l=$>ˡ?>!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[20][4] Jnet (fo=1, routed)Xhl=\ *&SFP_GEN[20].rx_data_ngccm_reg[20][4]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT)\ *&SFP_GEN[20].rx_data_ngccm_reg[20][4]/C JFDCEXhzr> Jclock pessimismXhr ($SFP_GEN[20].rx_data_ngccm_reg[20][4]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhW; J arrival timeXhX?/ JXh4 JslackXhk@=8mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsui;=}rC)ף;Sc?C?D=Go=Q8=$>I ?>|?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh+= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__20/I0 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__20/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru< sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__20_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)XhE?X4Y9 (CLOCK_ROOT) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)XhIl?X4Y9 (CLOCK_ROOT) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhG kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhr; J arrival timeXhe;?/ JXh4 JslackXhD=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuY%>}~je=J b?j?YL=!ʡ==$>?>!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhO= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__19/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__19/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh C?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh~; J arrival timeXh…?/ JXh4 JslackXhYL=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuz>}e~󍿭~=yf?? T=--=`P=$>ˡ?>/$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__19/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__19/OProp_H6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhq?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh-- g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhe~; J arrival timeXh?/ JXh4 JslackXh T=b!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A4*A daNb(@ @A=А=Qhd@R>&?t3@?ˡ?{?A?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 Jnet (fo=1, routed)Xhʡ= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr +> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 Jnet (fo=2, routed)XhP> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhK?X4Y9 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh4*A; J arrival timeXhA5/ JXh4 JslackXhQhd@ b!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A4*A daNb(@ @A=А=Qhd@R>&?t3@?ˡ?{?A?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 Jnet (fo=1, routed)Xhʡ= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr +> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 Jnet (fo=2, routed)XhP> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhK?X4Y9 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh4*A; J arrival timeXhA5/ JXh4 JslackXhQhd@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsup@}A<*A}? ]_Nb(@}? @A=А=lr@R>Ԩ?^9@?ˡ?{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzf> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_A6LUT_SLICEL_I0_O JLUT6XhzrE= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh.? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh<*A; J arrival timeXhC/ JXh4 JslackXhlr@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsup@}A<*A}? ]_Nb(@}? @A=А=lr@R>Ԩ?^9@?ˡ?{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzf> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_A6LUT_SLICEL_I0_O JLUT6XhzrE= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh.? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh<*A; J arrival timeXhC/ JXh4 JslackXhlr@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A@*A}? ]_Nb(@}? @A=А=r@R>Ԩ?x9@?ˡ?{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzf> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_A6LUT_SLICEL_I0_O JLUT6XhzrE= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh@*A; J arrival timeXh"/ JXh4 JslackXhr@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A@*A}? ]_Nb(@}? @A=А=r@R>Ԩ?x9@?ˡ?{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzf> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_A6LUT_SLICEL_I0_O JLUT6XhzrE= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh@*A; J arrival timeXh"/ JXh4 JslackXhr@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A@*A}? ]_Nb(@}? @A=А=r@R>Ԩ?x9@?ˡ?{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzf> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_A6LUT_SLICEL_I0_O JLUT6XhzrE= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh@*A; J arrival timeXh"/ JXh4 JslackXhr@ ~g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu|@}A0*AV  hbNb(@V @A=А=X7t@qR>!?2@?ˡ?{? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh|> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh+?X4Y9 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhqR>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0*A; J arrival timeXhE/ JXh4 JslackXhX7t@ ~g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu|@}A0*AV  hbNb(@V @A=А=X7t@qR>!?2@?ˡ?{? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh|> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh+?X4Y9 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhqR>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0*A; J arrival timeXhE/ JXh4 JslackXhX7t@ }g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A4*AV  hbNb(@V @A=А=?t@qR>!?\2@?ˡ?{? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhp> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh+?X4Y9 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhqR>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh4*A; J arrival timeXh$/ JXh4 JslackXh?t@ ( !gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!)y@1y @9Ay@Iy @e_q@hq}  =  >" rise - rise rise - rise  9g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuQ8>}F휿d=A?? == =ʡ>sh?ȶ>Y94?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__20/OProp_A6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhMb?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh·?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhF; J arrival timeXhK?/ JXh4 JslackXh =<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CGCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu)>}J둿=Nbp??ǽ$=^o=`=ʡ>G?ȶ>?5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt_reg[9][7]_0[0] Jnet (fo=10, routed)Xh = ~zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i[9]_i_1__0/I4 JXhzr }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i[9]_i_1__0/OProp_D6LUT_SLICEL_I4_O JLUT6Xhzru<m *&g_gbt_bank[1].gbtbank/i_gbt_bank_n_154 Jnet (fo=1, routed)Xho<y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh-R?X4Y9 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C JFDCEXhzr> Jclock pessimismXh^ EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhJ; J arrival timeXhp?/ JXh4 JslackXhǽ$= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[37]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuxh>}U휿+=ʁ??C4=.D==ʡ>z?ȶ>Y94?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[37]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[37] Jnet (fo=1, routed)Xh= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhB`e?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh·?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr> Jclock pessimismXh. c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhU; J arrival timeXh?/ JXh4 JslackXhC4=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsup=>}F휿d=A??5==5^=ʡ>sh?ȶ>Y94?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[0] Jnet (fo=2, routed)Xh㥛= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/OProp_B6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhMb?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh·?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXh5=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu3^:>}O=&?O?K8=r=X9=ʡ>43?ȶ>4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__20/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXhK8=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsut>}iW/o,=Ā?/?Dy;=8=L=ʡ>n?ȶ>k4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__20/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__20/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhSc?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhb?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh8 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhiW; J arrival timeXh33?/ JXh4 JslackXhDy;=:mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[1]/Cmig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu>}OqD=rh?O?@=.o=-=ʡ>F?ȶ>4?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/timer[1] Jnet (fo=6, routed)Xhrh= rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__21/I5 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__21/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzru< sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__21_n_0 Jnet (fo=1, routed)Xho< mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhd?X4Y9 (CLOCK_ROOT) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh'1?X4Y9 (CLOCK_ROOT) mig_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXh. kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhj?/ JXh4 JslackXh@=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[21].rx_data_ngccm_reg[21][69]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}􌿍휿w=%??C=8D=v=ʡ>?ȶ>Y94?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[21][69] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[21].rx_data_ngccm_reg[21][69]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh c?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh·?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][69]/C JFDCEXhzr> Jclock pessimismXh8t )%SFP_GEN[21].rx_data_ngccm_reg[21][69]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh􌿐; J arrival timeXho?/ JXh4 JslackXhC=A+'SFP_GEN[21].rx_data_ngccm_reg[21][73]/C0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsun>}̜!Q =a?̜? D='7=9H=ʡ>!?ȶ>3?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)x +'SFP_GEN[21].rx_data_ngccm_reg[21][73]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[83]_0[65] Jnet (fo=1, routed)Xh+=_ 1-SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[72]_i_1/I0 JXhzr 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[72]_i_1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[72]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xhc?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][73]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXh'7x .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh43?/ JXh4 JslackXh D=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuR%>} 휿6+j= ??H=+ʡ==ʡ>&?ȶ>Y94?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)XhL7= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__20/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ b?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh·?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh+ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh.ݔ?/ JXh4 JslackXhH=I$fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[104]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=4)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu@}Aʨ1A!M:@!@A=А=_q@Pn>?#Q@t8? ?&1(?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[104]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxencdata_s[9]_53[15] Jnet (fo=9, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__20/I3 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__20/OProp_F6LUT_SLICEL_I3_O JLUT6Xhzr֣p> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__20_n_0 Jnet (fo=1, routed)Xhv> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__20/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)> kgg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/s1_from_syndromes[0] Jnet (fo=33, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__20/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__20/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__20_n_0 Jnet (fo=1, routed)XhP= plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__41/I4 JXhzf okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__41/OProp_G6LUT_SLICEL_I4_O JLUT6Xhzr+> qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__41_n_0 Jnet (fo=1, routed)Xh~> xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__41/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__41/OProp_D6LUT_SLICEL_I3_O JLUT6XhzrZd> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)Xh*\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhm@X4Y9 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[104]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh'1@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhPn>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regSetup_DFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXhʨ1A; J arrival timeXh/ JXh4 JslackXh_q@!d!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuƋ@}A/A 솽3@ @A=А=~r@n>O?`(@t8??&1(??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr)> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20_n_0 Jnet (fo=1, routed)Xhv>> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrMb> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20_n_0 Jnet (fo=2, routed)XhM> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh)\@X4Y9 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh~r@ d!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu!@}A/A: '3@: @A=А=t@=n>O?R&@t8??&1(?5^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr)> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20_n_0 Jnet (fo=1, routed)Xhv>> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrMb> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20_n_0 Jnet (fo=2, routed)Xh`> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xhd;@X4Y9 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh=n>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXht@ rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu@}AV 0A"3@"@A=А={@`n>K?)@t8??&1(?پ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> > xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/OProp_F6LUT_SLICEL_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhA`%? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xhx @X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh`n>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhV 0A; J arrival timeXh/ JXh4 JslackXh{@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu~@}A0A"3@"@A=А=_@`n>K?X)@t8??&1(?پ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> > xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/OProp_F6LUT_SLICEL_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ$? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xhx @X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh`n>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh_@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuO@}A/A: '3@: @A=А=ǃ@=n>K?&@t8??&1(?5^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> > xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/OProp_F6LUT_SLICEL_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhH? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xhd;@X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh=n>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh/A; J arrival timeXhK/ JXh4 JslackXhǃ@ rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu6y@}A/A&!y3@&!@A=А=@n>K?U@t8??&1(?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> > xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/OProp_F6LUT_SLICEL_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhV> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuGy@}A./A&!y3@&!@A=А=@n>K?ˡ@t8??&1(?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> > xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/OProp_F6LUT_SLICEL_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh./A; J arrival timeXh/ JXh4 JslackXh@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuGy@}A./A&!y3@&!@A=А=@n>K?ˡ@t8??&1(?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> > xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/OProp_F6LUT_SLICEL_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh./A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsux@}A/A%!ր3@%!@A=А=*ň@%n>+?/@t8??&1(? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/OProp_H6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__21/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__21/OProp_G6LUT_SLICEL_I5_O JLUT6XhzrE= `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)XhP@X4Y9 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh%n>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXh5^/ JXh4 JslackXh*ň@ ( !gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!)y@1y @9Ay@Iy @e(@hq} = vv?& rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[24].rx_data_ngccm_reg[24][46]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu +>}刺g=??=D9H==l>$?J >G?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[24][46] Jnet (fo=1, routed)Xh=] +'SFP_GEN[24].rx_data_ngccm_reg[24][46]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhz?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][46]/C JFDCEXhzr> Jclock pessimismXhDs )%SFP_GEN[24].rx_data_ngccm_reg[24][46]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}Ԩoi5=H?Ԩ?f:;=YCB=T=l>Z$?J >_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__23/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__23/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhbx?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhYCB g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhh?/ JXh4 JslackXhf:;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}8h,=㥋??|C=[_D=T=l>T%?J >CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__23/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh[_D g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh8; J arrival timeXhV?/ JXh4 JslackXh|C=Xmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsui;=}Mz֣;t?z?D=Jo=Q8=l>?J >%!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= XTg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh+= rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__24/I0 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__24/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru< sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__24_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK Jnet (fo=674, routed)XhKW?X1Y2 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh%?X1Y2 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhJ kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhM; J arrival timeXhr?/ JXh4 JslackXhD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuw>}-= Q4=p=?= ?J6H=89%= =l>o#?J >$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__23/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__23/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh89 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh-; J arrival timeXhO?/ JXh4 JslackXhJ6H=]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuS=}-jv֣;kt?j?L=Mo=@=l>S?J >7!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/ready_from_bitSlipCtrller_0 Jnet (fo=2, routed)Xh)\= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23/I2 JXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh> W?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhM [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh-; J arrival timeXhu?/ JXh4 JslackXhL=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuV>}rĖ刺=Zd?? UM=sBv=j<=l>B`%?J >G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__23/OProp_F6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhsB g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhrĖ; J arrival timeXh/?/ JXh4 JslackXh UM=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}8h,=㥋??^%X=[_D=`P=l>T%?J >CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__23/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrT= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh[_D g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh8; J arrival timeXh?/ JXh4 JslackXh^%X=0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[26]/CHDSFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuT>}#𧦿$=6^??X=RH99H==l>S#?J >C`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)~ 0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[26]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/Q[10] Jnet (fo=2, routed)Xh=z HDSFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[24].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh? w?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[24].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh43?X1Y2 (CLOCK_ROOT)z HDSFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C JFDREXhzr> Jclock pessimismXhRH9 FBSFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh#; J arrival timeXhO?/ JXh4 JslackXhX=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuxh>}rĖ刺=Zd??Y=sB=D=l>B`%?J >G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__23/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__23/OProp_G6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXhsB g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhrĖ; J arrival timeXhi?/ JXh4 JslackXhY=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}AҎ+AS}%J *@S@A=А=(@F>?@6?M?A`%? ף?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh(? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrL= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh5^:? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh+?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhҎ+A; J arrival timeXhX/ JXh4 JslackXh(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][54]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsur@}Aғ0A&G<1@&@A=А=m?@L>η>@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)XhQ?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][54]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][54]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhv )%SFP_GEN[24].rx_data_ngccm_reg[24][54]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhғ0A; J arrival timeXhR/ JXh4 JslackXhm?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][73]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsur@}Aғ0A&G<1@&@A=А=m?@L>η>@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)XhQ?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][73]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][73]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhv )%SFP_GEN[24].rx_data_ngccm_reg[24][73]Setup_BFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhғ0A; J arrival timeXhR/ JXh4 JslackXhm?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][76]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsur@}Aғ0A&G<1@&@A=А=m?@L>η>@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)XhQ?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][76]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][76]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhv )%SFP_GEN[24].rx_data_ngccm_reg[24][76]Setup_CFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhғ0A; J arrival timeXhR/ JXh4 JslackXhm?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][51]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuZ@}A0A&G<1@&@A=А=?@L>η>/ݜ@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][51]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][51]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhu )%SFP_GEN[24].rx_data_ngccm_reg[24][51]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][72]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuZ@}A0A&G<1@&@A=А=?@L>η>/ݜ@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][72]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][72]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhu )%SFP_GEN[24].rx_data_ngccm_reg[24][72]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][74]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuZ@}A0A&G<1@&@A=А=?@L>η>/ݜ@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][74]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][74]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhu )%SFP_GEN[24].rx_data_ngccm_reg[24][74]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][77]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuZ@}A0A&G<1@&@A=А=?@L>η>/ݜ@6? -?A`%?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][77]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xhy@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][77]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhu )%SFP_GEN[24].rx_data_ngccm_reg[24][77]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh?@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][60]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuΧ@}A>{0A&{<1@&@A=А=\S@@L>η>Q@6? -?A`%??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)Xhµ?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][60]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)XhR@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][60]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhv )%SFP_GEN[24].rx_data_ngccm_reg[24][60]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh>{0A; J arrival timeXhgf/ JXh4 JslackXh\S@@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[24].rx_data_ngccm_reg[24][44]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuF@}A0A&{<1@&@A=А=@@L>η>X9@6? -?A`%??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/OProp_E6LUT_SLICEL_I0_O JLUT6XhzrA`>Y rx_data_ngccm[24] Jnet (fo=76, routed)XhA`?^ ,(SFP_GEN[24].rx_data_ngccm_reg[24][44]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)XhR@X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][44]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXhu )%SFP_GEN[24].rx_data_ngccm_reg[24][44]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXhZ/ JXh4 JslackXh@@L( !gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!)y@1y @9Ay@Iy @eR@hq} X = uv?  * rise - rise rise - rise  "fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[60]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu'>}%̜Χ؂=(?Χ?X =m9H==c>.?>aP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[60]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[60] Jnet (fo=1, routed)Xh= fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]/C JFDCEXhzr> Jclock pessimismXhm d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh%̜; J arrival timeXh&?/ JXh4 JslackXhX ="fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[24]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuxh>}EPW0G=H?P?H=.39H=v=c>1,?>ObP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[24]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[24] Jnet (fo=1, routed)Xhv= fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhbx?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXh.3 d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhE; J arrival timeXhV?/ JXh4 JslackXhH=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsut>}b֗rJ,=C?r?y;=:>=L=c>,?>-R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__33/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__33/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh:> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhb֗; J arrival timeXh.?/ JXh4 JslackXhy;=mg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu>}b֗rJ,=C?r?C=:>=T=c>,?>-R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__33/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__33/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh:> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhb֗; J arrival timeXh?/ JXh4 JslackXhC=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsup=>}뜿刺=??;H=,x=5^=c>O-?>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__33/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__33/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh,x g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh뜿; J arrival timeXh33?/ JXh4 JslackXh;H=0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/CB>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu_94>}›y馿)=㥋?y?JM=D=o>c>h-?>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)~ 0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= EASFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] Jnet (fo=1, routed)Xho>t B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X1Y4 (CLOCK_ROOT)t B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C JFDREXhzr> Jclock pessimismXh @}%KIs=C?K?JM=9H='1>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[36]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[36] Jnet (fo=1, routed)Xh'1> fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh%; J arrival timeXh]?/ JXh4 JslackXhJM=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsut>}M=I??>UM=>=L=c>.?>43S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGz?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhM; J arrival timeXhR?/ JXh4 JslackXh>UM=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[34].rx_data_ngccm_reg[34][49]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuX->}!vx=C??M=9D==c>,?>IL?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[34][49] Jnet (fo=1, routed)Xh=] +'SFP_GEN[34].rx_data_ngccm_reg[34][49]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)XhJ ?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][49]/C JFDCEXhzr> Jclock pessimismXh9t )%SFP_GEN[34].rx_data_ngccm_reg[34][49]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh!v; J arrival timeXha?/ JXh4 JslackXhM=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuw>}b֗rJ,=C?r?aO=:>=Q8=c>,?>-R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__33/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__33/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXh:> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhb֗; J arrival timeXhV?/ JXh4 JslackXhaO=!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu23@}AO/A$'>$&@$@A=А=R@]H>_?7a@'?J ?K?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 Jnet (fo=1, routed)XhS> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/OProp_G6LUT_SLICEL_I5_O JLUT6XhzrE= qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xh1 @X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhO/A; J arrival timeXhE/ JXh4 JslackXhR@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu23@}AO/A$'>$&@$@A=А=R@]H>_?7a@'?J ?K?j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 Jnet (fo=1, routed)XhS> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/OProp_G6LUT_SLICEL_I5_O JLUT6XhzrE= qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xh1 @X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhO/A; J arrival timeXhE/ JXh4 JslackXhR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuz@}A/A$2>$&@$@A=А=`@]H>ff?e@'?J ?K??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhQ? uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xhj @X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXhO/ JXh4 JslackXh`@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuNb@}A^/A$2>$&@$@A=А=`@]H>ff?he@'?J ?K??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh`P? uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xhj @X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh^/A; J arrival timeXht/ JXh4 JslackXh`@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuNb@}A^/A$2>$&@$@A=А=`@]H>ff?he@'?J ?K??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh`P? uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xhj @X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh^/A; J arrival timeXht/ JXh4 JslackXh`@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu@}A/Az$->$&@z$@A=А=[c@]H>!?C\@'?J ?K?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzfX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhO-? yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xh~j @X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh[c@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuM@}A/Az$->$&@z$@A=А=d@]H>ff?rha@'?J ?K?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh$@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_C6LUT_SLICEL_I2_O JLUT4XhzrX9= tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhA@? uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xh~j @X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh]H>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXhB`/ JXh4 JslackXhd@ %g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[34].rx_data_ngccm_reg[34][18]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu"ە@}A,-0AT%{e=.@T%@A=А=5f@,G>>@'?S?K??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5@ xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/I0 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[34] Jnet (fo=76, routed)Xh(?^ ,(SFP_GEN[34].rx_data_ngccm_reg[34][18]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][18]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXhv )%SFP_GEN[34].rx_data_ngccm_reg[34][18]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,-0A; J arrival timeXh}?/ JXh4 JslackXh5f@L%g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[34].rx_data_ngccm_reg[34][23]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu"ە@}A,-0AT%{e=.@T%@A=А=5f@,G>>@'?S?K??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5@ xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/I0 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[34] Jnet (fo=76, routed)Xh(?^ ,(SFP_GEN[34].rx_data_ngccm_reg[34][23]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][23]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXhv )%SFP_GEN[34].rx_data_ngccm_reg[34][23]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,-0A; J arrival timeXh}?/ JXh4 JslackXh5f@L%g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[34].rx_data_ngccm_reg[34][27]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu"ە@}A,-0AT%{e=.@T%@A=А=5f@,G>>@'?S?K??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5@ xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/I0 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[34] Jnet (fo=76, routed)Xh(?^ ,(SFP_GEN[34].rx_data_ngccm_reg[34][27]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][27]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXhv )%SFP_GEN[34].rx_data_ngccm_reg[34][27]Setup_GFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,-0A; J arrival timeXh}?/ JXh4 JslackXh5f@L( !gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!)y@1y @9Ay@Iy @eRl@hq} = wv?!!- rise - rise rise - rise  etpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuX9>}}=w??=v==A`>l?|>K7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF2_SLICEL_C_Q JFDCEXhzfD= rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh-= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[25]_i_1__26/I0 JXhzf jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[25]_i_1__26/OProp_D6LUT_SLICEL_I0_O JLUT5Xhzr< a]g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[25] Jnet (fo=1, routed)Xho< fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh}; J arrival timeXho?/ JXh4 JslackXh=etpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu;^:>}}=w??\=v==A`>l?|>K7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF2_SLICEL_C_Q JFDCEXhzfD= rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)XhX9= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[26]_i_1__26/I0 JXhzf jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[26]_i_1__26/OProp_C6LUT_SLICEL_I0_O JLUT5Xhzr< a]g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[26] Jnet (fo=1, routed)Xho< fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh}; J arrival timeXh43?/ JXh4 JslackXh\=kg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu+>}z=v?z?:,=,>ʡ=X9=A`>ˡ?|>M"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQX?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh,> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhOb?/ JXh4 JslackXh:,=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[35].rx_data_ngccm_reg[35][38]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsun>}˗l3= ?l?0=_6D=\=A`>ˡ%?|>(1H?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[35][38] Jnet (fo=1, routed)Xh\=] +'SFP_GEN[35].rx_data_ngccm_reg[35][38]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQx?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][38]/C JFDCEXhzr> Jclock pessimismXh_6t )%SFP_GEN[35].rx_data_ngccm_reg[35][38]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh˗; J arrival timeXhO?/ JXh4 JslackXh0=h+'SFP_GEN[35].rx_data_ngccm_reg[35][49]/C0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuv>>}+g)=v?+?!(8=<=j=A`>ˡ?|>ff&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)y +'SFP_GEN[35].rx_data_ngccm_reg[35][49]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] Jnet (fo=1, routed)Xh㥛=_ 1-SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[48]_i_1/I0 JXhzr 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[48]_i_1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)XhQX?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][49]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXh<x .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhВ?/ JXh4 JslackXh!(8=lg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu0>}R헿P8= ?P?<=W6%=1=A`>ˡ%?|>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O83[0] Jnet (fo=2, routed)XhO= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__34/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__34/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQx?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhW6 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhR헿; J arrival timeXhҝ?/ JXh4 JslackXh<=mnjg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cnjg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsui;=}Ђv֣;v??ћD=Go=Q8=A`>ˡ?|>\"?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh+= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__35/I0 JXhzr rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__35/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru< tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__35_n_0 Jnet (fo=1, routed)XhD< njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= TPg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK Jnet (fo=674, routed)XhQX?X1Y4 (CLOCK_ROOT) njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> TPg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh&?X1Y4 (CLOCK_ROOT) njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhG lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhЂ; J arrival timeXh?/ JXh4 JslackXhћD=etpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuG>}ÞcIŸ=w?c?G= o=$>A`>l?|>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] Jnet (fo=29, routed)XhF= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[35]_i_1__26/I2 JXhzr jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[35]_i_1__26/OProp_A6LUT_SLICEM_I2_O JLUT5Xhzru< a]g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[35] Jnet (fo=1, routed)XhD< fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzr> Jclock pessimismXh  d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhÞ; J arrival timeXh/ݔ?/ JXh4 JslackXhG=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu-2>}z=v?z?72I=,>X9= =A`>ˡ?|>M"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[1] Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__34/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__34/OProp_H5LUT_SLICEL_I2_O JLUT3Xhzrw= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQX?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh,> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhG?/ JXh4 JslackXh72I=g+'SFP_GEN[35].rx_data_ngccm_reg[35][65]/C0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]/D"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu)>}g\= &?)=w?= ?L}K=.[=T=A`>l?|>l'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)x +'SFP_GEN[35].rx_data_ngccm_reg[35][65]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[83]_0[57] Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[64]_i_1/I0 JXhzr 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[64]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<=u 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[64]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][65]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXh.x .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhg\; J arrival timeXhR?/ JXh4 JslackXhL}K=!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu<ߋ@}AOZ+An/Z'X)@n@A=А=Rl@c=G>X?n+@F3?n?M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhMb> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 Jnet (fo=1, routed)XhP= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 Jnet (fo=2, routed)Xhu> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xhk?X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhc=G>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhOZ+A; J arrival timeXhD/ JXh4 JslackXhRl@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu<ߋ@}AOZ+An/Z'X)@n@A=А=Rl@c=G>X?n+@F3?n?M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhMb> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 Jnet (fo=1, routed)XhP= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 Jnet (fo=2, routed)Xhu> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xhk?X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhc=G>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhOZ+A; J arrival timeXhD/ JXh4 JslackXhRl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsup@}Ar+A :X)@ @A=А=y@%G>?<'@F3?n?M"?k?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__35/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__35/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhz? uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhT?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh%G>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhr+A; J arrival timeXh/ JXh4 JslackXhy@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuO@}A~+A :X)@ @A=А=hz@%G>?'@F3?n?M"?k?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__35/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__35/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xht? uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhT?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh%G>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh~+A; J arrival timeXh/ JXh4 JslackXhhz@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuأ@}AR+A~V&X)@~@A=А=FT@:G>E?$@F3?n?M"?F?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/I5 JXhzr zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrMb> a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh/?X1Y4 (CLOCK_ROOT) vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh:G>@ Jclock uncertaintyXh tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhR+A; J arrival timeXhO/ JXh4 JslackXhFT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuD@}A]^+A~V&X)@~@A=А=n@:G>E?@F3?n?M"?F?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/I5 JXhzr zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrMb> a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhu> wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh/?X1Y4 (CLOCK_ROOT) vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh:G>@ Jclock uncertaintyXh tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh]^+A; J arrival timeXhM7/ JXh4 JslackXhn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuD@}A]^+A~V&X)@~@A=А=n@:G>E?@F3?n?M"?F?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/I5 JXhzr zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrMb> a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhu> wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh/?X1Y4 (CLOCK_ROOT) vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh:G>@ Jclock uncertaintyXh tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh]^+A; J arrival timeXhM7/ JXh4 JslackXhn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuQ@}A܂+Ao6X)@o@A=А=@*#G>p?!@F3?n?M"?0ݤ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh*#G>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh܂+A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuZ9@}A+A"k3X)@"@A=А=t(@ G>p?^!@F3?n?M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh$?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh G>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXhb/ JXh4 JslackXht(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuZ9@}A+Ao6X)@o@A=А=(@*#G>p?^!@F3?n?M"?0ݤ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh*#G>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh+A; J arrival timeXhb/ JXh4 JslackXh(@ ( !gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!)y@1y @9Ay@Iy @e8\@hq} \= vv?""0 rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[25].rx_data_ngccm_reg[25][68]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu">}HČ•H=z?•?\=#DD=S=>*\?->+?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[25][68] Jnet (fo=1, routed)XhS=] +'SFP_GEN[25].rx_data_ngccm_reg[25][68]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj\?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)XhM?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][68]/C JFDCEXhzr> Jclock pessimismXh#Dt )%SFP_GEN[25].rx_data_ngccm_reg[25][68]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhHČ; J arrival timeXhsh?/ JXh4 JslackXh\=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C+'SFP_GEN[25].rx_data_ngccm_reg[25][75]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu+>}&=$y??$='D9H==>?->0,?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[25][75] Jnet (fo=1, routed)Xh=] +'SFP_GEN[25].rx_data_ngccm_reg[25][75]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(\?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh\?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][75]/C JFDCEXhzr> Jclock pessimismXh'Ds )%SFP_GEN[25].rx_data_ngccm_reg[25][75]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh&; J arrival timeXhM?/ JXh4 JslackXh$=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[25].rx_data_ngccm_reg[25][49]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuK7>}E$ *=w?$?z1=V9H=>>V ?->I,?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[25][49] Jnet (fo=1, routed)Xh>] +'SFP_GEN[25].rx_data_ngccm_reg[25][49]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh!?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][49]/C JFDCEXhzr> Jclock pessimismXhVs )%SFP_GEN[25].rx_data_ngccm_reg[25][49]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhE; J arrival timeXhВ?/ JXh4 JslackXhz1=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuD>}Ҏ=bx??:9=1=5^=>O ?->)\/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__24/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__24/OProp_G6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^Z?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhҎ; J arrival timeXh?/ JXh4 JslackXh:9=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuǡE>}Ҏ=bx??1==1=j=>O ?->)\/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__24/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__24/OProp_H6LUT_SLICEL_I2_O JLUT3XhzrT= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^Z?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhҎ; J arrival timeXhj?/ JXh4 JslackXh1==wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Cwsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsui;=}o֣;+v??D=]Io=Q8=> ?->q=*?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] Jnet (fo=2, routed)Xh+= |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__25/I5 JXhzr {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__25/OProp_A6LUT_SLICEM_I5_O JLUT6Xhzru< }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__25_n_0 Jnet (fo=1, routed)XhD< wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)XhX?X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh]I uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXho; J arrival timeXhL7?/ JXh4 JslackXhD=eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu >}S𧖿DL=w??$E="9H==>V ?->O-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[35] Jnet (fo=1, routed)Xh= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh43?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]/C JFDCEXhzr> Jclock pessimismXh" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhS; J arrival timeXh|?/ JXh4 JslackXh$E=D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu5,>}@=x??B?F=h9H=F=>|?->K7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/Q[0] Jnet (fo=137, routed)XhF= RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh"[?X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh&?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_regHold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhB?F=0,SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[29]/CHDSFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu>}GȦ+=H?Ȧ?u +?->iM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR)} 0,SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[29]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/Q[13] Jnet (fo=2, routed)Xh=z HDSFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhbx?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[25].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS?X1Y2 (CLOCK_ROOT)z HDSFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C JFDREXhzr> Jclock pessimismXhm[4 FBSFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXhG; J arrival timeXhh?/ JXh4 JslackXhuC ?->C+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/ready_from_bitSlipCtrller_1 Jnet (fo=2, routed)Xh)\= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__24/I2 JXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__24/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__24_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh=O [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhЂ; J arrival timeXhL7?/ JXh4 JslackXhL=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][25]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu@}A/AW% =)\/@W%@A=А=8\@RF>>ʍ@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][25]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][25]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhv )%SFP_GEN[25].rx_data_ngccm_reg[25][25]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh8\@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][19]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu@}A/AW% =)\/@W%@A=А= \@RF>>-@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh@5?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][19]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][19]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhu )%SFP_GEN[25].rx_data_ngccm_reg[25][19]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh/A; J arrival timeXh-/ JXh4 JslackXh \@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][34]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu@}A/AW% =)\/@W%@A=А= \@RF>>-@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh@5?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][34]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][34]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhu )%SFP_GEN[25].rx_data_ngccm_reg[25][34]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh/A; J arrival timeXh-/ JXh4 JslackXh \@L!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsup@}AN+Az ǝB`%@z@A=А=^@pr?>?yF@*??5^?䥫?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhX@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 Jnet (fo=1, routed)Xhw= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr +> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 Jnet (fo=2, routed)Xh#۹> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh- @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhpr?>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhN+A; J arrival timeXh / JXh4 JslackXh^@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsup@}AN+Az ǝB`%@z@A=А=^@pr?>?yF@*??5^?䥫?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhX@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 Jnet (fo=1, routed)Xhw= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr +> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 Jnet (fo=2, routed)Xh#۹> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh- @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhpr?>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhN+A; J arrival timeXh / JXh4 JslackXh^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][32]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsush@}A2/A${<)\/@$@A=А=_e@RF>>@*??5^?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][32]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xhj @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][32]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhv )%SFP_GEN[25].rx_data_ngccm_reg[25][32]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh2/A; J arrival timeXh/ JXh4 JslackXh_e@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][28]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuO@}A|/A${<)\/@$@A=А=e@RF>>@*??5^?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh[d?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][28]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xhj @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][28]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhu )%SFP_GEN[25].rx_data_ngccm_reg[25][28]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh|/A; J arrival timeXh/ JXh4 JslackXhe@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][35]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuO@}A|/A${<)\/@$@A=А=e@RF>>@*??5^?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh[d?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][35]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xhj @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][35]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhu )%SFP_GEN[25].rx_data_ngccm_reg[25][35]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh|/A; J arrival timeXh/ JXh4 JslackXhe@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][26]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuK7@}AY0Ah%'=)\/@h%@A=А=f@RF>>a@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh ?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][26]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][26]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhv )%SFP_GEN[25].rx_data_ngccm_reg[25][26]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhY0A; J arrival timeXh`/ JXh4 JslackXhf@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[25].rx_data_ngccm_reg[25][37]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuK7@}AY0Ah%'=)\/@h%@A=А=f@RF>>a@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI$@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[25] Jnet (fo=76, routed)Xh ?^ ,(SFP_GEN[25].rx_data_ngccm_reg[25][37]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][37]/C JFDCEXhzr> Jclock pessimismXhRF>@ Jclock uncertaintyXhv )%SFP_GEN[25].rx_data_ngccm_reg[25][37]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhY0A; J arrival timeXh`/ JXh4 JslackXhf@L( !gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!)y@1y @9Ay@Iy @etW@hq} H < vv?##3 rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][35]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu(>}鲌$8=v?$?H <D==S>l?>z&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[26][35] Jnet (fo=1, routed)Xh=] +'SFP_GEN[26].rx_data_ngccm_reg[26][35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh!?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][35]/C JFDCEXhzr> Jclock pessimismXhs )%SFP_GEN[26].rx_data_ngccm_reg[26][35]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh鲌; J arrival timeXh?/ JXh4 JslackXhH <0*&SFP_GEN[26].rx_data_ngccm_reg[26][0]/C/+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu/>}pT㕿#=Ev?T?=+ ף=5^=S>z?>ff&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)w *&SFP_GEN[26].rx_data_ngccm_reg[26][0]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[0]_i_1/I1 JXhzr /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[0]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzr<t 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)XhvX?X1Y2 (CLOCK_ROOT)\ *&SFP_GEN[26].rx_data_ngccm_reg[26][0]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y2 (CLOCK_ROOT)a /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh+w -)SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhp; J arrival timeXh%?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][48]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu_94>}ioT㕿:>=u?T?=hD=o>S>$?>ff&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[26][48] Jnet (fo=1, routed)Xho>] +'SFP_GEN[26].rx_data_ngccm_reg[26][48]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhW?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xhn?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][48]/C JFDCEXhzr> Jclock pessimismXhhs )%SFP_GEN[26].rx_data_ngccm_reg[26][48]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhio; J arrival timeXhG?/ JXh4 JslackXh=eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu*\>}3E$;=? w?E?C.= 'D=j=S>?>+'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[23] Jnet (fo=1, routed)Xhj= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhXY?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhЂ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]/C JFDCEXhzr> Jclock pessimismXh ' c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh3; J arrival timeXhp?/ JXh4 JslackXhC.=<+'SFP_GEN[26].rx_data_ngccm_reg[26][57]/C0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu/>}@ffk#s=Fs?ff?E=?'=`P=S>Z?>l'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)x +'SFP_GEN[26].rx_data_ngccm_reg[26][57]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[49] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[56]_i_1/I0 JXhzr 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[56]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]=u 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[56]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][57]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXh?'x .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh@; J arrival timeXhi?/ JXh4 JslackXhE=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][20]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuX9>}QKƮ=Pw?K?@&=D='1>S>(1?>M7)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[26][20] Jnet (fo=1, routed)Xh'1>] +'SFP_GEN[26].rx_data_ngccm_reg[26][20]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$Y?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh ׃?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][20]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[26].rx_data_ngccm_reg[26][20]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhQ; J arrival timeXh?/ JXh4 JslackXh@&=<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CGCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu/>}s=s??$(=+ ף=5^=S>?>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt_reg[2][7]_0[0] Jnet (fo=10, routed)Xh= ~zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_1__1/I4 JXhzr }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_1__1/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzr<m *&g_gbt_bank[2].gbtbank/i_gbt_bank_n_147 Jnet (fo=1, routed)Xho<y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhEV?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)Xhأ?X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C JFDCEXhzr> Jclock pessimismXh+ EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh;ߏ?/ JXh4 JslackXh$(= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuT>}?EG=Ev?E?1="#'%={=S>z?>+'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__25/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__25/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhvX?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhЂ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh"#' g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh?; J arrival timeXh|?/ JXh4 JslackXh1=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C*&SFP_GEN[26].rx_data_ngccm_reg[26][6]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuUb>}Çr"=? w??9=B'D=v=S>?>̡%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[26][6] Jnet (fo=1, routed)Xhv=\ *&SFP_GEN[26].rx_data_ngccm_reg[26][6]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhXY?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)XhJ ?X1Y2 (CLOCK_ROOT)\ *&SFP_GEN[26].rx_data_ngccm_reg[26][6]/C JFDCEXhzr> Jclock pessimismXhB's ($SFP_GEN[26].rx_data_ngccm_reg[26][6]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhÇ; J arrival timeXhj?/ JXh4 JslackXh9=<+'SFP_GEN[26].rx_data_ngccm_reg[26][53]/C0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsut>}=І•J,=zt?•?y;=0=L=S>?>$&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)x +'SFP_GEN[26].rx_data_ngccm_reg[26][53]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[45] Jnet (fo=1, routed)XhC =_ 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[52]_i_1/I0 JXhzr 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[52]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][53]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXh0x .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh=І; J arrival timeXh ?/ JXh4 JslackXhy;=`!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu< @}AYf+Ac(@@A=А=tW@A>M?D@2?A?"?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25/OProp_D5LUT_SLICEM_I2_O JLUT4XhzrˡE> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25_n_0 Jnet (fo=1, routed)Xh@5^> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr`P= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhYf+A; J arrival timeXhn/ JXh4 JslackXhtW@ `!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu< @}AYf+Ac(@@A=А=tW@A>M?D@2?A?"?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25/OProp_D5LUT_SLICEM_I2_O JLUT4XhzrˡE> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25_n_0 Jnet (fo=1, routed)Xh@5^> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr`P= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhYf+A; J arrival timeXhn/ JXh4 JslackXhtW@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuO@}AR+A#"c(@#@A=А='a@W5A>?:@2?A?"?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZd? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhW5A>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhR+A; J arrival timeXhX/ JXh4 JslackXh'a@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuL7@}Aj!+A#"c(@#@A=А=b@W5A>?n:@2?A?"?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhW5A>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhj!+A; J arrival timeXh}?/ JXh4 JslackXhb@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuL7@}Aj!+A#"c(@#@A=А=b@W5A>?n:@2?A?"?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhW5A>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhj!+A; J arrival timeXh}?/ JXh4 JslackXhb@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu'1@}A=+A5^c(@5^@A=А=\d@\ A>?Mb8@2?A?"?43?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhn? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh\ A>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh=+A; J arrival timeXhX9/ JXh4 JslackXh\d@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu@}AE+A~hc(@~@A=А=g@A>?5@2?A?"?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhy? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh/?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhE+A; J arrival timeXh/ JXh4 JslackXhg@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu@}AI+A~hc(@~@A=А=g@A>?O5@2?A?"?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh$? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh/?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhI+A; J arrival timeXh!/ JXh4 JslackXhg@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuo@}A=+A]c(@]@A=А=Nn@A>?$.@2?A?"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh=+A; J arrival timeXh/ JXh4 JslackXhNn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu+@}AE+A c(@ @A=А=Ew@CA>+?)@2?A?"? ף?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhI @ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__26/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__26/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhw> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh}??X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhCA>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhE+A; J arrival timeXh[/ JXh4 JslackXhEw@ ( !gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!)y@1y @9Ay@Iy @eE@hq} = vv?$$5 rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuv>>}?:m=^?:?=ߗ=j=>?Z>Q8?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhߗ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh?; J arrival timeXh7?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[27].rx_data_ngccm_reg[27][76]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuT>}RauV=~?u?`!=):9H==>?Z>d8?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[27][76] Jnet (fo=1, routed)Xh=] +'SFP_GEN[27].rx_data_ngccm_reg[27][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[27].rx_data_ngccm_reg[27][76]/C JFDCEXhzr> Jclock pessimismXh):s )%SFP_GEN[27].rx_data_ngccm_reg[27][76]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhRa; J arrival timeXhp?/ JXh4 JslackXh`!=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[27].rx_data_ngccm_reg[27][67]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsun>}4ו$6=?$?)-=X;D=\=>n?Z>433?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[27][67] Jnet (fo=1, routed)Xh\=] +'SFP_GEN[27].rx_data_ngccm_reg[27][67]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9t?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)Xh!?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[27].rx_data_ngccm_reg[27][67]/C JFDCEXhzr> Jclock pessimismXhX;t )%SFP_GEN[27].rx_data_ngccm_reg[27][67]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh4ו; J arrival timeXhC?/ JXh4 JslackXh)-=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu!>}rCn=x?r?A3==<v= ף=>t?Z>7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)XhC= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__26/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__26/OProp_F6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?u?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh=< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh.?/ JXh4 JslackXhA3=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuF>}?:m=^?:?c@=ߗ`=j=>?Z>Q8?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhߗ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh?; J arrival timeXh\?/ JXh4 JslackXhc@=nmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[1]/Cmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu>}'(iF=Ȇ??B=4o=X9=>|?Z>|.?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[1]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= XTg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/timer[1] Jnet (fo=6, routed)Xht= rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__27/I5 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__27/OProp_C6LUT_SLICEM_I5_O JLUT6Xhzru< sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__27_n_0 Jnet (fo=1, routed)Xho< mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y2 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXh4 kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh'; J arrival timeXhq=?/ JXh4 JslackXhB=k0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[23]/CGCSFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu 0>}_ף\=…?ף?+iF=9H=l=>1 ?Z>'1(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)} 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[23]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=p -)SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/Q[7] Jnet (fo=5, routed)Xhl=y GCSFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[27].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y2 (CLOCK_ROOT)y GCSFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/C JFDREXhzr> Jclock pessimismXh EASFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]Hold_GFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh_; J arrival timeXhƛ?/ JXh4 JslackXh+iF=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuY%>}rpQf=^?r?K=5.<ʡ==>?Z>7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)XhO= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__26/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__26/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh5.< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhv?/ JXh4 JslackXhK=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu+>}9zԨBz=x?Ԩ?K=9.<v=E=>t?Z>u8?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__26/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__26/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?u?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh9.< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh9z; J arrival timeXhٞ?/ JXh4 JslackXhK=]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuS=}zeף;+?z?L=A`eo=@=>?Z> njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh%?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhA`e [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhA`?/ JXh4 JslackXhL=}!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}AC-AZd &1@Zd@A=А=E@]Q>?$I@M??t8?5^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG? okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/OProp_B5LUT_SLICEL_I2_O JLUT4XhzrC> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 Jnet (fo=1, routed)Xht> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrFs> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 Jnet (fo=2, routed)Xht? kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh]Q>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhC-A; J arrival timeXhC/ JXh4 JslackXhE@ }!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}AC-AZd &1@Zd@A=А=E@]Q>?$I@M??t8?5^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG? okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/OProp_B5LUT_SLICEL_I2_O JLUT4XhzrC> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 Jnet (fo=1, routed)Xht> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrFs> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 Jnet (fo=2, routed)Xht? kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh]Q>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhC-A; J arrival timeXhC/ JXh4 JslackXhE@ D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A-AZdW^1@Zd@A=А={@cR>>+n@M?$?t8?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhcR>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh-A; J arrival timeXhx/ JXh4 JslackXh{@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A-AZdW^1@Zd@A=А=+K|@cR>>Vn@M?$?t8?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhcR>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh-A; J arrival timeXhA`/ JXh4 JslackXh+K|@O$d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[2]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1 LUT4=1 LUT6=3)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu]@}A0AP.79@P@A=А= @da>m?+?@M?/?t8?!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[2]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrO > [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/Q[2] Jnet (fo=7, routed)Xh1,? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_6__26/I1 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_6__26/OProp_C5LUT_SLICEM_I1_O JLUT2Xhzr{.> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_6__26_n_0 Jnet (fo=3, routed)Xh ? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__26/I1 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__26/OProp_F6LUT_SLICEM_I1_O JLUT6XhzrGz> kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/s1_from_syndromes[0] Jnet (fo=33, routed)Xh1? qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__26/OProp_F6LUT_SLICEL_I2_O JLUT4XhzfQ= rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__26_n_0 Jnet (fo=1, routed)Xh&> plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__53/I4 JXhzf okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__53/OProp_H6LUT_SLICEM_I4_O JLUT6Xhzrgff> qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__53_n_0 Jnet (fo=1, routed)Xh= > xtg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__53/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__53/OProp_B6LUT_SLICEM_I3_O JLUT6Xhzrgff> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhT@X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh|@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhda>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regSetup_BFF_SLICEM_C_D JFDREXh}=/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh @!D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu+@}A-ASf[^1@S@A=А=x@ R>>zd@M?$?t8?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh R>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh-A; J arrival timeXhr/ JXh4 JslackXhx@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu+@}A-ASf[^1@S@A=А=x@ R>>zd@M?$?t8?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXh R>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh-A; J arrival timeXhr/ JXh4 JslackXhx@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu~@}A޾-ASf[^1@S@A=А=#@ R>>Id@M?$?t8?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh R>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh޾-A; J arrival timeXhZ/ JXh4 JslackXh#@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu~@}A޾-ASf[^1@S@A=А=#@ R>>Id@M?$?t8?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh R>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh޾-A; J arrival timeXhZ/ JXh4 JslackXh#@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/CE"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu~@}A-AP^1@@A=А=VL@&R>>(d@M?$?t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhV? okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrҍ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhˡ@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr> Jclock pessimismXh&R>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh-A; J arrival timeXhI/ JXh4 JslackXhVL@( !gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!)y@1y @9Ay@Iy @e\@hq} < vv?%% rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[28].rx_data_ngccm_reg[28][73]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuJs>}In>?n?<ԽD=\B>K> ?U ?b0?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[28][73] Jnet (fo=1, routed)Xh\B>] +'SFP_GEN[28].rx_data_ngccm_reg[28][73]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhЂ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][73]/C JFDCEXhzr> Jclock pessimismXhԽs )%SFP_GEN[28].rx_data_ngccm_reg[28][73]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhI; J arrival timeXh ?/ JXh4 JslackXh<g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsup=>}:S~=?S?d =![=Q=K>?U ?"2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__27/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__27/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<ߟ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh:; J arrival timeXh㥫?/ JXh4 JslackXhd =g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[28].rx_data_ngccm_reg[28][21]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu~>}S݁=F?S?=;D=/=K>|?U ?"2?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[28][21] Jnet (fo=1, routed)Xh/=] +'SFP_GEN[28].rx_data_ngccm_reg[28][21]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/݄?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)Xh<ߟ?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][21]/C JFDCEXhzr> Jclock pessimismXh;s )%SFP_GEN[28].rx_data_ngccm_reg[28][21]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh==+'SFP_GEN[28].rx_data_ngccm_reg[28][72]/C0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu(>}Υİ =Z?İ?`=}Nʡ= =K>*\?U ?i-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)y +'SFP_GEN[28].rx_data_ngccm_reg[28][72]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[83]_0[64] Jnet (fo=1, routed)Xhrh=_ 1-SFP_GEN[28].ngCCM_gbt/RX_Word_rx40[72]_i_1/I1 JXhzr 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40[72]_i_1/OProp_B6LUT_SLICEM_I1_O JLUT3Xhzr<u 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40[72]_i_1_n_0 Jnet (fo=1, routed)Xhu<b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][72]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXh}Nx .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhΥ; J arrival timeXhx?/ JXh4 JslackXh`=rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C{wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuK7>}Hsh=S?sh?=XVE=Q=K>O ?U ?.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/READY_O Jnet (fo=3, routed)Xhw= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/I4 JXhzr tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/OProp_D5LUT_SLICEM_I4_O JLUT5Xhzr #= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_I Jnet (fo=1, routed)XhD< {wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhz?X1Y2 (CLOCK_ROOT) rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) {wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhXV yug_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regHold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhH; J arrival timeXhq=?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu2A>}o`=?o?&=$=v=K>?U ?-2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__27/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__27/OProp_H6LUT_SLICEM_I2_O JLUT3Xhzr@= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh$ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh(?/ JXh4 JslackXh&=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuD>}PnW5=o?n?ͣ*=F=5^=K> ?U ?b0?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhF g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhP; J arrival timeXh䥫?/ JXh4 JslackXhͣ*=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuC>})\1=ף?)\?T.=)=-=K>?U ?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__27/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__27/OProp_D5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhT.=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuϡE>})\1=ף?)\?6=)`=5^=K>?U ?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xhʡ= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/OProp_A6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhX?/ JXh4 JslackXh6=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C*&SFP_GEN[28].rx_data_ngccm_reg[28][3]/D""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu-2>}zİ=X9?İ? 0;=QD=%>K>?U ?i-?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[28][3] Jnet (fo=1, routed)Xh%>\ *&SFP_GEN[28].rx_data_ngccm_reg[28][3]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)XhO?X1Y2 (CLOCK_ROOT)\ *&SFP_GEN[28].rx_data_ngccm_reg[28][3]/C JFDCEXhzr> Jclock pessimismXhQs ($SFP_GEN[28].rx_data_ngccm_reg[28][3]Hold_BFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhz; J arrival timeXh~?/ JXh4 JslackXh 0;={!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuMb@}A(2A-}?E@-@A=А=\@d>?GB@?5?T?I ?x?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzrgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhَ> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh(2A; J arrival timeXh / JXh4 JslackXh\@ {!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu'1@}A\2A-}?E@-@A=А=3]@¨d>?~B@?5?T?I ?^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzrgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhَ> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 Jnet (fo=2, routed)XhR> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhT@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh¨d>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh\2A; J arrival timeXh/ JXh4 JslackXh3]@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuP@}AԐ2Ap-/}?E@p-@A=А=5m@d>W?u8@?5?T?I ?9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzrgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrP> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhV> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA`@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhԐ2A; J arrival timeXh-/ JXh4 JslackXh5m@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsut@}A2Ap-/}?E@p-@A=А=*n@d>W?Nb8@?5?T?I ?9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzrgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrP> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA`@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh2A; J arrival timeXh{/ JXh4 JslackXh*n@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu~@}An2A$. }?E@$.@A=А=Gp@d>̼?6@?5?T?I ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzfgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn2A; J arrival timeXh/ JXh4 JslackXhGp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu~@}An2A$. }?E@$.@A=А=Gp@d>̼?6@?5?T?I ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzfgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_AFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn2A; J arrival timeXh/ JXh4 JslackXhGp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuq=@}A2Aˡ-D%}?E@ˡ-@A=А=p@۵d>̼?{6@?5?T?I ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzfgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhh@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh۵d>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh2A; J arrival timeXh0/ JXh4 JslackXhp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsugf@}A2A$. }?E@$.@A=А=p@d>̼?ff6@?5?T?I ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzfgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh2A; J arrival timeXh&/ JXh4 JslackXhp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsugf@}A2A$. }?E@$.@A=А=p@d>̼?ff6@?5?T?I ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzfgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ8> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh2A; J arrival timeXh&/ JXh4 JslackXhp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu @}A 2A.}?E@.@A=А=#u@$d>O?1@?5?T?I ?#۩?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhl@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzrgff> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)XhX9> vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhJ *@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh$d>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh 2A; J arrival timeXh/ JXh4 JslackXh#u@ ( !gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!)y@1y @9Ay@Iy @eA@hq}  = vv?&&9 rise - rise rise - rise  eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuxh>}`堿QU= ׃?`? =939H=v=>'1?Z>9(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[21] Jnet (fo=1, routed)Xhv= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhi?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhp?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/C JFDCEXhzr> Jclock pessimismXh93 c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh =g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[29].rx_data_ngccm_reg[29][21]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu5,>}d#)\& =?)\?.=9H=F=>9?Z>ˡ%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[29][21] Jnet (fo=1, routed)XhF=] +'SFP_GEN[29].rx_data_ngccm_reg[29][21]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~j?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_74 Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[29].rx_data_ngccm_reg[29][21]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[29].rx_data_ngccm_reg[29][21]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhd#; J arrival timeXh?/ JXh4 JslackXh.='g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C+'g_rx_rs_err[29].rx_rs_err_cnt_reg[29]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuC>}ږ롿[=X9??>:=o=I >>?Z>*?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_0 Jnet (fo=4, routed)XhS= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/g_rx_rs_err[29].rx_rs_err_cnt[29]_i_1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/g_rx_rs_err[29].rx_rs_err_cnt[29]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzru<b g_gbt_bank[2].gbtbank_n_195 Jnet (fo=1, routed)Xho<] +'g_rx_rs_err[29].rx_rs_err_cnt_reg[29]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK Jnet (fo=674, routed)Xhj?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_74 Jnet (fo=674, routed)Xhv?X1Y3 (CLOCK_ROOT)] +'g_rx_rs_err[29].rx_rs_err_cnt_reg[29]/C JFDREXhzr> Jclock pessimismXhs )%g_rx_rs_err[29].rx_rs_err_cnt_reg[29]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhږ; J arrival timeXh?/ JXh4 JslackXh>:=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsut>}i&;,= ׃?&?y;=@?=L=>'1?Z>L7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__28/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__28/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh@? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhi; J arrival timeXhE?/ JXh4 JslackXhy;=>+'SFP_GEN[29].rx_data_ngccm_reg[29][44]/C0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu)>}rM5?)=?M?.}K=//@[=T=>~ ?Z> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)x +'SFP_GEN[29].rx_data_ngccm_reg[29][44]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[29].ngCCM_gbt/RX_Word_rx40[44]_i_1/I1 JXhzr 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40[44]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzrj<=u 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_74 Jnet (fo=674, routed)XhIl?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[29].rx_data_ngccm_reg[29][44]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhَ?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXh//@x .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhr; J arrival timeXhΗ?/ JXh4 JslackXh.}K=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuw>}i&;,= ׃?&?aO=@?=Q8=>'1?Z>L7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__28/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__28/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXh@? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhi; J arrival timeXhz?/ JXh4 JslackXhaO=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuv>}7G=?7?ǬQ=Oq5=Y=>^ ?Z>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__28/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__28/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr/]= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXhOq5 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhu?/ JXh4 JslackXhǬQ=]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/Cb^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuE6>}pB[=B`??V=ʡ==>C ?Z>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzfD= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_to_bitSlipCtrller_5 Jnet (fo=10, routed)Xh= gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_inv_i_1__29/I0 JXhzf fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_inv_i_1__29/OProp_D6LUT_SLICEM_I0_O JLUT6Xhzr< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xho< b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhVm?X1Y3 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhV?X1Y3 (CLOCK_ROOT) b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXh `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_invHold_DFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXhp; J arrival timeXh(?/ JXh4 JslackXhV= +'SFP_GEN[29].rx_data_ngccm_reg[29][28]/C0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuK7>}C)\=?)\?W=D=$>>9?Z>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)y +'SFP_GEN[29].rx_data_ngccm_reg[29][28]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD=w 40SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] Jnet (fo=1, routed)Xh$>b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_74 Jnet (fo=674, routed)Xh~j?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[29].rx_data_ngccm_reg[29][28]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhy .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhC; J arrival timeXh ?/ JXh4 JslackXhW=_[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[2]/C_[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg/D"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu>}\;,=?\?|%X=F@v=im=> ?Z>1,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[2]/QProp_HFF2_SLICEL_C_Q JFDCEXhzfD= YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress[2] Jnet (fo=8, routed)Xh1,= d`g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_i_1__29/I0 JXhzf c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_i_1__29/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_i_1__29_n_0 Jnet (fo=1, routed)Xho< _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhDl?X1Y3 (CLOCK_ROOT) _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg/C JFDCEXhzr> Jclock pessimismXhF@ ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_regHold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXh|%X=~g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu@}A C-A5'10@@A=А=A@Q>+?A`@M?o?t8?Ȧ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzrlg> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh ? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh C-A; J arrival timeXh/ JXh4 JslackXhA@ }g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuʡ@}AUO-A5'10@@A=А=vA@Q>+?_@M?o?t8?Ȧ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzrlg> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhw? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhUO-A; J arrival timeXhU/ JXh4 JslackXhvA@ b!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuz@}A -AnX| '10@n@A=А= H@Q>Mb?ʡM@M?o?t8?r?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhL> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/OProp_B5LUT_SLICEM_I2_O JLUT4Xhzrҍ> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 Jnet (fo=1, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh -A; J arrival timeXh / JXh4 JslackXh H@ b!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuz@}A -AnX| '10@n@A=А= H@Q>Mb?ʡM@M?o?t8?r?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhL> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/OProp_B5LUT_SLICEM_I2_O JLUT4Xhzrҍ> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 Jnet (fo=1, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh -A; J arrival timeXh / JXh4 JslackXh H@ ~g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu#۝@}AUO-A5'10@@A=А=UI@Q>+? X@M?o?t8?Ȧ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzrlg> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)XhA? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhUO-A; J arrival timeXh/ JXh4 JslackXhUI@ pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu@}AqW-A^'10@^@A=А=NK@wQ>x?U@M?o?t8?> ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhC> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhwQ>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhqW-A; J arrival timeXh:/ JXh4 JslackXhNK@ og_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuz@}A[-A^'10@^@A=А=8GL@wQ>x?U@M?o?t8?> ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhL7> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhwQ>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh[-A; J arrival timeXhu/ JXh4 JslackXh8GL@ og_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuК@}AO-Aq'10@@A=А=I~P@ĤQ>x?-R@M?o?t8?Ԩ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh\@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhĤQ>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhO-A; J arrival timeXhx/ JXh4 JslackXhI~P@ pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu@}A:-Ax/'10@x@A=А=bP@Q>x?uP@M?o?t8?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhʡ> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh:-A; J arrival timeXh/ JXh4 JslackXhbP@ og_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu@}A9G-Ax/'10@x@A=А=Q@Q>x?NbP@M?o?t8?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh= '@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrA`e> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhA> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh9G-A; J arrival timeXh/ JXh4 JslackXhQ@ ( !gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!)y@1y @9Ay@Iy @ep@hq} D= tv?'' rise - rise rise - rise  mg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsui;=}ʑ}?֣;?}??D=To=Q8=>L7)?->~J?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/error_detected_msb Jnet (fo=4, routed)Xh+= xtg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__59/I5 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__59/OProp_A6LUT_SLICEM_I5_O JLUT6Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)XhEv?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xhʑ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhT g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regHold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhʑ; J arrival timeXh?/ JXh4 JslackXhD=Eeag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[37]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu:A>}"O+=x?+?I= 79H=)\>>|?->V.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[37]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[37] Jnet (fo=1, routed)Xh)\> eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"[?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr> Jclock pessimismXh 7 c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh"O; J arrival timeXh?/ JXh4 JslackXhI=wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Cwsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuS=}X9K֣;x?K?L=Qo=@=>|?->.?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] Jnet (fo=2, routed)Xh)\= |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__30/I5 JXhzr {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__30/OProp_A6LUT_SLICEL_I5_O JLUT6Xhzru< }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__30_n_0 Jnet (fo=1, routed)XhD< wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"[?X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ׃?X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhQ uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhX9; J arrival timeXh?/ JXh4 JslackXhL=]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuS=}񂿍֣;Ev??L=]Io=@=> ?->)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/ready_from_bitSlipCtrller_6 Jnet (fo=2, routed)Xh)\= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_i_1__29/I2 JXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_i_1__29/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_i_1__29_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhvX?X1Y3 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh8?X1Y3 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh]I [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh񂿐; J arrival timeXhX?/ JXh4 JslackXhL=mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuS=}񂿍֣;Ev??L=Fo=@=> ?->K7)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= XTg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh)\= rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__30/I0 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__30/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru< sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__30_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhvX?X1Y3 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&?X1Y3 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhF kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh񂿐; J arrival timeXhX?/ JXh4 JslackXhL=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[30].rx_data_ngccm_reg[30][32]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsut>}1X9=}?u?X9?N=%S%9H=[=>~ ?->r(?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[30][32] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[30].rx_data_ngccm_reg[30][32]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPW?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)XhĀ?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][32]/C JFDCEXhzr> Jclock pessimismXh%S%t )%SFP_GEN[30].rx_data_ngccm_reg[30][32]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh1; J arrival timeXhV?/ JXh4 JslackXhN=Xg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuT>}P&?)=?P?O==%={=>~*?->O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__29/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__29/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPw?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhi?/ JXh4 JslackXhO=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}4Qi5=6^??fO=$==@=>)?->)\O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[1] Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__29/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__29/OProp_D5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh? w?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh$= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh4; J arrival timeXh.?/ JXh4 JslackXhfO=sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuJ>}CnKչ=Kw?K?Q='Dv==>D ?->.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_BFF2_SLICEL_C_Q JFDCEXhzfD= qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh/= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[20]_i_1__31/I0 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[20]_i_1__31/OProp_A6LUT_SLICEL_I0_O JLUT5Xhzr< `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg00[20] Jnet (fo=1, routed)XhD< eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ׃?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzr> Jclock pessimismXh'D c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhCn; J arrival timeXh?/ JXh4 JslackXhQ=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuw>}P&?)=?P?S==[=/]=>~*?->O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__29/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__29/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPw?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh.?/ JXh4 JslackXhS=%D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[30].ngccm_status_reg_reg[30][21]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu"@}Ay,0AT% >^)@T%@A=А=p@G>a>{@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xh/d?a /+SFP_GEN[30].ngccm_status_reg_reg[30][21]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)` .*SFP_GEN[30].ngccm_status_reg_reg[30][21]/C JFDPEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhy ,(SFP_GEN[30].ngccm_status_reg_reg[30][21]Setup_HFF2_SLICEM_C_CE JFDPEXhim/ JXh< J required timeXhy,0A; J arrival timeXh/ JXh4 JslackXhp@!D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[30].ngccm_status_reg_reg[30][2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu"@}Ay,0AT% >^)@T%@A=А=p@G>a>{@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xh/d?` .*SFP_GEN[30].ngccm_status_reg_reg[30][2]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)_ -)SFP_GEN[30].ngccm_status_reg_reg[30][2]/C JFDCEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhx +'SFP_GEN[30].ngccm_status_reg_reg[30][2]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhy,0A; J arrival timeXh/ JXh4 JslackXhp@!D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[30].ngccm_status_reg_reg[30][7]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu"@}Ay,0AT% >^)@T%@A=А=p@G>a>{@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xh/d?` .*SFP_GEN[30].ngccm_status_reg_reg[30][7]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)_ -)SFP_GEN[30].ngccm_status_reg_reg[30][7]/C JFDCEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhx +'SFP_GEN[30].ngccm_status_reg_reg[30][7]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhy,0A; J arrival timeXh/ JXh4 JslackXhp@$D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[30].ngccm_status_reg_reg[30][18]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu= @}A80AT% >^)@T%@A=А=5q@G>a>@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xhd?a /+SFP_GEN[30].ngccm_status_reg_reg[30][18]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)` .*SFP_GEN[30].ngccm_status_reg_reg[30][18]/C JFDPEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhx ,(SFP_GEN[30].ngccm_status_reg_reg[30][18]Setup_EFF_SLICEM_C_CE JFDPEXhGa/ JXh< J required timeXh80A; J arrival timeXhl/ JXh4 JslackXh5q@$D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[30].ngccm_status_reg_reg[30][23]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu= @}A80AT% >^)@T%@A=А=5q@G>a>@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xhd?a /+SFP_GEN[30].ngccm_status_reg_reg[30][23]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)` .*SFP_GEN[30].ngccm_status_reg_reg[30][23]/C JFDPEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhx ,(SFP_GEN[30].ngccm_status_reg_reg[30][23]Setup_HFF_SLICEM_C_CE JFDPEXhGa/ JXh< J required timeXh80A; J arrival timeXhl/ JXh4 JslackXh5q@ D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[30].ngccm_status_reg_reg[30][5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu= @}A80AT% >^)@T%@A=А=5q@G>a>@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xhd?` .*SFP_GEN[30].ngccm_status_reg_reg[30][5]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)_ -)SFP_GEN[30].ngccm_status_reg_reg[30][5]/C JFDCEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhw +'SFP_GEN[30].ngccm_status_reg_reg[30][5]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh80A; J arrival timeXhl/ JXh4 JslackXh5q@ D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[30].ngccm_status_reg_reg[30][8]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu= @}A80AT% >^)@T%@A=А=5q@G>a>@*??5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhR@s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/I1 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT2XhzrL7>_ rx_test_comm_cnt235_out Jnet (fo=18, routed)Xhd?` .*SFP_GEN[30].ngccm_status_reg_reg[30][8]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT)_ -)SFP_GEN[30].ngccm_status_reg_reg[30][8]/C JFDCEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhw +'SFP_GEN[30].ngccm_status_reg_reg[30][8]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh80A; J arrival timeXhl/ JXh4 JslackXh5q@g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuЎ@}AE0A$&MN]=/@$&@A=А==Zt@̯F>>-@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh&@^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh{@X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][66]/C JFDCEXhzr> Jclock pessimismXh̯F>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][66]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhE0A; J arrival timeXh5^/ JXh4 JslackXh=Zt@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuЎ@}AE0A$&MN]=/@$&@A=А==Zt@̯F>>-@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh&@^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh{@X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][70]/C JFDCEXhzr> Jclock pessimismXh̯F>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][70]Setup_BFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhE0A; J arrival timeXh5^/ JXh4 JslackXh=Zt@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuЎ@}AE0A$&MN]=/@$&@A=А==Zt@̯F>>-@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh&@^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh{@X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][73]/C JFDCEXhzr> Jclock pessimismXh̯F>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][73]Setup_CFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhE0A; J arrival timeXh5^/ JXh4 JslackXh=Zt@L( !gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!)y@1y @9Ay@Iy @e[f`@hq} '< wv?((  rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*&SFP_GEN[31].rx_data_ngccm_reg[31][4]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu/$>}QPL=H?P?'<D=l=S>ff&?>_I?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[31][4] Jnet (fo=1, routed)Xhl=\ *&SFP_GEN[31].rx_data_ngccm_reg[31][4]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhbx?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)\ *&SFP_GEN[31].rx_data_ngccm_reg[31][4]/C JFDCEXhzr> Jclock pessimismXhs ($SFP_GEN[31].rx_data_ngccm_reg[31][4]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhQ; J arrival timeXh|?/ JXh4 JslackXh'<g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu.>}[ZȖ.f=Qx?Ȗ?q%= =1=S>?>(1(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__30/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__30/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh[Z; J arrival timeXh?/ JXh4 JslackXhq%=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[31].rx_data_ngccm_reg[31][79]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuxh>}3Ȗx@=w?Ȗ?=&9H=v=S>r?>(1(?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[31][79] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[31].rx_data_ngccm_reg[31][79]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][79]/C JFDCEXhzr> Jclock pessimismXh&t )%SFP_GEN[31].rx_data_ngccm_reg[31][79]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh3; J arrival timeXh|?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[31].rx_data_ngccm_reg[31][69]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu}&>}}?+=w?}??#=D==S>r?>%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[31][69] Jnet (fo=1, routed)Xh=] +'SFP_GEN[31].rx_data_ngccm_reg[31][69]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][69]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[31].rx_data_ngccm_reg[31][69]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhĐ?/ JXh4 JslackXh#=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[31].rx_data_ngccm_reg[31][73]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsun>}3Ȗx@=w?Ȗ?#=&D=[=S>r?>(1(?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[31][73] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[31].rx_data_ngccm_reg[31][73]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][73]/C JFDCEXhzr> Jclock pessimismXh&t )%SFP_GEN[31].rx_data_ngccm_reg[31][73]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh3; J arrival timeXh@5?/ JXh4 JslackXh#=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu|.>}l =C?l?,==ʡ=5^=S>+'?>xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__30/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__30/OProp_D6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh%?/ JXh4 JslackXh,=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu/>}l =C?l?u0==ʡ=j=S>+'?>xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__30/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__30/OProp_C6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh&?/ JXh4 JslackXhu0=0*&SFP_GEN[31].rx_data_ngccm_reg[31][0]/C/+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu|.>}[== ="?= ?5= ף=Q=S>z&?>:H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)w *&SFP_GEN[31].rx_data_ngccm_reg[31][0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] Jnet (fo=1, routed)XhP=^ 0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[0]_i_1/I1 JXhzr /+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[0]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT3Xhzr<t 1-SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xhvx?X1Y3 (CLOCK_ROOT)\ *&SFP_GEN[31].rx_data_ngccm_reg[31][0]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)a /+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhw -)SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh[=; J arrival timeXha?/ JXh4 JslackXh5=<+'SFP_GEN[31].rx_data_ngccm_reg[31][37]/C0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuj<>}Χݔ=?Χ? 5=v=5^=S>/$?>q=J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)x +'SFP_GEN[31].rx_data_ngccm_reg[31][37]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[83]_0[29] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[36]_i_1/I0 JXhzr 0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[36]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[36]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xh+v?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][37]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhx .*SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh 5=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu&1>}l =C?l?8==-= =S>+'?>xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__30/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__30/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhsh?/ JXh4 JslackXh8={!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsup=@}A +AZd#_&)@Zd@A=А=[f`@@>?4@2?n?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 Jnet (fo=2, routed)Xhr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh +A; J arrival timeXh/ JXh4 JslackXh[f`@ {!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsup=@}A +AZd#_&)@Zd@A=А=[f`@@>?4@2?n?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 Jnet (fo=2, routed)Xhr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh +A; J arrival timeXh/ JXh4 JslackXh[f`@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu$@}A+AW9d1&)@W9@A=А=rk@@>?;@2?n?"?y?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhˡ%? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhrk@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu`@}A+AW9d1&)@W9@A=А=Zk@@>?S;@2?n?"?y?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh$? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh+A; J arrival timeXhx/ JXh4 JslackXhZk@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu@}A}+AZd#_&)@Zd@A=А=`w@@>?.@2?n?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh}+A; J arrival timeXh33/ JXh4 JslackXh`w@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu@}A}+AZd#_&)@Zd@A=А=`w@@>?.@2?n?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh}+A; J arrival timeXh33/ JXh4 JslackXh`w@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu+@}A +AZd#_&)@Zd@A=А=w@@>?.@2?n?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh +A; J arrival timeXh/ JXh4 JslackXhw@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu+@}A +AZd#_&)@Zd@A=А=w@@>?.@2?n?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh@>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh +A; J arrival timeXh/ JXh4 JslackXhw@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu…@}Ay+ASb&)@S@A=А=;y@t@>?W-@2?n?"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> > tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXht@>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhy+A; J arrival timeXhV/ JXh4 JslackXh;y@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu…@}Ay+ASb&)@S@A=А=;y@t@>?W-@2?n?"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh|? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> > tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXht@>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhy+A; J arrival timeXhV/ JXh4 JslackXh;y@ ( !gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!)y@1y @9Ay@Iy @eQ@hq} `J= uv?))! rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C*&SFP_GEN[32].rx_data_ngccm_reg[32][7]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu/$>}Hc e=(?c?`J=D=l=G>)?5^>2L?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[32][7] Jnet (fo=1, routed)Xhl=\ *&SFP_GEN[32].rx_data_ngccm_reg[32][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)\ *&SFP_GEN[32].rx_data_ngccm_reg[32][7]/C JFDCEXhzr> Jclock pessimismXhr ($SFP_GEN[32].rx_data_ngccm_reg[32][7]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhH; J arrival timeXhĠ?/ JXh4 JslackXh`J=>+'SFP_GEN[32].rx_data_ngccm_reg[32][46]/C0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu/>}.:ѣ=Ƌ?:?f=-=1=G>L7)?5^>OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)x +'SFP_GEN[32].rx_data_ngccm_reg[32][46]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[83]_0[38] Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[32].ngCCM_gbt/RX_Word_rx40[46]_i_1/I1 JXhzr 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40[46]_i_1/OProp_G5LUT_SLICEL_I1_O JLUT3Xhzr=u 2.SFP_GEN[32].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh$y?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][46]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~??X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXhy .*SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh.; J arrival timeXh?/ JXh4 JslackXhf=eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuxh>}D:zN=㥋?:?=4D==G>(?5^>OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[39] Jnet (fo=1, routed)Xh= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhy?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh~??X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]/C JFDCEXhzr> Jclock pessimismXh4 c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhD; J arrival timeXhҝ?/ JXh4 JslackXh=q0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/CB>SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuK7>}ޞ5^%=D?5^?=xTD=$>G>*?5^>ףP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)} 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= EASFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[6] Jnet (fo=1, routed)Xh$>t B>SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh[d{?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy?X1Y4 (CLOCK_ROOT)t B>SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C JFDREXhzr> Jclock pessimismXhxT @}@MԨe=H?Ԩ?C(==5^=G>l'?5^>iM?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/QProp_EFF_SLICEL_C_Q JFDPEXhzr9H= {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[0] Jnet (fo=5, routed)Xhʡ= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__31/I1 JXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__31/OProp_A6LUT_SLICEL_I1_O JLUT3XhzrQ8= c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__31_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhbx?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)XhB`?X1Y4 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh@M; J arrival timeXh\?/ JXh4 JslackXhC(=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuX94>}o/:r=(?:?90=h~ ף==G>)?5^>OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh ף= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__31/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__31/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhh~ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXho/; J arrival timeXh!?/ JXh4 JslackXh90=4g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu)>};X;=?X?E9=6%=1=G> +?5^>N?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__31/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__31/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh6 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh;; J arrival timeXh|?/ JXh4 JslackXhE9=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}a5^`i5=D?5^?:;=2=A=T=G>*?5^>ףP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__31/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__31/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[d{?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh2=A g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXha; J arrival timeXhd;?/ JXh4 JslackXh:;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuz>}Aq=5?)=̌?q=?LC=S5A=`P=G>C+?5^>NbP?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__31/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__31/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhl{?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhȖ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhS5A g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhA; J arrival timeXh)\?/ JXh4 JslackXhLC=eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[27]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuxh>}:=m?:?LC=)?D==G>x)?5^>OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[27]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[27] Jnet (fo=1, routed)Xh= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh~??X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]/C JFDCEXhzr> Jclock pessimismXh)? c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh|?/ JXh4 JslackXhLC=`!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuK@}A30Aˡ%F^>Nb(@ˡ%@A=А=Q@zfI>!?}?]@/?]?|?Zd?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31/OProp_H5LUT_SLICEL_I2_O JLUT4Xhzr7A> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31_n_0 Jnet (fo=1, routed)XhA`> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31_n_0 Jnet (fo=2, routed)Xhl> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y4 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh30A; J arrival timeXh|/ JXh4 JslackXhQ@ `!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuK@}A30Aˡ%F^>Nb(@ˡ%@A=А=Q@zfI>!?}?]@/?]?|?Zd?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31/OProp_H5LUT_SLICEL_I2_O JLUT4Xhzr7A> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31_n_0 Jnet (fo=1, routed)XhA`> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31_n_0 Jnet (fo=2, routed)Xhl> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y4 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh30A; J arrival timeXh|/ JXh4 JslackXhQ@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu™@}ATH0A?5&&>Nb(@?5&@A=А=9e@zfI>5^?VV@/?]?|?D?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhTH0A; J arrival timeXh/ JXh4 JslackXh9e@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu™@}ATH0A?5&&>Nb(@?5&@A=А=9e@zfI>5^?VV@/?]?|?D?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh$@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhTH0A; J arrival timeXh/ JXh4 JslackXh9e@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu@}A\0A+&D+>Nb(@+&@A=А=e@zfI>5^?$V@/?]?|?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh\0A; J arrival timeXh$/ JXh4 JslackXhe@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsui@}Ai0A+&D+>Nb(@+&@A=А=Af@zfI>5^?U@/?]?|?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhi0A; J arrival timeXh/ JXh4 JslackXhAf@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][59]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu@}AY0A+&a<1@+&@A=А=/m@H>>ף@/??|?/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[32] Jnet (fo=76, routed)Xh+?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][59]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][59]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXhv )%SFP_GEN[32].rx_data_ngccm_reg[32][59]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhY0A; J arrival timeXh/ JXh4 JslackXh/m@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][57]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu/ݐ@}Ae0A+&a<1@+&@A=А=}m@H>>D@/??|?/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{>Y rx_data_ngccm[32] Jnet (fo=76, routed)Xh$?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][57]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][57]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXhu )%SFP_GEN[32].rx_data_ngccm_reg[32][57]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhe0A; J arrival timeXh#/ JXh4 JslackXh}m@Lng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu@}A#@0AT%v!>Nb(@T%@A=А=>p@zfI>5^?J@/?]?|?m?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh#@0A; J arrival timeXh'1/ JXh4 JslackXh>p@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu<ߓ@}A;D0AT%v!>Nb(@T%@A=А=&p@zfI>5^?\J@/?]?|?m?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh$@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhzfI>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh;D0A; J arrival timeXhc/ JXh4 JslackXh&p@ ( !gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!)y@1y @9Ay@Iy @e@hq} L< wv?**% rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[33].rx_data_ngccm_reg[33][48]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuMb>}ض]=}?u??L< #D=v=G>y?5^>'?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[33][48] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[33].rx_data_ngccm_reg[33][48]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPW?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][48]/C JFDCEXhzr> Jclock pessimismXh #t )%SFP_GEN[33].rx_data_ngccm_reg[33][48]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhض; J arrival timeXh?/ JXh4 JslackXhL<g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C*&SFP_GEN[33].rx_data_ngccm_reg[33][7]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu;^:>}*y𧖿ۜ=v??&=CD=L7 >G>r?5^>M7)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[33][7] Jnet (fo=1, routed)XhL7 >\ *&SFP_GEN[33].rx_data_ngccm_reg[33][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)Xh43?X1Y4 (CLOCK_ROOT)\ *&SFP_GEN[33].rx_data_ngccm_reg[33][7]/C JFDCEXhzr> Jclock pessimismXhCs ($SFP_GEN[33].rx_data_ngccm_reg[33][7]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh*y; J arrival timeXh!?/ JXh4 JslackXh&=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu3^:>}x󌿍$f=v?$?qK+=>=X9=G>?5^>(1(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__32/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__32/OProp_A6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQX?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh!?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhx󌿐; J arrival timeXhM?/ JXh4 JslackXhqK+=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu@>}_y閿ȶ=Ev?y?/=[=v=G>?5^>_)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__32/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__32/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhvX?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh_; J arrival timeXh33?/ JXh4 JslackXh/=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[33].rx_data_ngccm_reg[33][49]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu~>}ض]=}?u??<= #D=/=G>y?5^>'?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[33][49] Jnet (fo=1, routed)Xh/=] +'SFP_GEN[33].rx_data_ngccm_reg[33][49]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPW?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][49]/C JFDCEXhzr> Jclock pessimismXh #s )%SFP_GEN[33].rx_data_ngccm_reg[33][49]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhض; J arrival timeXh?/ JXh4 JslackXh<=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuz>}Uه+&?)=v?+?1LC=.=`P=G>r?5^>(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__32/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__32/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh. g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhUه; J arrival timeXh?/ JXh4 JslackXh1LC=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuz>};y閿&?)=Pw?y?1LC=.=`P=G>L7 ?5^>_)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__32/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__32/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$Y?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh. g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh;; J arrival timeXhV?/ JXh4 JslackXh1LC==+'SFP_GEN[33].rx_data_ngccm_reg[33][76]/C0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuz>}𝈿K?)=Qx?K?NLC=.=`P=G> ?5^>~*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)x +'SFP_GEN[33].rx_data_ngccm_reg[33][76]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[83]_0[68] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[76]_i_1/I1 JXhzr 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[76]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT3XhzrQ8=u 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][76]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ׃?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXh.x .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh𝈿; J arrival timeXhS?/ JXh4 JslackXhNLC=4g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu>}bև+Y,=+v?+?|C=S.=T=G>'1?5^>(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O85[1] Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__32/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__32/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhS. g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhbև; J arrival timeXh?/ JXh4 JslackXh|C=.sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu433>}!$Zc}=u?Z?qD==G=G>l?5^>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_DFF2_SLICEM_C_Q JFDCEXhzf9H= qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[36]_i_1__28/I0 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[36]_i_1__28/OProp_H6LUT_SLICEM_I0_O JLUT5Xhzro< `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg00[36] Jnet (fo=1, routed)Xho< eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhcX?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xha?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh!$; J arrival timeXhG?/ JXh4 JslackXhqD=`!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuc@}A"*A9^1'@9@A=А=@KXB>?$?/??|?7?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh = okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/OProp_A6LUT_SLICEM_I2_O JLUT4XhzrE= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 Jnet (fo=1, routed)Xh333> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzr(> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 Jnet (fo=2, routed)Xhy> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)XhG?X1Y4 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhKXB>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh"*A; J arrival timeXh/ JXh4 JslackXh@ `!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuc@}A"*A9^1'@9@A=А=@KXB>?$?/??|?7?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh = okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/OProp_A6LUT_SLICEM_I2_O JLUT4XhzrE= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 Jnet (fo=1, routed)Xh333> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzr(> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 Jnet (fo=2, routed)Xhy> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)XhG?X1Y4 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhKXB>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh"*A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuk@}A=,A,#'@@A=А=(@3B>?7!@/??|?S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)Xh7!@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xho?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/C JFDCEXhzr> Jclock pessimismXh3B>@ Jclock uncertaintyXh d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]Setup_AFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh=,A; J arrival timeXhS/ JXh4 JslackXh(@ $eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[97]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1 LUT6=3)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu$n@}AU-Al'@l@A=А=@tB>%?ˡ%@/?sh?|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[97]/QProp_AFF2_SLICEL_C_Q JFDCEXhzrV> plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxencdata_s[9]_53[22] Jnet (fo=9, routed)Xhy? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_16__32/I5 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_16__32/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_16__32_n_0 Jnet (fo=1, routed)XhԸ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_8__32/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_8__32/OProp_E6LUT_SLICEL_I2_O JLUT5Xhzr֣p> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/s3_from_syndromes[2] Jnet (fo=24, routed)XhX9? qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__32/I0 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__32/OProp_D6LUT_SLICEL_I0_O JLUT4XhzfZd> rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__32_n_0 Jnet (fo=1, routed)Xh!> plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__65/I4 JXhzf okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__65/OProp_F6LUT_SLICEL_I4_O JLUT6Xhzr> qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__65_n_0 Jnet (fo=1, routed)Xh!> xtg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__65/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__65/OProp_H6LUT_SLICEM_I3_O JLUT6Xhzr"y> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)Xh*\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[97]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhtB>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regSetup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhU-A; J arrival timeXh/ JXh4 JslackXh@ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsumc@}AN*AajS.'@a@A=А=G@oPB>?k@/??|??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhoPB>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhN*A; J arrival timeXh/ JXh4 JslackXhG@ ng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsumc@}AN*AajS.'@a@A=А=G@oPB>?k@/??|??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhoPB>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhN*A; J arrival timeXh/ JXh4 JslackXhG@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsub@}Ae*AajS.'@a@A=А=p@oPB>?z@/??|??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhoPB>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhe*A; J arrival timeXh@`/ JXh4 JslackXhp@ mg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsub@}Ae*AajS.'@a@A=А=p@oPB>?z@/??|??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhoPB>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhe*A; J arrival timeXh@`/ JXh4 JslackXhp@ |g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsub@}AX*AGE>('@G@A=А=@@B>?@/??|?!?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__33/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__33/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh5^> vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xhn?X1Y4 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh@B>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_FFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhX*A; J arrival timeXhX/ JXh4 JslackXh@ |g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuz^@}A+ArhK7&'@rh@A=А=r@s;B>?(1?/??|??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh ? qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__33/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__33/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk @X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh!?X1Y4 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhs;B>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh / JXh4 JslackXhr@ ( !gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!)y@1y @9Ay@Iy @ef@hq} d= vv?,,) rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu/>}kηҪ=u?η?d=q$ ף=5^=C ?)1?A ?r(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__35/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__35/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh_?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhq$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhk; J arrival timeXhv?/ JXh4 JslackXhd=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu/>}#=??#}=x g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhx}η{=x?η?N =8'%==C ? ?A ?r(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].cnt_reg[0][5] Jnet (fo=14, routed)Xh1= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].cnt[0][1]_i_1__2/I3 JXhzr rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].cnt[0][1]_i_1__2/OProp_C6LUT_SLICEM_I3_O JLUT6Xhzru<m *&g_gbt_bank[3].gbtbank/i_gbt_bank_n_223 Jnet (fo=1, routed)Xho<n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C JFDCEXhzr> Jclock pessimismXh8' :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXhN =g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu433>}irq=X?r?a=BR$X9=-=C ?` ?A ?_)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_15_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__35/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__35/OProp_H5LUT_SLICEM_I2_O JLUT3Xhzr #= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhBR$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_HFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhi; J arrival timeXhw?/ JXh4 JslackXha=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[36].rx_data_ngccm_reg[36][31]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuxh>}ݓK7I=?K7?=sFD==C ?C ?A ?C+?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[36][31] Jnet (fo=1, routed)Xh=] +'SFP_GEN[36].rx_data_ngccm_reg[36][31]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh¥?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][31]/C JFDCEXhzr> Jclock pessimismXhsFt )%SFP_GEN[36].rx_data_ngccm_reg[36][31]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhݓ; J arrival timeXhI?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C*&SFP_GEN[36].rx_data_ngccm_reg[36][5]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu~>}IZd}8s=?Zd?9a&=PHD=/=C ?E ?A ?/?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=U rx_data[36][5] Jnet (fo=1, routed)Xh/=\ *&SFP_GEN[36].rx_data_ngccm_reg[36][5]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][5]/C JFDCEXhzr> Jclock pessimismXhPHr ($SFP_GEN[36].rx_data_ngccm_reg[36][5]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhI; J arrival timeXhS?/ JXh4 JslackXh9a&=1*&SFP_GEN[36].rx_data_ngccm_reg[36][1]/C/+SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsup=>}ƻ{#=㥛?ƻ?]*=gt'=5^=C ?V?A ?Nb0?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)w *&SFP_GEN[36].rx_data_ngccm_reg[36][1]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[83]_0[1] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[0]_i_1/I0 JXhzr /+SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[0]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8=t 1-SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xȟ?X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][1]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X1Y6 (CLOCK_ROOT)a /+SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhgt'w -)SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh]*=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C+'SFP_GEN[36].rx_data_ngccm_reg[36][71]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu?5>}﷿@=??X;6=W$D=>C ?q= ?A ?:(?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[36][71] Jnet (fo=1, routed)Xh>] +'SFP_GEN[36].rx_data_ngccm_reg[36][71]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xhz?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][71]/C JFDCEXhzr> Jclock pessimismXhW$t )%SFP_GEN[36].rx_data_ngccm_reg[36][71]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhA?/ JXh4 JslackXhX;6=Ig_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuw>}rᨿ,*F=??o6=PHo={=C ?|?A ?V.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/feedbackRegister[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__35/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__35/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhPH g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhrᨿ; J arrival timeXh?/ JXh4 JslackXho6=p0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/CHDSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu|.>}r=?r?7='D="=C ?I ?A ?_)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)~ 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/QProp_CFF2_SLICEL_C_Q JFDCEXhzrD=q .*SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/Q[11] Jnet (fo=2, routed)Xh"=z HDSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhƋ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)z HDSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C JFDREXhzr> Jclock pessimismXh' FBSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXh7=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C+'SFP_GEN[36].rx_data_ngccm_reg[36][6]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsutx@}AC*4A"3;˓T@"3@A=А=f@B s>~j>i@?u?(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)Xhj?] +'SFP_GEN[36].rx_data_ngccm_reg[36][6]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xho@X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][6]/C JFDCEXhzr> Jclock pessimismXhB s>@ Jclock uncertaintyXhu ($SFP_GEN[36].rx_data_ngccm_reg[36][6]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhC*4A; J arrival timeXh!/ JXh4 JslackXhf@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C+'SFP_GEN[36].rx_data_ngccm_reg[36][4]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuPbx@}A64A"3;˓T@"3@A=А=Ձ@B s>~j>^i@?u?(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)XhZ?] +'SFP_GEN[36].rx_data_ngccm_reg[36][4]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xho@X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][4]/C JFDCEXhzr> Jclock pessimismXhB s>@ Jclock uncertaintyXht ($SFP_GEN[36].rx_data_ngccm_reg[36][4]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh64A; J arrival timeXh/ JXh4 JslackXhՁ@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][36]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu(\w@}A64A"3;˓T@"3@A=А=X@B s>~j>9h@?u?(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)XhM?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][36]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xho@X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][36]/C JFDCEXhzr> Jclock pessimismXhB s>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][36]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh64A; J arrival timeXh{/ JXh4 JslackXhX@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][35]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuw@}A:4A"3;˓T@"3@A=А=@B s>~j>rh@?u?(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][35]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xho@X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][35]/C JFDCEXhzr> Jclock pessimismXhB s>@ Jclock uncertaintyXhu )%SFP_GEN[36].rx_data_ngccm_reg[36][35]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh:4A; J arrival timeXh/ JXh4 JslackXh@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C+'SFP_GEN[36].rx_data_ngccm_reg[36][1]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu/u@}AF4AZd31đT@Zd3@A=А=@r>~j>+f@?u?(?~?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh?] +'SFP_GEN[36].rx_data_ngccm_reg[36][1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)XhS@X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][1]/C JFDCEXhzr> Jclock pessimismXhr>@ Jclock uncertaintyXht ($SFP_GEN[36].rx_data_ngccm_reg[36][1]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhF4A; J arrival timeXh/ JXh4 JslackXh@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C+'SFP_GEN[36].rx_data_ngccm_reg[36][2]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu s@}AJ4A3(T@3@A=А=|C@Nr>~j>/e@?u?(? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)XhC?] +'SFP_GEN[36].rx_data_ngccm_reg[36][2]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][2]/C JFDCEXhzr> Jclock pessimismXhNr>@ Jclock uncertaintyXhu ($SFP_GEN[36].rx_data_ngccm_reg[36][2]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhJ4A; J arrival timeXhQ/ JXh4 JslackXh|C@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C+'SFP_GEN[36].rx_data_ngccm_reg[36][7]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu s@}AJ4A3(T@3@A=А=|C@Nr>~j>/e@?u?(? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)XhC?] +'SFP_GEN[36].rx_data_ngccm_reg[36][7]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)\ *&SFP_GEN[36].rx_data_ngccm_reg[36][7]/C JFDCEXhzr> Jclock pessimismXhNr>@ Jclock uncertaintyXhu ($SFP_GEN[36].rx_data_ngccm_reg[36][7]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhJ4A; J arrival timeXhQ/ JXh4 JslackXh|C@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu"s@}A'"4A 3ΔT@ 3@A=А=L@s>~j>zd@?u?(?_?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh#?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][19]/C JFDCEXhzr> Jclock pessimismXhs>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][19]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh'"4A; J arrival timeXh/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][21]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu"s@}A'"4A 3ΔT@ 3@A=А=L@s>~j>zd@?u?(?_?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh#?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][21]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][21]/C JFDCEXhzr> Jclock pessimismXhs>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][21]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh'"4A; J arrival timeXh/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu"s@}A'"4A 3ΔT@ 3@A=А=L@s>~j>zd@?u?(?_?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrQ=Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh#?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][24]/C JFDCEXhzr> Jclock pessimismXhs>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][24]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh'"4A; J arrival timeXh/ JXh4 JslackXhL@L( !gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!)y@1y @9Ay@Iy @eG@hq} XP< G$?--, rise - rise rise - rise  q0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[25]/CGCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu'>}mV=I??XP<R9H==Т>x)?j>L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)~ 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[25]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H=p -)SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/Q[9] Jnet (fo=2, routed)Xh=y GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhGz?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)y GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/C JFDREXhzr> Jclock pessimismXhR EASFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhmV; J arrival timeXhG?/ JXh4 JslackXhXP<F+'SFP_GEN[46].rx_data_ngccm_reg[46][42]/C0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu&1>}vk5=1??=W-= =Т>(?j>VM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)x +'SFP_GEN[46].rx_data_ngccm_reg[46][42]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[83]_0[34] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[42]_i_1/I1 JXhzr 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[42]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3Xhzr=u 2.SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[42]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[3].gbtbank_n_124 Jnet (fo=674, routed)Xh5^z?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[46].rx_data_ngccm_reg[46][42]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXhWy .*SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhv; J arrival timeXh-?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[46].rx_data_ngccm_reg[46][32]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu+>}- =??=N9H==Т>'?j>q=J?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[46][32] Jnet (fo=1, routed)Xh=] +'SFP_GEN[46].rx_data_ngccm_reg[46][32]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_124 Jnet (fo=674, routed)XhX9?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[46].rx_data_ngccm_reg[46][32]/C JFDCEXhzr> Jclock pessimismXhNs )%SFP_GEN[46].rx_data_ngccm_reg[46][32]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh- ; J arrival timeXha?/ JXh4 JslackXh=p0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/CGCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu/$>}GɛlH=I?l?#=2r9H=A`=Т>x)?j>_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)} 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=p -)SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/Q[2] Jnet (fo=5, routed)XhA`=y GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhGz?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)y GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C JFDREXhzr> Jclock pessimismXh2r EASFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhGɛ; J arrival timeXh`?/ JXh4 JslackXh#=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu?>}BMbHট>y&@MbH@ޓ$=?X~j>>M"?C?n2?t@z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_EFF_SLICEM_C_Q JFDCEXhzrl= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh(\> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__45/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__45/OProp_C6LUT_SLICEM_I2_O JLUT3Xhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/-@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh?X g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEM_C_D JFDREXhI >/ JXh< J required timeXhB; J arrival timeXhiE@/ JXh4 JslackXhޓ$=4fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[37]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuE6>}Мr-=?r? /=l9H=>Т>'?j>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[37]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= `\g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[37] Jnet (fo=1, routed)Xh> fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr> Jclock pessimismXhl d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhМ; J arrival timeXhM?/ JXh4 JslackXh /=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsut>};Shoi5=|?h?K 3=}IC=L=Т>;/?j>V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__45/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__45/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh}IC g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh;S; J arrival timeXh?/ JXh4 JslackXhK 3=G+'SFP_GEN[46].rx_data_ngccm_reg[46][78]/C0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu>}AgfFל>< '@gfF@L>=X^>j<>M"??n2?/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)y +'SFP_GEN[46].rx_data_ngccm_reg[46][78]/QProp_CFF2_SLICEM_C_Q JFDCEXhzrl=w 40SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[83]_0[70] Jnet (fo=1, routed)Xhw>_ 1-SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[78]_i_1/I1 JXhzr 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[78]_i_1/OProp_H5LUT_SLICEM_I1_O JLUT3Xhzr>u 2.SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[78]_i_1_n_0 Jnet (fo=1, routed)XhA`<b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[3].gbtbank_n_124 Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)] +'SFP_GEN[46].rx_data_ngccm_reg[46][78]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33+@X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXhXy .*SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]Hold_HFF2_SLICEM_C_D JFDCEXho>/ JXh< J required timeXhA; J arrival timeXh1D@/ JXh4 JslackXhL>=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuw>};Shoi5=|?h?-G=}IC=Q8=Т>;/?j>V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__45/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__45/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh}IC g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh;S; J arrival timeXh\?/ JXh4 JslackXh-G=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuD>}D=Ƌ??$K=RX9==Т>r(?j>{N?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xhj= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__45/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__45/OProp_D5LUT_SLICEM_I2_O JLUT3Xhzr #= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[2] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$y?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXhR g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhD; J arrival timeXhZ?/ JXh4 JslackXh$K=!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuz@}AH`0A+&9->c(@+&@A=А=G@,F>?@n2??M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 Jnet (fo=1, routed)Xh"> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 Jnet (fo=2, routed)Xhx> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y9 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhH`0A; J arrival timeXhU / JXh4 JslackXhG@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuz@}AH`0A+&9->c(@+&@A=А=G@,F>?@n2??M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 Jnet (fo=1, routed)Xh"> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 Jnet (fo=2, routed)Xhx> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y9 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhH`0A; J arrival timeXhU / JXh4 JslackXhG@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuף@}A|0A&G4>c(@&@A=А=ě0@,F>l?@n2??M"? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzf"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/I0 JXhzf |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/OProp_F6LUT_SLICEM_I0_O JLUT6XhzrGz> c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X1Y9 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh|0A; J arrival timeXhV/ JXh4 JslackXhě0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuף@}A|0A< 'T5>c(@< '@A=А=ț0@,F>l?@n2??M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzf"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/I0 JXhzf |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/OProp_F6LUT_SLICEM_I0_O JLUT6XhzrGz> c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh|0A; J arrival timeXhV/ JXh4 JslackXhț0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuף@}A|0A< 'T5>c(@< '@A=А=ț0@,F>l?@n2??M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzf"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/I0 JXhzf |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/OProp_F6LUT_SLICEM_I0_O JLUT6XhzrGz> c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh|0A; J arrival timeXhV/ JXh4 JslackXhț0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu@}A0A< 'T5>c(@< '@A=А=0@,F>l?8@n2??M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzf"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/I0 JXhzf |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/OProp_F6LUT_SLICEM_I0_O JLUT6XhzrGz> c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXhE/ JXh4 JslackXh0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu@}A0A< 'T5>c(@< '@A=А=0@,F>l?8@n2??M"??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzf"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/I0 JXhzf |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/OProp_F6LUT_SLICEM_I0_O JLUT6XhzrGz> c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXhE/ JXh4 JslackXh0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu@}A{h0Ay&3>c(@y&@A=А=9@,F>?J z@n2??M"?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh"[> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhR> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh{h0A; J arrival timeXh/ JXh4 JslackXh9@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu@}A{h0Ay&3>c(@y&@A=А=9@,F>?J z@n2??M"?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh"[> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhR> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh{h0A; J arrival timeXh/ JXh4 JslackXh9@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu ׯ@}At0Ay&3>c(@y&@A=А=:@,F>?y@n2??M"?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhP@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr"y> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh"[> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh,F>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXht0A; J arrival timeXh/ JXh4 JslackXh:@ ( !gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!)y@1y @9Ay@Iy @e%aN@hq} = uv?../ rise - rise rise - rise  u0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[23]/CGCSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu0>}z"۩r=Ƌ?"۩?=T3D==M>;(?Zd>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)} 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[23]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD=p -)SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/Q[7] Jnet (fo=5, routed)Xh=y GCSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$y?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff?X1Y9 (CLOCK_ROOT)y GCSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/C JFDREXhzr> Jclock pessimismXhT3 EASFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhz; J arrival timeXh?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[47].rx_data_ngccm_reg[47][48]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuxh>}u1Z=v?1?=5D==M>|.?Zd>tS?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[47][48] Jnet (fo=1, routed)Xh=] +'SFP_GEN[47].rx_data_ngccm_reg[47][48]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_134 Jnet (fo=674, routed)Xhu?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[47].rx_data_ngccm_reg[47][48]/C JFDCEXhzr> Jclock pessimismXh5t )%SFP_GEN[47].rx_data_ngccm_reg[47][48]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhu; J arrival timeXhأ?/ JXh4 JslackXh=Gtpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu|.>}PQ=p??O=y1%="=M>1,?Zd>*\O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzfD= rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh5^= kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[26]_i_1__38/I1 JXhzf jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[26]_i_1__38/OProp_C6LUT_SLICEM_I1_O JLUT5Xhzru< a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[26] Jnet (fo=1, routed)Xho< fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh,?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr> Jclock pessimismXhy1 d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh33?/ JXh4 JslackXhO=Gtpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu-2>}PQ=p??r"=y1o=G=M>1,?Zd>*\O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzfD= rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh= kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[25]_i_1__38/I1 JXhzf jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[25]_i_1__38/OProp_D6LUT_SLICEM_I1_O JLUT5Xhzro< a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[25] Jnet (fo=1, routed)Xho< fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh,?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzr> Jclock pessimismXhy1 d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhF?/ JXh4 JslackXhr"=Gtpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu'>}V:A=p?:?#=Io==M>1,?Zd>L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF2_SLICEL_C_Q JFDCEXhzfD= rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh1= kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[24]_i_1__38/I0 JXhzf jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[24]_i_1__38/OProp_H6LUT_SLICEM_I0_O JLUT5Xhzro< a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[24] Jnet (fo=1, routed)Xho< fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh~??X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr> Jclock pessimismXhI d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhV; J arrival timeXhn?/ JXh4 JslackXh#=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[47].rx_data_ngccm_reg[47][79]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuz>}ƫIF=َ?ƫ?Z*=$5D==M>.?Zd>R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[47][79] Jnet (fo=1, routed)Xh=] +'SFP_GEN[47].rx_data_ngccm_reg[47][79]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_134 Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[47].rx_data_ngccm_reg[47][79]/C JFDCEXhzr> Jclock pessimismXh$5t )%SFP_GEN[47].rx_data_ngccm_reg[47][79]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhrh?/ JXh4 JslackXhZ*=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[47].rx_data_ngccm_reg[47][55]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuX9>}G=??:=D9H=+>M>W-?Zd>أP?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[47][55] Jnet (fo=1, routed)Xh+>] +'SFP_GEN[47].rx_data_ngccm_reg[47][55]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_134 Jnet (fo=674, routed)Xh+?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[47].rx_data_ngccm_reg[47][55]/C JFDCEXhzr> Jclock pessimismXhDs )%SFP_GEN[47].rx_data_ngccm_reg[47][55]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhG; J arrival timeXh?/ JXh4 JslackXh:={0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[27]/CHDSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu+>}K5>=̌??+<=$k9H==M>*?Zd>J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)~ 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[27]/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H=q .*SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/Q[11] Jnet (fo=2, routed)Xh=z HDSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhX9?X1Y9 (CLOCK_ROOT)z HDSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C JFDREXhzr> Jclock pessimismXh$k FBSFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]Hold_GFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhK; J arrival timeXh-?/ JXh4 JslackXh+<=Gtpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuX9>}PQ=p??n]?=y1v==M>1,?Zd>*\O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzfD= rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh5^= kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[37]_i_1__38/I1 JXhzf jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[37]_i_1__38/OProp_A6LUT_SLICEM_I1_O JLUT5Xhzr< a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[37] Jnet (fo=1, routed)XhD< fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh,?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzr> Jclock pessimismXhy1 d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhn]?=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu/$>},ƫn=h?ƫ?@=(6ʡ==M>I,?Zd>R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh+= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__46/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__46/OProp_H6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh(6 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh,; J arrival timeXh-?/ JXh4 JslackXh@=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuʩ@}AB2A&2(>>ff&@&@A=А=%aN@MD> ?= @`0?? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xh= @ fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]Setup_HFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhB2A; J arrival timeXh/ JXh4 JslackXh%aN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu @}AB2A&2(>>ff&@&@A=А=[@MD>c?y@`0?? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[4]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[4] J GTHE3_CHANNELXhzrc? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[4] Jnet (fo=6, routed)Xhy@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]/C JFDCEXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]Setup_HFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhB2A; J arrival timeXh@5/ JXh4 JslackXh[@!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuО@}A0AB`%3>ff&@B`%@A=А=4\@MD>Q?xY@`0?? ?q=?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh*@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I0 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 Jnet (fo=1, routed)XhO= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/OProp_A6LUT_SLICEL_I5_O JLUT6XhzrE= qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 Jnet (fo=2, routed)Xh5^> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhO @X1Y9 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh4\@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuО@}A0AB`%3>ff&@B`%@A=А=4\@MD>Q?xY@`0?? ?q=?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh*@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I0 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh/> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 Jnet (fo=1, routed)XhO= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/OProp_A6LUT_SLICEL_I5_O JLUT6XhzrE= qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 Jnet (fo=2, routed)Xh5^> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhO @X1Y9 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh4\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuh@}AiH0AV&FC>ff&@V&@A=А=m_@MD>~?T]@`0?? ?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh*@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I0 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh ? uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhE@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhiH0A; J arrival timeXh/ JXh4 JslackXhm_@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsux@}AL0AV&FC>ff&@V&@A=А=_@MD>~?-]@`0?? ?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh*@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I0 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhE@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhL0A; J arrival timeXh/ JXh4 JslackXh_@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuW9@}A/2A$&j4@>ff&@$&@A=А=>a@MD> ?z@`0?? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[1] Jnet (fo=10, routed)Xhz@ gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh{@X1Y9 (CLOCK_ROOT) gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]/C JFDCEXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]Setup_DFF2_SLICEM_C_D JFDCEXhL7=/ JXh< J required timeXh/2A; J arrival timeXhl/ JXh4 JslackXh>a@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu\@}AZ2Az&?.?>ff&@z&@A=А=Id@MD>l?shi@`0?? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[11]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[11] J GTHE3_CHANNELXhzr? ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[13] Jnet (fo=6, routed)Xhf@ kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[33]_i_1__38/I3 JXhzr jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[33]_i_1__38/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrA`e> a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[33] Jnet (fo=1, routed)Xh= fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]Setup_CFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhZ2A; J arrival timeXh/ JXh4 JslackXhId@g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu-@}Ae/A$->ff&@$@A=А=e@MD>~?$V@`0?? ?x?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh*@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I0 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh%? uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhe/A; J arrival timeXh`/ JXh4 JslackXhe@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu&@}A/A/$+>ff&@/$@A=А=lf@MD>~?VU@`0?? ?L7?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh*@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I0 JXhzf qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhX> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh33 @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhMD>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXhZ/ JXh4 JslackXhlf@ ( !gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!)y@1y @9Ay@Iy @eF@hq}  = xv?//2 rise - rise rise - rise  8g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu +>} )󭿭fN=8?? =ìʡ=X9=K>` ? ?(1(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/O85[1] Jnet (fo=2, routed)Xh㥛= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__36/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__36/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh!?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhì g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ); J arrival timeXhy?/ JXh4 JslackXh =8g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuw>}a?^=a??٭=r6o={=K>r? ?x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__36/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__36/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhr6 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXha; J arrival timeXh?/ JXh4 JslackXh٭=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C+'SFP_GEN[37].rx_data_ngccm_reg[37][61]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}Þv;N=G?v?l&=59H==K>L7 ? ?M7)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[37][61] Jnet (fo=1, routed)Xh=] +'SFP_GEN[37].rx_data_ngccm_reg[37][61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh ?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][61]/C JFDCEXhzr> Jclock pessimismXh5t )%SFP_GEN[37].rx_data_ngccm_reg[37][61]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhÞ; J arrival timeXh?/ JXh4 JslackXhl&=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[37].rx_data_ngccm_reg[37][67]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu >}P󭿭l=w??0=o6D=e;=K>$? ?(1(?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[37][67] Jnet (fo=1, routed)Xhe;=] +'SFP_GEN[37].rx_data_ngccm_reg[37][67]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh~?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][67]/C JFDCEXhzr> Jclock pessimismXho6s )%SFP_GEN[37].rx_data_ngccm_reg[37][67]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhP; J arrival timeXh ף?/ JXh4 JslackXh0=<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CGCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu'>}󟿍ƫ\=?ƫ?դ1=No==K>? ? #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gbtBank_Clk_gen[1].cnt_reg[1][7]_0[0] Jnet (fo=10, routed)Xh1= ~zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i[1]_i_1__2/I4 JXhzr }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i[1]_i_1__2/OProp_D6LUT_SLICEL_I4_O JLUT6Xhzru<m *&g_gbt_bank[3].gbtbank/i_gbt_bank_n_146 Jnet (fo=1, routed)Xho<y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)XhQ?X1Y6 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C JFDCEXhzr> Jclock pessimismXhN EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh󟿐; J arrival timeXh?/ JXh4 JslackXhդ1= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuϡE>}v:=?v?*5==E=K>U? ?M7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xhw= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__36/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__36/OProp_C5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĀ?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXh*5=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[37].rx_data_ngccm_reg[37][68]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuv>>}%󭿭= ??C9=9H=I >K>y? ?(1(?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[37][68] Jnet (fo=1, routed)XhI >] +'SFP_GEN[37].rx_data_ngccm_reg[37][68]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh~?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][68]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[37].rx_data_ngccm_reg[37][68]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh%; J arrival timeXh?/ JXh4 JslackXhC9=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuz>}`)\?)=?)\?1LC=Z5A=`P=K>~ ? ? +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__36/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__36/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhZ5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh`; J arrival timeXhz?/ JXh4 JslackXh1LC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuK7>} )󭿭fN=8??72I=ìX9=5^=K>` ? ?(1(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] Jnet (fo=2, routed)Xhw= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__36/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__36/OProp_B5LUT_SLICEM_I2_O JLUT3Xhzrw= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhT< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh!?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhì g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_BFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ); J arrival timeXhr?/ JXh4 JslackXh72I=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu)>}䛝?)=&??L}K=Z5A[=T=K>? ?x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__36/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__36/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhZ5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh䛝; J arrival timeXh?/ JXh4 JslackXhL}K=rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu(\w@}A1AG*a5zD@G*@A=А=F@ 8d>|?@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh ? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh 8d>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhF@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu+w@}A1AG*a5zD@G*@A=А= @ 8d>|?l@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh ? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh 8d>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh @ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuH r@}A1A*^4zD@*@A=А=@l5d>|?M@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)XhH@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhl5d>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh1A; J arrival timeXhC/ JXh4 JslackXh@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu$q@}A1A*^4zD@*@A=А=粈@l5d>|?@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhx> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)XhH@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhl5d>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh+/ JXh4 JslackXh粈@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu$q@}A1A*^4zD@*@A=А=粈@l5d>|?@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhx> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)XhH@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhl5d>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh+/ JXh4 JslackXh粈@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu$q@}A1A*^4zD@*@A=А=粈@l5d>|?@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhx> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)XhH@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhl5d>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh+/ JXh4 JslackXh粈@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuIt@}A 3A5^2-MzD@5^2@A=А=k@:n>|?D@{?z???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`P> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/OProp_A6LUT_SLICEM_I3_O JLUT5Xhzrx> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)XhM@X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh:n>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh 3A; J arrival timeXhNb/ JXh4 JslackXhk@ Mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuo@}Ae3An2IzD@n2@A=А=ɍ@n>|?c@{?z??n?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36/OProp_B6LUT_SLICEM_I1_O JLUT6Xhzrx> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36_n_0 Jnet (fo=2, routed)Xh> > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh5^@X1Y6 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhe3A; J arrival timeXh$/ JXh4 JslackXhɍ@ Mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuo@}Ae3An2IzD@n2@A=А=ɍ@n>|?c@{?z??n?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36/OProp_B6LUT_SLICEM_I1_O JLUT6Xhzrx> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36_n_0 Jnet (fo=2, routed)Xh> > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh5^@X1Y6 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhe3A; J arrival timeXh$/ JXh4 JslackXhɍ@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuzo@}A3A[2/@zD@[2@A=А=T@W}n> ׳?@{?z??S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhv? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/I0 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzf +> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhN> |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__37/I0 JXhzf {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__37/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG)@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK Jnet (fo=674, routed)Xh~@X1Y6 (CLOCK_ROOT) wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhW}n>@ Jclock uncertaintyXh uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXhT@ ( !gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!)y@1y @9Ay@Iy @eӦw@hq} = vv?00; rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[38].rx_data_ngccm_reg[38][76]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuE6>}5X=q??=;D=>S>M?> #?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[38][76] Jnet (fo=1, routed)Xh>] +'SFP_GEN[38].rx_data_ngccm_reg[38][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xh&?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][76]/C JFDCEXhzr> Jclock pessimismXh;t )%SFP_GEN[38].rx_data_ngccm_reg[38][76]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh5; J arrival timeXh?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C+'SFP_GEN[38].rx_data_ngccm_reg[38][78]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuE6>}5X=q??=;D=>S>M?> #?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[38][78] Jnet (fo=1, routed)Xh>] +'SFP_GEN[38].rx_data_ngccm_reg[38][78]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xh&?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][78]/C JFDCEXhzr> Jclock pessimismXh;t )%SFP_GEN[38].rx_data_ngccm_reg[38][78]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh5; J arrival timeXh?/ JXh4 JslackXh==+'SFP_GEN[38].rx_data_ngccm_reg[38][34]/C0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu&1>}6=53s??+$=3X9={=S> ?>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)x +'SFP_GEN[38].rx_data_ngccm_reg[38][34]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[34]_i_1/I1 JXhzr 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[34]_i_1/OProp_H5LUT_SLICEM_I1_O JLUT3Xhzr #=u 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][34]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhأ?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh3y .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhx?/ JXh4 JslackXh+$=eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuS>}?>U%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[24] Jnet (fo=1, routed)Xh= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEV?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXh4# c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh} :/=s??1=%D==S>?>"?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[38][7] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[38].rx_data_ngccm_reg[38][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhEV?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhأ?X1Y7 (CLOCK_ROOT)\ *&SFP_GEN[38].rx_data_ngccm_reg[38][7]/C JFDCEXhzr> Jclock pessimismXh%r ($SFP_GEN[38].rx_data_ngccm_reg[38][7]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh(?/ JXh4 JslackXh1=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuX->}Q~QE=t??N4=# ף=E=S>̡?>\"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__37/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__37/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKW?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhQ~; J arrival timeXh ?/ JXh4 JslackXhN4=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsut>}mA`J,=Fs?A`?y;=0=L=S>Z?>A`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__37/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__37/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh0 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhm; J arrival timeXhI?/ JXh4 JslackXhy;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[38].rx_data_ngccm_reg[38][58]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu^d;>}}? =X9t?}??56<=D=p= >S>/?>%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[38][58] Jnet (fo=1, routed)Xhp= >] +'SFP_GEN[38].rx_data_ngccm_reg[38][58]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+V?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhʁ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][58]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[38].rx_data_ngccm_reg[38][58]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh8?/ JXh4 JslackXh56<=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu +>}%SВÂ=s?В?l A=F ף=-=S>?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__37/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__37/OProp_H6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhEV?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS~?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhF g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh%S; J arrival timeXh)\?/ JXh4 JslackXhl A=6mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsui;=}&z֣;!r?z?D=So=Q8=S>S?>#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= XTg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh+= rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__38/I0 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__38/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzru< sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__38_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK Jnet (fo=674, routed)XhT?X1Y7 (CLOCK_ROOT) mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhS kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh&; J arrival timeXhK?/ JXh4 JslackXhD=`!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu-@}A%+A](u(@@A=А=Ӧw@A>\?o+@2?G?"?n?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhc> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 Jnet (fo=1, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/OProp_A6LUT_SLICEL_I5_O JLUT6Xhzr`P= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 Jnet (fo=2, routed)XhA`> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB` @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh ?X1Y7 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh%+A; J arrival timeXhv/ JXh4 JslackXhӦw@ `!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu|@}AN1+AV&u(@@A=А=x@A>\?H*@2?G?"?"?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhc> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/OProp_B6LUT_SLICEL_I2_O JLUT4XhzrA`> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 Jnet (fo=1, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/OProp_A6LUT_SLICEL_I5_O JLUT6Xhzr`P= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 Jnet (fo=2, routed)Xh > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB` @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhN1+A; J arrival timeXh6^/ JXh4 JslackXhx@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsù@}A*A9A<u(@9@A=А=x@OA>Zd?m+@2?G?"?<ߟ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_G6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhG? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB` @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)XhG?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhOA>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhx@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][66]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsurx@}A[+AHk0@H@A=А=R@c@>w>zd@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)Xh^?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][66]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][66]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhv )%SFP_GEN[38].rx_data_ngccm_reg[38][66]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh[+A; J arrival timeXhף/ JXh4 JslackXhR@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][69]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsurx@}A[+AHk0@H@A=А=R@c@>w>zd@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)Xh^?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][69]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhv )%SFP_GEN[38].rx_data_ngccm_reg[38][69]Setup_BFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh[+A; J arrival timeXhף/ JXh4 JslackXhR@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][71]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsurx@}A[+AHk0@H@A=А=R@c@>w>zd@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)Xh^?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][71]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][71]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhv )%SFP_GEN[38].rx_data_ngccm_reg[38][71]Setup_CFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh[+A; J arrival timeXhף/ JXh4 JslackXhR@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][65]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuAx@}A_+AHk0@H@A=А=4@c@>w>Id@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)XhX?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][65]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][65]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhu )%SFP_GEN[38].rx_data_ngccm_reg[38][65]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh_+A; J arrival timeXhC/ JXh4 JslackXh4@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][68]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuAx@}A_+AHk0@H@A=А=4@c@>w>Id@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)XhX?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][68]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][68]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhu )%SFP_GEN[38].rx_data_ngccm_reg[38][68]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh_+A; J arrival timeXhC/ JXh4 JslackXh4@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][70]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuAx@}A_+AHk0@H@A=А=4@c@>w>Id@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)XhX?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][70]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][70]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhu )%SFP_GEN[38].rx_data_ngccm_reg[38][70]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh_+A; J arrival timeXhC/ JXh4 JslackXh4@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[38].rx_data_ngccm_reg[38][72]/CE""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuAx@}A_+AHk0@H@A=А=4@c@>w>Id@2??"?Y9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhe;? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr&1>Y rx_data_ngccm[38] Jnet (fo=76, routed)XhX?^ ,(SFP_GEN[38].rx_data_ngccm_reg[38][72]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xhˡ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][72]/C JFDCEXhzr> Jclock pessimismXhc@>@ Jclock uncertaintyXhu )%SFP_GEN[38].rx_data_ngccm_reg[38][72]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh_+A; J arrival timeXhC/ JXh4 JslackXh4@L( !gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!)y@1y @9Ay@Iy @eJ@hq}  = vv?11 rise - rise rise - rise  0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[29]/CHDSFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu>} ͉K0|=u?K? =G$9H=a=>  ?->.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)~ 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[29]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/Q[13] Jnet (fo=2, routed)Xha=z HDSFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhcX?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[39].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ׃?X1Y7 (CLOCK_ROOT)z HDSFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C JFDREXhzr> Jclock pessimismXhG$ FBSFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]Hold_FFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh ͉; J arrival timeXh@5?/ JXh4 JslackXh =g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[39].rx_data_ngccm_reg[39][52]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsup=>}as=s??mS=}9H=C >>L7 ?->2,?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[39][52] Jnet (fo=1, routed)XhC >] +'SFP_GEN[39].rx_data_ngccm_reg[39][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhEV?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xh]?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][52]/C JFDCEXhzr> Jclock pessimismXh}s )%SFP_GEN[39].rx_data_ngccm_reg[39][52]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXha; J arrival timeXh?/ JXh4 JslackXhmS=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[39].rx_data_ngccm_reg[39][39]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu'>}㌿•vג=y?•?c=ND=i=>V?->+?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[39][39] Jnet (fo=1, routed)Xhi=] +'SFP_GEN[39].rx_data_ngccm_reg[39][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[d[?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)XhM?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][39]/C JFDCEXhzr> Jclock pessimismXhNt )%SFP_GEN[39].rx_data_ngccm_reg[39][39]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh㌿; J arrival timeXh8?/ JXh4 JslackXhc=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu|?>}Mff=u?ff?z%=h=1=> ?->,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__38/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__38/OProp_C5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhW?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXhh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhM; J arrival timeXh!?/ JXh4 JslackXhz%=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsun>}:Ȗoi5=v?Ȗ?.=x-v=L=>1 ?->i-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__38/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__38/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhx- g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh:; J arrival timeXh-?/ JXh4 JslackXh.=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu>}ӉlK=vx?l?6Q==&=`P=> ?->.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__38/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__38/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhHZ?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh& g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhӉ; J arrival timeXhw?/ JXh4 JslackXh6Q==g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuz>}!P5?)=Xy?P?LC=q,=`P=>?->/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__38/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__38/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhq, g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh!; J arrival timeXhd;?/ JXh4 JslackXhLC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuT>}:Ȗoi5=v?Ȗ?kC=x-=Q8=>1 ?->i-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__38/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__38/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXhx- g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh:; J arrival timeXhV?/ JXh4 JslackXhkC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[39].rx_data_ngccm_reg[39][70]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu]B>}>T㕿I?=u?T?^F=pD=rh>>  ?->+?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[39][70] Jnet (fo=1, routed)Xhrh>] +'SFP_GEN[39].rx_data_ngccm_reg[39][70]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhcX?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhn?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][70]/C JFDCEXhzr> Jclock pessimismXhps )%SFP_GEN[39].rx_data_ngccm_reg[39][70]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh>; J arrival timeXh43?/ JXh4 JslackXh^F=Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu)>}t;,=u??(G=/-=Y=>  ?->0,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/O85[1] Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__38/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__38/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhcX?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh/- g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXht; J arrival timeXh-?/ JXh4 JslackXh(G=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][48]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}A+AxP/@@A=А=J@>>xi>@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xh/?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][48]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][48]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhv )%SFP_GEN[39].rx_data_ngccm_reg[39][48]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh+A; J arrival timeXh-/ JXh4 JslackXhJ@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][51]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}A+AxP/@@A=А=J@>>xi>@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xh/?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][51]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][51]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhv )%SFP_GEN[39].rx_data_ngccm_reg[39][51]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh+A; J arrival timeXh-/ JXh4 JslackXhJ@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][53]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}A+AxP/@@A=А=J@>>xi>@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xh/?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][53]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][53]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhv )%SFP_GEN[39].rx_data_ngccm_reg[39][53]Setup_GFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh+A; J arrival timeXh-/ JXh4 JslackXhJ@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][69]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}A+AxP/@@A=А=J@>>xi>@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xh/?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][69]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhv )%SFP_GEN[39].rx_data_ngccm_reg[39][69]Setup_HFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh+A; J arrival timeXh-/ JXh4 JslackXhJ@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][47]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuҙ@}A]+AxP/@@A=А=AVK@>>xi>+@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xhz?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][47]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][47]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhu )%SFP_GEN[39].rx_data_ngccm_reg[39][47]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh]+A; J arrival timeXh/ JXh4 JslackXhAVK@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][50]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuҙ@}A]+AxP/@@A=А=AVK@>>xi>+@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xhz?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][50]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][50]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhu )%SFP_GEN[39].rx_data_ngccm_reg[39][50]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh]+A; J arrival timeXh/ JXh4 JslackXhAVK@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][52]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuҙ@}A]+AxP/@@A=А=AVK@>>xi>+@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xhz?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][52]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][52]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhu )%SFP_GEN[39].rx_data_ngccm_reg[39][52]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh]+A; J arrival timeXh/ JXh4 JslackXhAVK@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][63]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuҙ@}A]+AxP/@@A=А=AVK@>>xi>+@*?S?5^?H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xhz?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][63]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhb?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][63]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhu )%SFP_GEN[39].rx_data_ngccm_reg[39][63]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh]+A; J arrival timeXh/ JXh4 JslackXhAVK@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][54]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}AZa+ACq삾P/@C@A=А=Q@>>xi>Ў@*?S?5^?K7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xhˡ?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][54]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhff?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][54]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhv )%SFP_GEN[39].rx_data_ngccm_reg[39][54]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhZa+A; J arrival timeXhT/ JXh4 JslackXhQ@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[39].rx_data_ngccm_reg[39][65]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}AZa+ACq삾P/@C@A=А=Q@>>xi>Ў@*?S?5^?K7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6XhzrE=Y rx_data_ngccm[39] Jnet (fo=76, routed)Xhˡ?^ ,(SFP_GEN[39].rx_data_ngccm_reg[39][65]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhff?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][65]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhv )%SFP_GEN[39].rx_data_ngccm_reg[39][65]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhZa+A; J arrival timeXhT/ JXh4 JslackXhQ@L( !gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!)y@1y @9Ay@Iy @eSKh@hq} W= uv?228 rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuj<>})㥫=p?㥫?W=7=Q=M>1,?Zd>!R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__39/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__39/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh7 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh); J arrival timeXh?/ JXh4 JslackXhW=9g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}㥫b=-?㥫?=K6%=-=M>E,?Zd>!R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF2_SLICEL_C_Q JFDCEXhzrD= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__39/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__39/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh.}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhK6 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXha?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[40].rx_data_ngccm_reg[40][60]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu >}򛿍㥫j=p?㥫?h"=6D== =M>1,?Zd>!R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[40][60] Jnet (fo=1, routed)Xh= =] +'SFP_GEN[40].rx_data_ngccm_reg[40][60]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)Xh'1?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][60]/C JFDCEXhzr> Jclock pessimismXh6s )%SFP_GEN[40].rx_data_ngccm_reg[40][60]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh򛿐; J arrival timeXh%?/ JXh4 JslackXhh"=+'SFP_GEN[40].rx_data_ngccm_reg[40][28]/C0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu!>}O|=v?O?%=7D=G=M>|.?Zd>V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)x +'SFP_GEN[40].rx_data_ngccm_reg[40][28]/QProp_GFF_SLICEM_C_Q JFDCEXhzrD=w 40SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] Jnet (fo=1, routed)XhG=b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)Xhe;?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][28]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh#ۙ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXh7y .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXh%=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[40].rx_data_ngccm_reg[40][56]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuS>}򛿍㥫j=p?㥫?5*=69H==M>1,?Zd>!R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[40][56] Jnet (fo=1, routed)Xh=] +'SFP_GEN[40].rx_data_ngccm_reg[40][56]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)Xh'1?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][56]/C JFDCEXhzr> Jclock pessimismXh6s )%SFP_GEN[40].rx_data_ngccm_reg[40][56]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh򛿐; J arrival timeXhG?/ JXh4 JslackXh5*=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu:A>})㥫=p?㥫?8.=7={=M>1,?Zd>!R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__39/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__39/OProp_C5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[8] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr> Jclock pessimismXh7 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh); J arrival timeXhˡ?/ JXh4 JslackXh8.=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[40].rx_data_ngccm_reg[40][47]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu >}C~Qf=/?C?`7=y7D=d;=M> +?Zd>Q?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[40][47] Jnet (fo=1, routed)Xhd;=] +'SFP_GEN[40].rx_data_ngccm_reg[40][47]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh |?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)XhΗ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][47]/C JFDCEXhzr> Jclock pessimismXhy7s )%SFP_GEN[40].rx_data_ngccm_reg[40][47]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhG?/ JXh4 JslackXh`7=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsut>}DCJ,=-?C?y;=LA=L=M>E,?Zd>Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__39/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__39/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh.}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhΗ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXhLA g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhD; J arrival timeXh ?/ JXh4 JslackXhy;=rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/Cb^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu >} כ/N=?5??v>=6o=E=M>h-?Zd>nR?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnt[0] Jnet (fo=6, routed)Xh= gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_inv_i_1__40/I3 JXhzr fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_inv_i_1__40/OProp_C6LUT_SLICEM_I3_O JLUT6Xhzru< ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xho< b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)XhQ~?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhc?X1Y8 (CLOCK_ROOT) b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXh6 `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_invHold_CFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh כ; J arrival timeXhʡ?/ JXh4 JslackXhv>=@,(SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}C㥫d11=?㥫?r?=EAo==M>W-?Zd>!R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)y ,(SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=i &"SFP_GEN[40].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)Xh+=_ 1-SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__15/I1 JXhzr 0,SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__15/OProp_C6LUT_SLICEM_I1_O JLUT4Xhzru<u 2.SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__15_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5~?X1Y8 (CLOCK_ROOT)^ ,(SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X1Y8 (CLOCK_ROOT)^ ,(SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXhEAt *&SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_regHold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhC; J arrival timeXhף?/ JXh4 JslackXhr?=d!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuI@}AFP0Aef&%>Nb(@ef&@A=А=SKh@.>E>֣?AH@&1??$!?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhFP0A; J arrival timeXhz/ JXh4 JslackXhSKh@ d!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuI@}AFP0Aef&%>Nb(@ef&@A=А=SKh@.>E>֣?AH@&1??$!?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhFP0A; J arrival timeXhz/ JXh4 JslackXhSKh@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@}A0Aˡ%5>Nb(@ˡ%@A=А=*j@.>E> ?O@&1??$!??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhc? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh*j@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@}A0Aˡ%5>Nb(@ˡ%@A=А=*j@.>E> ?O@&1??$!??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhc? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh*j@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@}A7#0Aˡ%5>Nb(@ˡ%@A=А=j@.>E> ?vO@&1??$!??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh= ? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh7#0A; J arrival timeXh/ JXh4 JslackXhj@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@}A7#0Aˡ%5>Nb(@ˡ%@A=А=j@.>E> ?vO@&1??$!??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh= ? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh7#0A; J arrival timeXh/ JXh4 JslackXhj@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@}A7#0Aˡ%5>Nb(@ˡ%@A=А=j@.>E> ?vO@&1??$!??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhV> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh= ? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhh @X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh7#0A; J arrival timeXh/ JXh4 JslackXhj@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuO@}AFP2A&,>Nb(@&@A=А= ?n@.>E>%a?4^z@&1??$!?W?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL1[1]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL1[1] J GTHE3_CHANNELXhzr%a? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[19] Jnet (fo=6, routed)Xh4^z@ eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]/C JFDCEXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhFP2A; J arrival timeXh/ JXh4 JslackXh ?n@g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]/D"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuv@}AX2A֣(VI>Nb(@֣(@A=А=$ns@.>E>w?g@&1??$!?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[15]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[15] J GTHE3_CHANNELXhzrw? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[17] Jnet (fo=6, routed)Xhg@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]/C JFDCEXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]Setup_DFF2_SLICEM_C_D JFDCEXhL7=/ JXh< J required timeXhX2A; J arrival timeXh/ JXh4 JslackXh$ns@g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu{@}AFP0Aef&%>Nb(@ef&@A=А=ҵt@.>E>= ?ף@@&1??$!?(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzfgff> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__40/I0 JXhzf {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__40/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y> b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh$> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh/ @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh.>E>@ Jclock uncertaintyXh uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_AFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhFP0A; J arrival timeXhE/ JXh4 JslackXhҵt@ ( !gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!)y@1y @9Ay@Iy @e2#@hq} ^X< vv?33 rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][80]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu>}zffц=?ff?^X<KD==>I,?->L?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[41][80] Jnet (fo=1, routed)Xh=] +'SFP_GEN[41].rx_data_ngccm_reg[41][80]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhXy?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][80]/C JFDCEXhzr> Jclock pessimismXhKt )%SFP_GEN[41].rx_data_ngccm_reg[41][80]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhz; J arrival timeXh?/ JXh4 JslackXh^X<g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu|.>}d#l:=?l?J=Kv=j=>~*?->N?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__40/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__40/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPw?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhK g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhd#; J arrival timeXhNb?/ JXh4 JslackXhJ=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][33]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&1>}d;+=~?+?o-=CD=>>r=*?->VM?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[41][33] Jnet (fo=1, routed)Xh>] +'SFP_GEN[41].rx_data_ngccm_reg[41][33]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xho?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][33]/C JFDCEXhzr> Jclock pessimismXhCs )%SFP_GEN[41].rx_data_ngccm_reg[41][33]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhd;; J arrival timeXhأ?/ JXh4 JslackXho-=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsut>}:`i5=C?:?i 3=*>=L=>+?->thQ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__40/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__40/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh*> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh.?/ JXh4 JslackXhi 3=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][26]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu*\>}"=x??s5=4D=j=>'1(?->q=J?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[41][26] Jnet (fo=1, routed)Xhj=] +'SFP_GEN[41].rx_data_ngccm_reg[41][26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh}?u?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][26]/C JFDCEXhzr> Jclock pessimismXh4t )%SFP_GEN[41].rx_data_ngccm_reg[41][26]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhZd?/ JXh4 JslackXhs5=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][55]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsun>}іEQ#-=p=?E?67=4D=[=>^)?->DL?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[41][55] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[41].rx_data_ngccm_reg[41][55]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)XhВ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][55]/C JFDCEXhzr> Jclock pessimismXh4t )%SFP_GEN[41].rx_data_ngccm_reg[41][55]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhі; J arrival timeXhD?/ JXh4 JslackXh67=d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[0]/C{wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuC>}@Mt'=?t?ܥ8=E=`=>~*?->&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[0]/QProp_DFF2_SLICEM_C_Q JFDCEXhzf9H= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/Q[0] Jnet (fo=5, routed)XhQ= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/I3 JXhzf tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/OProp_D5LUT_SLICEM_I3_O JLUT5Xhzr #= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_I Jnet (fo=1, routed)XhD< {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhPw?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh yug_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regHold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh@M; J arrival timeXho?/ JXh4 JslackXhܥ8=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuj<>}vOˡm=Ԉ?ˡ?ZB=-==>y&?->CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__40/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__40/OProp_C5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhs?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhvO; J arrival timeXhNb?/ JXh4 JslackXhZB=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuw>}:`i5=C?:?KG=*>=Q8=>+?->thQ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__40/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__40/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh*> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXhKG=Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuS>}XPJ=~?P?J=5%=j=>r=*?->O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/O83[1] Jnet (fo=2, routed)Xh ף= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__40/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__40/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[1] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh5 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhX; J arrival timeXhV?/ JXh4 JslackXhJ=!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsul@}A@0A%rO>p%@%@A=А=2#@H|G>?v@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhlg> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40_n_0 Jnet (fo=2, routed)Xh > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhT @X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh@0A; J arrival timeXhO/ JXh4 JslackXh2#@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsul@}A@0A%rO>p%@%@A=А=2#@H|G>?v@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhlg> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40_n_0 Jnet (fo=2, routed)Xh > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhT @X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh@0A; J arrival timeXhO/ JXh4 JslackXh2#@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu>5@}AQ0AE&*T>p%@E&@A=А=i7@H|G>23?z@*??5^?d;?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhY> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGz> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhQ0A; J arrival timeXhv/ JXh4 JslackXhi7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsush@}Ai0A& Z>p%@&@A=А=d9@H|G>4^?Ђ@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhi0A; J arrival timeXhb/ JXh4 JslackXhd9@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuO@}Am0A& Z>p%@&@A=А=9@H|G>4^?R@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhm0A; J arrival timeXh/ JXh4 JslackXh9@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A'U0AV&UU>p%@V&@A=А=:@H|G>23?lw@*??5^?)\?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhY> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGz> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_AFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh'U0A; J arrival timeXh/ JXh4 JslackXh:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuj@}A>Y0AV&UU>p%@V&@A=А=Y;@H|G>23?e;w@*??5^?)\?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhY> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGz> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh > vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh>Y0A; J arrival timeXhh/ JXh4 JslackXhY;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}AH0A$&ԿR>p%@$&@A=А=A@H|G>4^? |@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhH0A; J arrival timeXh/ JXh4 JslackXhA@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuԬ@}AL0A$&ԿR>p%@$&@A=А=0B@H|G>4^?z|@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhL0A; J arrival timeXhQ/ JXh4 JslackXh0B@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuԬ@}AL0A$&ԿR>p%@$&@A=А=0B@H|G>4^?z|@*??5^??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhS@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I2 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhH|G>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhL0A; J arrival timeXhQ/ JXh4 JslackXh0B@ ( !gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!)y@1y @9Ay@Iy @e /@hq} = uv?44  rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*&SFP_GEN[42].rx_data_ngccm_reg[42][4]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu_94>}poe=*\o?o?=pD=o>S>?> ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=U rx_data[42][4] Jnet (fo=1, routed)Xho>\ *&SFP_GEN[42].rx_data_ngccm_reg[42][4]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xhe;?X1Y8 (CLOCK_ROOT)\ *&SFP_GEN[42].rx_data_ngccm_reg[42][4]/C JFDCEXhzr> Jclock pessimismXhpr ($SFP_GEN[42].rx_data_ngccm_reg[42][4]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhp; J arrival timeXhA5?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu&1>}g \V!=o?\?= ף=v=S>|>>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)Xh-= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__41/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__41/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhshQ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhg ; J arrival timeXh-?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C+'SFP_GEN[42].rx_data_ngccm_reg[42][57]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsun>}NoxDL=أp?o?C.="D=[=S>G?> ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[42][57] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[42].rx_data_ngccm_reg[42][57]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xhe;?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][57]/C JFDCEXhzr> Jclock pessimismXh"t )%SFP_GEN[42].rx_data_ngccm_reg[42][57]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhN; J arrival timeXh?/ JXh4 JslackXhC.=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[42].rx_data_ngccm_reg[42][51]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuxh>}X\Kd;=أp?\?T$=l#D==S>G?>w?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[42][51] Jnet (fo=1, routed)Xh=] +'SFP_GEN[42].rx_data_ngccm_reg[42][51]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xh@5~?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][51]/C JFDCEXhzr> Jclock pessimismXhl#t )%SFP_GEN[42].rx_data_ngccm_reg[42][51]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhX; J arrival timeXh~?/ JXh4 JslackXhT$=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[42].rx_data_ngccm_reg[42][53]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuxh>}X\Kd;=أp?\?T$=l#D==S>G?>w?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[42][53] Jnet (fo=1, routed)Xh=] +'SFP_GEN[42].rx_data_ngccm_reg[42][53]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xh@5~?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][53]/C JFDCEXhzr> Jclock pessimismXhl#t )%SFP_GEN[42].rx_data_ngccm_reg[42][53]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhX; J arrival timeXh~?/ JXh4 JslackXhT$=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuE6>}g \V!=o?\?s)=E=E=S>|>>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)Xh-= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__41/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__41/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[3] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhshQ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhg ; J arrival timeXhV?/ JXh4 JslackXhs)=1*&SFP_GEN[42].rx_data_ngccm_reg[42][7]/C/+SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu433>}ԉS5=-r?S?5=P-=X9=S>?>G!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)w *&SFP_GEN[42].rx_data_ngccm_reg[42][7]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[83]_0[7] Jnet (fo=1, routed)Xh-=^ 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40[6]_i_1/I0 JXhzr /+SFP_GEN[42].ngCCM_gbt/RX_Word_rx40[6]_i_1/OProp_C5LUT_SLICEM_I0_O JLUT3Xhzr=t 1-SFP_GEN[42].ngCCM_gbt/RX_Word_rx40[6]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)XhzT?X1Y8 (CLOCK_ROOT)\ *&SFP_GEN[42].rx_data_ngccm_reg[42][7]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X1Y8 (CLOCK_ROOT)a /+SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXhPx -)SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhԉ; J arrival timeXh|?/ JXh4 JslackXh5=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[42].rx_data_ngccm_reg[42][47]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu|.>}7j=أp?7?;B=9H==S>G?>-?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[42][47] Jnet (fo=1, routed)Xh=] +'SFP_GEN[42].rx_data_ngccm_reg[42][47]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xh(|?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][47]/C JFDCEXhzr> Jclock pessimismXhs )%SFP_GEN[42].rx_data_ngccm_reg[42][47]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh|?/ JXh4 JslackXh;B=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu>}/oh,= p?o?|C=,=T=S>?> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__41/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__41/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhnR?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh, g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh/; J arrival timeXh?/ JXh4 JslackXh|C=<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/D""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu|.>}]~=w??C=ʡ=5^=S>r?>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][7]_0[4] Jnet (fo=9, routed)Xhʡ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][5]_i_1__2/I4 JXhzr rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][5]_i_1__2/OProp_A6LUT_SLICEL_I4_O JLUT6Xhzr<m *&g_gbt_bank[3].gbtbank/i_gbt_bank_n_308 Jnet (fo=1, routed)XhD<n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhZ?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh8?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/C JFDCEXhzr> Jclock pessimismXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh]; J arrival timeXh?/ JXh4 JslackXhC= D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuX@}A6*AavfI)@a@A=А= /@A>:>̜@2?S?"?A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhMb? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh6*A; J arrival timeXh$/ JXh4 JslackXh /@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu|?@}A*AavfI)@a@A=А=mq/@A>:>:@2?S?"?A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh*A; J arrival timeXhI / JXh4 JslackXhmq/@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuS@}A,*A{O)@@A=А=*:@A>:>Ȗ@2?S?"?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhQ? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,*A; J arrival timeXh / JXh4 JslackXh*:@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuS@}A,*A{O)@@A=А=*:@A>:>Ȗ@2?S?"?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhQ? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,*A; J arrival timeXh / JXh4 JslackXh*:@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu23@}AD*A{O)@@A=А=9;@A>:>@2?S?"?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhη? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhD*A; J arrival timeXh/ JXh4 JslackXh9;@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu23@}AD*A{O)@@A=А=9;@A>:>@2?S?"?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhη? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhD*A; J arrival timeXh/ JXh4 JslackXh9;@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu23@}AD*A{O)@@A=А=9;@A>:>@2?S?"?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhη? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhD*A; J arrival timeXh/ JXh4 JslackXh9;@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuYd@}A/+A#6)@@A=А=[D@MA>:>ْ@2?S?"?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xht? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXhMA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh/+A; J arrival timeXh'1/ JXh4 JslackXh[D@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK@}A3+A-5)@-@A=А=AD@A>:>@2?S?"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh'1? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh3+A; J arrival timeXh/ JXh4 JslackXhAD@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK@}A3+A-5)@-@A=А=AD@A>:>@2?S?"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhshQ@ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/OProp_B5LUT_SLICEL_I1_O JLUT2Xhzr8> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh'1? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhff@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh3+A; J arrival timeXh/ JXh4 JslackXhAD@( !gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!)y@1y @9Ay@Iy @e3j@hq} 4< vv?55  rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu5,>} mį= ׃??4<[ʡ=E=>'1?Z>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__42/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__42/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh[ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh m; J arrival timeXhX?/ JXh4 JslackXh4<]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu-2>}AMNb!=Z?Nb?O*={ʡ=\=>L7 ?Z>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/ready_from_bitSlipCtrller_7 Jnet (fo=2, routed)Xhʡ= b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_i_1__42/I0 JXhzr a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_i_1__42/OProp_C6LUT_SLICEM_I0_O JLUT6Xhzr< WSg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd Jnet (fo=1, routed)Xho< ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh k?X1Y8 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXh{ [Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_regHold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhAM; J arrival timeXh?/ JXh4 JslackXhO*=/sog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuQ8>}'&6=z?&?.="ʡ==>x ?Z>L7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) sog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF_SLICEL_C_Q JFDCEXhzf9H= qmg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)XhE= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[35]_i_1__42/I1 JXhzf ieg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[35]_i_1__42/OProp_A6LUT_SLICEM_I1_O JLUT5Xhzr< `\g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg00[35] Jnet (fo=1, routed)XhD< eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhCk?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzr> Jclock pessimismXh" c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh'; J arrival timeXh ?/ JXh4 JslackXh.=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuv>>}Ô<ߟ=n?<ߟ?//=K2=j=>B`?Z>&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__42/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__42/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+g?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXhK2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhÔ; J arrival timeXhq=?/ JXh4 JslackXh//=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C+'SFP_GEN[43].rx_data_ngccm_reg[43][65]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu>}@D >?=Nb?D?e1=-x1D=9=>G?Z> ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[43][65] Jnet (fo=1, routed)Xh9=] +'SFP_GEN[43].rx_data_ngccm_reg[43][65]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhoc?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][65]/C JFDCEXhzr> Jclock pessimismXh-x1t )%SFP_GEN[43].rx_data_ngccm_reg[43][65]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh@; J arrival timeXho?/ JXh4 JslackXhe1=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[43].rx_data_ngccm_reg[43][60]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuS>}y<[=]??}:=ر19H==>ˡ?Z>$&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[43][60] Jnet (fo=1, routed)Xh=] +'SFP_GEN[43].rx_data_ngccm_reg[43][60]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhlg?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh(?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][60]/C JFDCEXhzr> Jclock pessimismXhر1s )%SFP_GEN[43].rx_data_ngccm_reg[43][60]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhy; J arrival timeXhgf?/ JXh4 JslackXh}:=rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/Cb^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu>}oV[N=?o?:=4o=X9=>C ?Z>W-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnt[3] Jnet (fo=5, routed)Xh= gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_inv_i_1__43/I5 JXhzr fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_inv_i_1__43/OProp_B6LUT_SLICEL_I5_O JLUT6Xhzru< ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xhu< b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)XhVn?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXh4 `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_invHold_BFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXhx?/ JXh4 JslackXh:=>+'SFP_GEN[43].rx_data_ngccm_reg[43][49]/C0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsut>}d|Y,=n?|?ay;=X4==L=>B`?Z>T%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)x +'SFP_GEN[43].rx_data_ngccm_reg[43][49]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] Jnet (fo=1, routed)XhC =_ 1-SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[48]_i_1/I0 JXhzr 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[48]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh+g?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][49]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXhX4=x .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhd; J arrival timeXh/ݔ?/ JXh4 JslackXhay;=>+'SFP_GEN[43].rx_data_ngccm_reg[43][40]/C0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu|?>}V=J ???=CG=5^=>?Z>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)x +'SFP_GEN[43].rx_data_ngccm_reg[43][40]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[40]_i_1/I1 JXhzr 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_H6LUT_SLICEM_I1_O JLUT3Xhzr@=u 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xhgff?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][40]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh䥋?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXhCGx .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh?=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu>}i&;,= ׃?&?C=@?=T=>'1?Z>L7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__42/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__42/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh@? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhi; J arrival timeXh,?/ JXh4 JslackXhC=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][56]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuƇ@}A,A9@@A=А=3j@KQ>Q>x@M??t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhP?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][56]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh:?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][56]/C JFDCEXhzr> Jclock pessimismXhKQ>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][56]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh3j@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][62]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuƇ@}A,A9@@A=А=3j@KQ>Q>x@M??t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhP?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][62]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh:?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][62]/C JFDCEXhzr> Jclock pessimismXhKQ>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][62]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh3j@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][54]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu@}A,A9@@A=А=bj@KQ>Q>Qx@M??t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh+?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][54]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh:?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][54]/C JFDCEXhzr> Jclock pessimismXhKQ>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][54]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhbj@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][61]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu@}A,A9@@A=А=bj@KQ>Q>Qx@M??t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh+?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][61]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh:?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][61]/C JFDCEXhzr> Jclock pessimismXhKQ>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][61]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhbj@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][57]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuG@}Ao-A֣|9@֣@A=А=3'k@m1Q>Q>Nbx@M??t8?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhK?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][57]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][57]/C JFDCEXhzr> Jclock pessimismXhm1Q>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][57]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXho-A; J arrival timeXhD/ JXh4 JslackXh3'k@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuG@}Ao-A֣|9@֣@A=А=3'k@m1Q>Q>Nbx@M??t8?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhK?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][59]/C JFDCEXhzr> Jclock pessimismXhm1Q>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][59]Setup_BFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXho-A; J arrival timeXhD/ JXh4 JslackXh3'k@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][74]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuG@}Ao-A֣|9@֣@A=А=3'k@m1Q>Q>Nbx@M??t8?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhK?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][74]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][74]/C JFDCEXhzr> Jclock pessimismXhm1Q>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][74]Setup_CFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXho-A; J arrival timeXhD/ JXh4 JslackXh3'k@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][55]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu@}A-A֣|9@֣@A=А=yk@m1Q>Q> x@M??t8?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][55]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][55]/C JFDCEXhzr> Jclock pessimismXhm1Q>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][55]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh-A; J arrival timeXhj/ JXh4 JslackXhyk@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][58]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu@}A-A֣|9@֣@A=А=yk@m1Q>Q> x@M??t8?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][58]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][58]/C JFDCEXhzr> Jclock pessimismXhm1Q>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][58]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh-A; J arrival timeXhj/ JXh4 JslackXhyk@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][60]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu@}A-A֣|9@֣@A=А=yk@m1Q>Q> x@M??t8?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhk @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][60]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][60]/C JFDCEXhzr> Jclock pessimismXhm1Q>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][60]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh-A; J arrival timeXhj/ JXh4 JslackXhyk@L( !gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!)y@1y @9Ay@Iy @e G@hq} Z< wv?66$ rise - rise rise - rise  <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CGCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu >}\ܚ=??Z<o=v=>~*?->1L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gbtBank_Clk_gen[8].cnt_reg[8][7]_0[0] Jnet (fo=10, routed)Xh-= ~zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i[8]_i_1__2/I4 JXhzr }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i[8]_i_1__2/OProp_C6LUT_SLICEL_I4_O JLUT6Xhzru<m *&g_gbt_bank[3].gbtbank/i_gbt_bank_n_153 Jnet (fo=1, routed)Xho<y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)XhPw?X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C JFDCEXhzr> Jclock pessimismXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh\ܚ; J arrival timeXhR?/ JXh4 JslackXhZ< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[44].rx_data_ngccm_reg[44][39]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsudI>}鲠ƫB=D?ƫ?!=D=u>>V.?->QW?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[44][39] Jnet (fo=1, routed)Xhu>] +'SFP_GEN[44].rx_data_ngccm_reg[44][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[d{?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[44].rx_data_ngccm_reg[44][39]/C JFDCEXhzr> Jclock pessimismXhs )%SFP_GEN[44].rx_data_ngccm_reg[44][39]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh鲠; J arrival timeXh¥?/ JXh4 JslackXh!=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*&SFP_GEN[44].rx_data_ngccm_reg[44][1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuK>}鲠ƫB=D?ƫ?%*=D=>>V.?->QW?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=U rx_data[44][1] Jnet (fo=1, routed)Xh>\ *&SFP_GEN[44].rx_data_ngccm_reg[44][1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[d{?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT)\ *&SFP_GEN[44].rx_data_ngccm_reg[44][1]/C JFDCEXhzr> Jclock pessimismXhr ($SFP_GEN[44].rx_data_ngccm_reg[44][1]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh鲠; J arrival timeXh?/ JXh4 JslackXh%*=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu/>}\m竿EIW=v?m?G:=ϲ5`=T=>-2?->W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__43/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__43/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhϲ5 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh\; J arrival timeXh-?/ JXh4 JslackXhG:=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu>} Țm竿h,=?5?m?|C=SB=T=>1?->W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__43/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__43/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ~?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhSB g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh Ț; J arrival timeXh`?/ JXh4 JslackXh|C=`,(SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuT>}h3=/??E=_6o=1=>/?->33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)y ,(SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H=i &"SFP_GEN[44].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)XhC=_ 1-SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__37/I1 JXhzr 0,SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__37/OProp_C6LUT_SLICEM_I1_O JLUT4Xhzru<u 2.SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__37_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh |?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXh_6t *&SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_regHold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhE=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[44].rx_data_ngccm_reg[44][59]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuS>}%N=V??F=I59H==>1?->> W?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[44][59] Jnet (fo=1, routed)Xh=] +'SFP_GEN[44].rx_data_ngccm_reg[44][59]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)Xhc?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[44].rx_data_ngccm_reg[44][59]/C JFDCEXhzr> Jclock pessimismXhI5t )%SFP_GEN[44].rx_data_ngccm_reg[44][59]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh-?/ JXh4 JslackXhF=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[44].rx_data_ngccm_reg[44][52]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu">}aR=?5??OS=$5D=S=>1?->> W?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=V rx_data[44][52] Jnet (fo=1, routed)XhS=] +'SFP_GEN[44].rx_data_ngccm_reg[44][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ~?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)Xhc?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[44].rx_data_ngccm_reg[44][52]/C JFDCEXhzr> Jclock pessimismXh$5t )%SFP_GEN[44].rx_data_ngccm_reg[44][52]Hold_BFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh\?/ JXh4 JslackXhOS=]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu=`=}n𧦿;??T="[o=D=>*?->OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/ready_from_bitSlipCtrller_8 Jnet (fo=2, routed)Xht= b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__43/I2 JXhzr a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__43/OProp_E6LUT_SLICEL_I2_O JLUT3Xhzru< c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__43_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhw?X1Y9 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh43?X1Y9 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh"[ [Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_regHold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhn; J arrival timeXh?/ JXh4 JslackXhT=Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu>}ʗr|=Ƌ?r?YU=ޘ>=T=>,?->`P?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__43/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__43/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$y?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhޘ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhʗ; J arrival timeXhv?/ JXh4 JslackXhYU=!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu-@}Ao/AW%kCE>W%@W%@A=А= G@kCE>? k@~*?v???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh$> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/OProp_D6LUT_SLICEL_I2_O JLUT4Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 Jnet (fo=1, routed)Xh"> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 Jnet (fo=2, routed)Xh> > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXho/A; J arrival timeXhX9/ JXh4 JslackXh G@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu-@}Ao/AW%kCE>W%@W%@A=А= G@kCE>? k@~*?v???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh$> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/OProp_D6LUT_SLICEL_I2_O JLUT4Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 Jnet (fo=1, routed)Xh"> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 Jnet (fo=2, routed)Xh> > kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXho/A; J arrival timeXhX9/ JXh4 JslackXh G@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu䥧@}Ah2Ae;'Jh>W%@e;'@A=А=IU@kCE>jt?V@~*?v??G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL0[1]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL0[1] J GTHE3_CHANNELXhzrjt? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/D[18] Jnet (fo=6, routed)XhV@ eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+@X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]/C JFDCEXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]Setup_HFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhh2A; J arrival timeXh-/ JXh4 JslackXhIU@g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuYd@}A/A$7C>W%@$@A=А=e[@kCE>i?jd@~*?v?? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhgf> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhe[@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuK@}A&/A$7C>W%@$@A=А="\@kCE>i?X9d@~*?v?? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh&/A; J arrival timeXh/ JXh4 JslackXh"\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuٞ@}A/A$7C>W%@$@A=А=\@kCE>i?Sc@~*?v?? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh-> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXhB`/ JXh4 JslackXh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuٞ@}A/A$7C>W%@$@A=А=\@kCE>i?Sc@~*?v?? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh-> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh/A; J arrival timeXhB`/ JXh4 JslackXh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}A&/A$7C>W%@$@A=А=;9]@kCE>i?"c@~*?v?? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh(> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh&/A; J arrival timeXhG/ JXh4 JslackXh;9]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}A&/A$7C>W%@$@A=А=;9]@kCE>i?"c@~*?v?? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh(> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh&/A; J arrival timeXhG/ JXh4 JslackXh;9]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}Ao/AW%kCE>W%@W%@A=А=^@kCE>i?#a@~*?v???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh6@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_G6LUT_SLICEL_I0_O JLUT4Xhzrjt> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr-= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh# @X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhkCE>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXho/A; J arrival timeXh֣/ JXh4 JslackXh^@ ( !gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!)y@1y @9Ay@Iy @eFO@hq} {= vv?77( rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuX->}ɑ̜=أ?̜?{=Qpʡ=Q=>?Z> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_GFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__44/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__44/OProp_H6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhQp g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhɑ; J arrival timeXhE?/ JXh4 JslackXh{=eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[26]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuph>} Ap)F=a?p?g,=29H=v=>M?Z>!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[26]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[26] Jnet (fo=1, routed)Xhv= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhd?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]/C JFDCEXhzr> Jclock pessimismXh2 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh A; J arrival timeXho?/ JXh4 JslackXhg,=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu-2>}vRM=n?R?q=& ף==>B`?Z>Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xhw= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__44/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+g?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh& g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhv; J arrival timeXh:?/ JXh4 JslackXhq=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu&1>}ɑ̜=أ?̜?(=Qp-= =>?Z> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_GFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__44/OProp_H5LUT_SLICEL_I0_O JLUT3Xhzrw= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhQp g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhɑ; J arrival timeXhȖ?/ JXh4 JslackXh(=7g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu>}>c=??!=a2o=-=> ?Z>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__44/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzro< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡe?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh䥋?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXha2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh!=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[45].rx_data_ngccm_reg[45][42]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuv>}{1)\$o=8?)\?t)=29H="=>?Z>ˡ%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[45][42] Jnet (fo=1, routed)Xh"=] +'SFP_GEN[45].rx_data_ngccm_reg[45][42]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`e?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xhm?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][42]/C JFDCEXhzr> Jclock pessimismXh2s )%SFP_GEN[45].rx_data_ngccm_reg[45][42]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh{1; J arrival timeXh?/ JXh4 JslackXht)=6g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu@>}ę͉=%??/=]F==>]?Z>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)Xhw= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__44/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh]F g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhę; J arrival timeXh?/ JXh4 JslackXh/=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuS>}1B)\.ue=?)\? 0='2=/]=>Z?Z>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__44/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$f?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh'2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh1B; J arrival timeXh•?/ JXh4 JslackXh 0=rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/Cb^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuK7>}ٞ&C=?ٞ?H?=v= =>gf?Z>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/QProp_HFF2_SLICEL_C_Q JFDCEXhzfD= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnt[1] Jnet (fo=6, routed)XhP= gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_inv_i_1__45/I2 JXhzf fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_inv_i_1__45/OProp_A6LUT_SLICEM_I2_O JLUT6XhzrQ8= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)XhD< b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh'1h?X1Y9 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)XhZd?X1Y9 (CLOCK_ROOT) b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXh `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_invHold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh#ۙ?/ JXh4 JslackXhH?=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C+'SFP_GEN[45].rx_data_ngccm_reg[45][71]/D"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu433>}sגҝDё=]?ҝ? C=4D=I >>ˡ?Z>]"?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[45][71] Jnet (fo=1, routed)XhI >] +'SFP_GEN[45].rx_data_ngccm_reg[45][71]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhlg?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xh6^?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][71]/C JFDCEXhzr> Jclock pessimismXh4t )%SFP_GEN[45].rx_data_ngccm_reg[45][71]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhsג; J arrival timeXh?/ JXh4 JslackXh C=D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu@}A|,A.@@A=А=FO@P>>@OM?A?b8?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh|,A; J arrival timeXh/ JXh4 JslackXhFO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu@}A|,A.@@A=А=FO@P>>@OM?A?b8?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh|,A; J arrival timeXh/ JXh4 JslackXhFO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*@}A,A.@@A=А=ӨO@P>>rh@OM?A?b8?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh"/ JXh4 JslackXhӨO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*@}A,A.@@A=А=ӨO@P>>rh@OM?A?b8?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Setup_FFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh"/ JXh4 JslackXhӨO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*@}A,A.@@A=А=ӨO@P>>rh@OM?A?b8?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh"/ JXh4 JslackXhӨO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*@}A,A.@@A=А=CO@yP>>rh@OM?A?b8?F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh"/ JXh4 JslackXhCO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*@}A,A.@@A=А=CO@yP>>rh@OM?A?b8?F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh"/ JXh4 JslackXhCO@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuff@}A,A.@@A=А=)P@yP>>G@OM?A?b8?F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh^/ JXh4 JslackXh)P@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuff@}A,A.@@A=А=)P@yP>>G@OM?A?b8?F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh^/ JXh4 JslackXh)P@D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/CE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuff@}A,A.@@A=А=)P@yP>>G@OM?A?b8?F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh` @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/OProp_E6LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xht@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh^/ JXh4 JslackXh)P@ rxoutclk_out[0]_1rxoutclk_out[0]_1!)Ë>?1Ë>@9AË>?IË>@hq}?::   TTC_rxusrclk TTC_rxusrclk!)Ë>?1Ë>@9AË>?IË>@e>hq}&<ѣ><< rise - rise rise - rise  H c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[19]/C?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]/D"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuz>}iۿ꿭ƺr=V??&</9H==-2?g?lG?z?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[19]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=u 2.i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[19] Jnet (fo=1, routed)Xh=q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]/D JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)XhV?X3Y2 (CLOCK_ROOT) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[19]/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]/C JFDCEXhzr> Jclock pessimismXh/ =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhiۿ; J arrival timeXh?/ JXh4 JslackXh&<O d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[205]/C@}޿=V??-2?g?lG??e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[205]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=v 3/i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[205] Jnet (fo=1, routed)Xh>r @ Jclock pessimismXh/ >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[205]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh޿; J arrival timeXhS?/ JXh4 JslackXh}ۿQA=v?Q?/&=]QD=[=-2?j?lG? ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[220]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=v 3/i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[220] Jnet (fo=1, routed)Xh[=r @ Jclock pessimismXh]Q >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[220]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhۿ; J arrival timeXh?/ JXh4 JslackXh/&=P d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[240]/C@}1GۿvE={?v?;|'=Q9H=[=-2?i?lG??e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[240]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=v 3/i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[240] Jnet (fo=1, routed)Xh[=r @ Jclock pessimismXhQ >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[240]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh1Gۿ; J arrival timeXh?/ JXh4 JslackXh;|'= @}Ţv~=h??11=7~/%=>-2?h?lG?"?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) @ Jclock pessimismXh7~/ ]Yi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[212]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhŢ; J arrival timeXhA/ JXh4 JslackXh11=  ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[54]/C^Zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[19]/D"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZ(LUT6=1)bL Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2j5TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238nsuF>}I=??,1=/o=>-2?lg?lG?"?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[54]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= @ Jclock pessimismXh/ \Xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[19]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhI; J arrival timeXhA/ JXh4 JslackXh,1= }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register_reg[41]/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]/D"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZ(LUT3=1)j5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuϡE>}K߿M=m??s2=@/=j=-2?̡e?lG??e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR)  }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register_reg[41]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD= {wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register[41] Jnet (fo=2, routed)Xh㥛= ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData[22]_i_1/I0 JXhzr }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData[22]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrY= soi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/p_0_out[22] Jnet (fo=1, routed)Xho< }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]/D JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)Xhm?X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register_reg[41]/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]/C JFDREXhzr> Jclock pessimismXh@/ {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhK߿; J arrival timeXh?/ JXh4 JslackXhs2=[i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg[1]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg/D"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsu!>}޿_pn=|?_?dH3=OD=G=-2?l?lG?/?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg[1]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg_n_0_[1] Jnet (fo=6, routed)XhG= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg/D JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/rxusrclk2_in[0] Jnet (fo=1861, routed)Xh|?X3Y2 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg[1]/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/rxusrclk2_in[0] Jnet (fo=1861, routed)Xh_?X3Y2 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg/C JFDREXhzr> Jclock pessimismXhO i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_regHold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh޿; J arrival timeXhF?/ JXh4 JslackXhdH3= ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[64]/C^Zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[24]/D"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZ(LUT6=1)bL Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2j5TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238nsuG>}X=??i5=/o=$>-2?g?lG?C?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[64]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= @ Jclock pessimismXh/ \Xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[24]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhDA/ JXh4 JslackXhi5= F c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[92]/C?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]/D"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuC>} ߿v?k=V?v?G:=/9H=sh>-2?g?lG??e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[92]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=u 2.i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[92] Jnet (fo=1, routed)Xhsh>q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]/D JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)XhV?X3Y2 (CLOCK_ROOT) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[92]/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhv?X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]/C JFDCEXhzr> Jclock pessimismXh/ =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ߿; J arrival timeXh?/ JXh4 JslackXhG:=, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu~:@}G@@MjҤ=w@Mj@G@=А=>>)\>81@Mb?l@V?" @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i Jnet (fo=731, routed)Xh81@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)XhMj@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXhV/ JXh4 JslackXh>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu~:@}G@@MjҤ=w@Mj@G@=А=>>)\>81@Mb?l@V?" @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i Jnet (fo=731, routed)Xh81@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)XhMj@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]Setup_CFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXhV/ JXh4 JslackXh>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu~:@}G@@MjҤ=w@Mj@G@=А=>>)\>81@Mb?l@V?" @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i Jnet (fo=731, routed)Xh81@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)XhMj@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]Setup_BFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXhV/ JXh4 JslackXh>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu~:@}G@@MjҤ=w@Mj@G@=А=>>)\>81@Mb?l@V?" @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i Jnet (fo=731, routed)Xh81@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)XhMj@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]Setup_AFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXhV/ JXh4 JslackXh>( \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C|i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu5^:@}G@@-jĠ=w@-j@G@=А=>B>)\>sh1@Mb?l@V?  @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/reset_i Jnet (fo=731, routed)Xhsh1@ |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out Jnet (fo=1861, routed)Xh-j@X3Y2 (CLOCK_ROOT) |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]/C JFDREXhzr> Jclock pessimismXhB>@ Jclock uncertaintyXh ~zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu5^:@}G@@-jĠ=w@-j@G@=А=>B>)\>sh1@Mb?l@V?  @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/reset_i Jnet (fo=731, routed)Xhsh1@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out Jnet (fo=1861, routed)Xh-j@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]/C JFDREXhzr> Jclock pessimismXhB>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]Setup_CFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu5^:@}G@@-jĠ=w@-j@G@=А=>B>)\>sh1@Mb?l@V?  @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/reset_i Jnet (fo=731, routed)Xhsh1@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out Jnet (fo=1861, routed)Xh-j@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]/C JFDREXhzr> Jclock pessimismXhB>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]Setup_BFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu69@}G@<@iQ=w@i@G@=А= &>>)\>t0@Mb?l@V? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/reset_i Jnet (fo=731, routed)Xht0@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)Xhi@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]Setup_EFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh<@; J arrival timeXht/ JXh4 JslackXh &>- \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu69@}G@<@iQ=w@i@G@=А= &>>)\>t0@Mb?l@V? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/reset_i Jnet (fo=731, routed)Xht0@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)Xhi@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]Setup_EFF2_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh<@; J arrival timeXht/ JXh4 JslackXh &>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]/R"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu69@}G@<@iQ=w@i@G@=А= &>>)\>t0@Mb?l@V? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/reset_i Jnet (fo=731, routed)Xht0@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)Xhi@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]Setup_FFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh<@; J arrival timeXht/ JXh4 JslackXh &>  fabric_clk_in fabric_clk_in!)Ë>(@1Ë>8@9AË>(@IË>8@eCAhq}?;=@==B rise - rise rise - rise  :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuϡE>}`2QH`=(@QH@?;=q3̾%=>?5^Z??Z?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[9] Jnet (fo=52, routed)Xhx=l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[106]_i_1__0/I2 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[106]_i_1__0/OProp_H6LUT_SLICEL_I2_O JLUT6Xhzru< =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[96]_2[10] Jnet (fo=1, routed)Xho<l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhh?X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhm?X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]/C JFDREXhzr> Jclock pessimismXhq3̾ 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh`2; J arrival timeXhO5@/ JXh4 JslackXh?;=4 :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZj7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu >}90AH3=q=*@AH@;==پD=9=?|_??X9?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[20]_11[2] Jnet (fo=56, routed)Xh9=k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh ?X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh?X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]/C JFDREXhzr> Jclock pessimismXhپ 73i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]Hold_BFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh90; J arrival timeXh3@/ JXh4 JslackXh;==895i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuxJ>}d2ףH=G)@ףH@]O='̾==?[???h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[0] Jnet (fo=66, routed)XhE=k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[70]_i_1__0/I1 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[70]_i_1__0/OProp_B6LUT_SLICEL_I1_O JLUT6XhzrQ8= =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[58]_0[12] Jnet (fo=1, routed)Xhu<k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh?5?X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhD?X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]/C JFDREXhzr> Jclock pessimismXh'̾ 73i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhd2; J arrival timeXh5@/ JXh4 JslackXh]O=B95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuG>}2rH7=G)@rH@QO=B*̾==?[???h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[0] Jnet (fo=66, routed)Xh-=k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[64]_i_1__0/I4 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[64]_i_1__0/OProp_G6LUT_SLICEL_I4_O JLUT6XhzrQ8= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[58]_0[6] Jnet (fo=1, routed)XhA`e<k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh?5?X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh(?X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]/C JFDREXhzr> Jclock pessimismXhB*̾ 73i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh2; J arrival timeXh5@/ JXh4 JslackXhQO=B #i_tcds2_if/ttc_rx_err_cnt_reg/C#i_tcds2_if/ttc_rx_err_cnt_reg/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu =} Jclock pessimismXhgk !i_tcds2_if/ttc_rx_err_cnt_regHold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh Jclock pessimismXh2쾐v ,(i_tcds2_if/prbs_checker/data_notzero_regHold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh-; J arrival timeXhG1@/ JXh4 JslackXh@/]=95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuM>}L2Hö=G)@H@ndd=B*̾o=I >?[??k?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[0] Jnet (fo=66, routed)Xh=l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[119]_i_1__0/I1 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[119]_i_1__0/OProp_D6LUT_SLICEL_I1_O JLUT6Xhzru< =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[4] Jnet (fo=1, routed)Xho<l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh?5?X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhI?X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]/C JFDREXhzr> Jclock pessimismXhB*̾ 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhL2; J arrival timeXh$6@/ JXh4 JslackXhndd=B#i_tcds2_if/BC0_onTime_cnt_reg/C#i_tcds2_if/BC0_onTime_cnt_reg/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT5=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu=}&?أ;!"@?@_e=l羥=T=?GA??+g?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)p #i_tcds2_if/BC0_onTime_cnt_reg/QProp_BFF_SLICEM_C_Q JFDREXhzr9H= |xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/BC0_early_cnt_reg[3] Jnet (fo=2, routed)XhP= }yi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/BC0_onTime_cnt_i_1/I4 JXhzr |xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/BC0_onTime_cnt_i_1/OProp_B6LUT_SLICEM_I4_O JLUT5Xhzro<k ($i_tcds2_if/cmp_lpgbtfpga_uplink_n_45 Jnet (fo=1, routed)Xhu<U #i_tcds2_if/BC0_onTime_cnt_reg/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף<u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh%?X3Y3 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #i_tcds2_if/BC0_onTime_cnt_reg/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr=u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh"?X3Y3 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #i_tcds2_if/BC0_onTime_cnt_reg/C JFDREXhzr> Jclock pessimismXhl羐k !i_tcds2_if/BC0_onTime_cnt_regHold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh&; J arrival timeXh-*@/ JXh4 JslackXh_e=i_tcds2_if/bcnt_reg[5]/Ci_tcds2_if/bcnt_reg[5]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu=}&b@֣;H"@b@@[`e=y澥=T=?J B??g?h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)i i_tcds2_if/bcnt_reg[5]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= wsi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt_reg[11][5] Jnet (fo=8, routed)XhP= vri_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[5]_i_1/I5 JXhzr uqi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[5]_i_1/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzro<[ i_tcds2_if/p_0_in[5] Jnet (fo=1, routed)Xhu<N i_tcds2_if/bcnt_reg[5]/D JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף<u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xhrh?X3Y3 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i_tcds2_if/bcnt_reg[5]/C JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr=u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)XhZd?X3Y3 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i_tcds2_if/bcnt_reg[5]/C JFDCEXhzr> Jclock pessimismXhy澐d i_tcds2_if/bcnt_reg[5]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh&; J arrival timeXh5^*@/ JXh4 JslackXh[`e=:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu$N>}?2'1H=(@'1H@h=_7̾==?5^Z???h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[9] Jnet (fo=52, routed)Xh =l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[130]_i_1__0/I4 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[130]_i_1__0/OProp_B6LUT_SLICEL_I4_O JLUT6XhzrY= >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[15] Jnet (fo=1, routed)Xhu<l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhʡ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhh?X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh}??L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh?X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/C JFDREXhzr> Jclock pessimismXh_7̾ 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh?2; J arrival timeXhU5@/ JXh4 JslackXhh=4Z!95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/CD@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(CARRY8=9 LUT5=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsu)l@}AVoAA@I@@A=А=CA!?K?K7@^?O@I?w@h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) * 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] Jnet (fo=1, routed)Xh?5? RNi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/I3 JXhzr QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/OProp_A6LUT_SLICEM_I3_O JLUT6Xhzrx> SOi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 Jnet (fo=1, routed)Xh XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/S[0] JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8Xhzr? WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5]Prop_CARRY8_SLICEM_CI_CO[5] JCARRY8XhzrC >q .*i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] Jnet (fo=3, routed)XhW9? QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/I1 JXhzr PLi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/OProp_G6LUT_SLICEL_I1_O JLUT5Xhzre;_>n +'i_tcds2_if/prbs_checker/prbs_lock_state Jnet (fo=2, routed)Xhh>v D@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh -r@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhTU@X3Y3 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C JFDREXhzr> Jclock pessimismXh!?@ Jclock uncertaintyXh A=i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhVoA; J arrival timeXh'\// JXh4 JslackXhCAZ!95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/CD@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(CARRY8=9 LUT5=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsu)l@}AVoAA@I@@A=А=CA!?K?K7@^?O@I?w@h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) * 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] Jnet (fo=1, routed)Xh?5? RNi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/I3 JXhzr QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/OProp_A6LUT_SLICEM_I3_O JLUT6Xhzrx> SOi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 Jnet (fo=1, routed)Xh XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/S[0] JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8Xhzr? WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5]Prop_CARRY8_SLICEM_CI_CO[5] JCARRY8XhzrC >q .*i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] Jnet (fo=3, routed)XhW9? QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/I1 JXhzr PLi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/OProp_G6LUT_SLICEL_I1_O JLUT5Xhzre;_>n +'i_tcds2_if/prbs_checker/prbs_lock_state Jnet (fo=2, routed)Xhh>v D@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE JFDSEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh -r@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhTU@X3Y3 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C JFDSEXhzr> Jclock pessimismXh!?@ Jclock uncertaintyXh A=i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]Setup_GFF2_SLICEL_C_CE JFDSEXhim/ JXh< J required timeXhVoA; J arrival timeXh'\// JXh4 JslackXhCA6!95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/CC?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(CARRY8=9 LUT4=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuy?m@}A5BA@I@@A=А=ⰨA!?Y?R@^?O@I?w@h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) * 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] Jnet (fo=1, routed)Xh?5? RNi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/I3 JXhzr QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/OProp_A6LUT_SLICEM_I3_O JLUT6Xhzrx> SOi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 Jnet (fo=1, routed)Xh XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/S[0] JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8Xhzr? WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzrB`< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5]Prop_CARRY8_SLICEM_CI_CO[5] JCARRY8XhzrC >d !i_tcds2_if/prbs_checker/error Jnet (fo=3, routed)XhjT?r D@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state[1]_i_3/I2 JXhzr C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state[1]_i_3/OProp_G5LUT_SLICEL_I2_O JLUT4Xhzr>t 1-i_tcds2_if/prbs_checker/prbs_lock_state__1[1] Jnet (fo=1, routed)XhD=u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/D JFDSEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh -r@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhTU@X3Y3 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C JFDSEXhzr> Jclock pessimismXh!?@ Jclock uncertaintyXh A=i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]Setup_GFF2_SLICEL_C_D JFDSEXh=/ JXh< J required timeXh5B; J arrival timeXht// JXh4 JslackXhⰨA6!95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/CC?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(CARRY8=9 LUT4=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsum@}A4BA@I@@A=А=A!?̼?S@^?O@I?w@h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) * 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] Jnet (fo=1, routed)Xh?5? RNi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/I3 JXhzr QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/OProp_A6LUT_SLICEM_I3_O JLUT6Xhzrx> SOi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 Jnet (fo=1, routed)Xh XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/S[0] JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8Xhzf? WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CI JXhzf YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CI JXhzf YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CI JXhzf YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CI JXhzf YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CI JXhzf YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CI JXhzf YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CI JXhzf XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8XhzfB`< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CI JXhzf XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5]Prop_CARRY8_SLICEM_CI_CO[5] JCARRY8XhzfC >d !i_tcds2_if/prbs_checker/error Jnet (fo=3, routed)Xh}?U?r D@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state[0]_i_1/I1 JXhzf C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state[0]_i_1/OProp_H5LUT_SLICEL_I1_O JLUT4Xhzrˡ>t 1-i_tcds2_if/prbs_checker/prbs_lock_state__1[0] Jnet (fo=1, routed)Xh~j<=u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh -r@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhTU@X3Y3 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C JFDREXhzr> Jclock pessimismXh!?@ Jclock uncertaintyXh A=i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]Setup_HFF2_SLICEL_C_D JFDREXho=/ JXh< J required timeXh4B; J arrival timeXhl// JXh4 JslackXhA95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[6]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT4=1 LUT5=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuY@}AO#B7!Tj@7@A=А=A"?XY?C#@^?i@I?@h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[6]/QProp_CFF_SLICEL_C_Q JFDREXhzrO > <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[5] Jnet (fo=53, routed)Xh-?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_3/I0 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_3/OProp_F5LUT_SLICEL_I0_O JLUT4XhzrI> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_3_n_0 Jnet (fo=18, routed)Xh`P?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_2__0/I0 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT5Xhzre;_> ?;i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_2__0_n_0 Jnet (fo=1, routed)Xhף>l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_1__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_1__0/OProp_B6LUT_SLICEL_I5_O JLUT6XhzrA`> >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[14] Jnet (fo=1, routed)Xh+=l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhnr@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[6]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhT@X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]/C JFDREXhzr> Jclock pessimismXh"?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]Setup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXhO#B; J arrival timeXh*/ JXh4 JslackXhA595i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[7]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1 LUT6=2)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsu(\W@}A[BC.#@C@A=А=A|!?+V?^!@^?@I?p= @h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[7]/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[6] Jnet (fo=50, routed)Xhff?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[221]_i_4/I1 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[221]_i_4/OProp_G6LUT_SLICEL_I1_O JLUT3Xhzrjt> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[221]_i_4_n_0 Jnet (fo=9, routed)XhuX?k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[0]_i_2__0/I5 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[0]_i_2__0/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrMb> >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[229]__0[5] Jnet (fo=1, routed)Xh&>k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[0]_i_1__0/I5 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[0]_i_1__0/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrFs>u 2.i_tcds2_if/prbs_checker/cmp_prbs_gen/p_1_in[0] Jnet (fo=1, routed)Xh*\=k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhr@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[7]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhNbX@X3Y3 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]/C JFDREXhzr> Jclock pessimismXh|!?@ Jclock uncertaintyXh 73i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]Setup_HFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh[B; J arrival timeXh$*/ JXh4 JslackXhA2:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[18]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]/D"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT5=2)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuT@}A8B$G@$@A=А=Ak!?33? =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[17] Jnet (fo=59, routed)XhM?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_2__0/I0 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT5Xhzre;_> ?;i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_2__0_n_0 Jnet (fo=4, routed)Xh?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_1__0/I3 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_1__0/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrA`> >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[172]_8[18] Jnet (fo=1, routed)Xhi>l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhr@X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[18]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh$V@X3Y3 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]/C JFDREXhzr> Jclock pessimismXhk!?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh8B; J arrival timeXhx)/ JXh4 JslackXhA;. i_tcds2_if/prbs_rst_reg[3]/C2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]/R"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuG@}AA^]_@^@A=А=߫Ae!?ˡE>S;@^?*@I?+@h(rising edge-triggered cell FDPE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)n i_tcds2_if/prbs_rst_reg[3]/QProp_FFF2_SLICEL_C_Q JFDPEXhzrO >e "ctrl_regs_inst/count_reg[0][0] Jnet (fo=1, routed)Xh +?i ;7ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/I0 JXhzr :6ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT3XhzrGa=u 0,i_tcds2_if/prbs_chk_unlock_cnt/prbschk_reset Jnet (fo=293, routed)Xhu@d 2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]/R JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף>u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)XhYds@X3Y3 (CLOCK_ROOT)R i_tcds2_if/prbs_rst_reg[3]/C JFDPEXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> &"i_tcds2_if/prbs_chk_unlock_cnt/CLK Jnet (fo=792, routed)XhOU@X3Y3 (CLOCK_ROOT)d 2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]/C JFDREXhzr> Jclock pessimismXhe!?@ Jclock uncertaintyXh{ 0,i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhA; J arrival timeXh4^&/ JXh4 JslackXh߫A. i_tcds2_if/prbs_rst_reg[3]/C2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]/R"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuG@}AA^]_@^@A=А=߫Ae!?ˡE>S;@^?*@I?+@h(rising edge-triggered cell FDPE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)n i_tcds2_if/prbs_rst_reg[3]/QProp_FFF2_SLICEL_C_Q JFDPEXhzrO >e "ctrl_regs_inst/count_reg[0][0] Jnet (fo=1, routed)Xh +?i ;7ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/I0 JXhzr :6ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT3XhzrGa=u 0,i_tcds2_if/prbs_chk_unlock_cnt/prbschk_reset Jnet (fo=293, routed)Xhu@d 2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]/R JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף>u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)XhYds@X3Y3 (CLOCK_ROOT)R i_tcds2_if/prbs_rst_reg[3]/C JFDPEXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> &"i_tcds2_if/prbs_chk_unlock_cnt/CLK Jnet (fo=792, routed)XhOU@X3Y3 (CLOCK_ROOT)d 2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]/C JFDREXhzr> Jclock pessimismXhe!?@ Jclock uncertaintyXh{ 0,i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]Setup_CFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhA; J arrival timeXh4^&/ JXh4 JslackXh߫A. i_tcds2_if/prbs_rst_reg[3]/C2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]/R"$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X54Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuG@}AA^]_@^@A=А=߫Ae!?ˡE>S;@^?*@I?+@h(rising edge-triggered cell FDPE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)n i_tcds2_if/prbs_rst_reg[3]/QProp_FFF2_SLICEL_C_Q JFDPEXhzrO >e "ctrl_regs_inst/count_reg[0][0] Jnet (fo=1, routed)Xh +?i ;7ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/I0 JXhzr :6ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT3XhzrGa=u 0,i_tcds2_if/prbs_chk_unlock_cnt/prbschk_reset Jnet (fo=293, routed)Xhu@d 2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]/R JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)XhQH@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף>u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)XhYds@X3Y3 (CLOCK_ROOT)R i_tcds2_if/prbs_rst_reg[3]/C JFDPEXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh5@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> &"i_tcds2_if/prbs_chk_unlock_cnt/CLK Jnet (fo=792, routed)XhOU@X3Y3 (CLOCK_ROOT)d 2.i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]/C JFDREXhzr> Jclock pessimismXhe!?@ Jclock uncertaintyXh{ 0,i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]Setup_BFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhA; J arrival timeXh4^&/ JXh4 JslackXh߫A CLKFBOUTCLKFBOUT!Ë>@)yuȶ2@1Ë>8@9Ë>@Ayuȶ2@IË>8@hq}A>> fabric_clk_dcmfabric_clk_dcm!)Ë>(@1Ë>8@9AË>(@IË>8@hq}A??A tx_wordclk_dcmtx_wordclk_dcm!)y@1y @9Ay@Iy @hq}^@@@> clk125clk125!)@1@9A@I@eW@hq}=lC@AA rise - rise rise - rise  W ($i_AXI4_to_ipbus/length_cntr_reg[0]/C($i_AXI4_to_ipbus/length_cntr_reg[4]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT6=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsuv>>}`x=M??=B  ף==v>t?L7>O?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR)v ($i_AXI4_to_ipbus/length_cntr_reg[0]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=n +'i_AXI4_to_ipbus/length_cntr_reg_n_0_[0] Jnet (fo=9, routed)XhQ=W )%i_AXI4_to_ipbus/length_cntr[4]_i_1/I1 JXhzrx ($i_AXI4_to_ipbus/length_cntr[4]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT6Xhzr<e "i_AXI4_to_ipbus/length_cntr[4] Jnet (fo=1, routed)Xho<Z ($i_AXI4_to_ipbus/length_cntr_reg[4]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)XhM?X2Y4 (CLOCK_ROOT)Z ($i_AXI4_to_ipbus/length_cntr_reg[0]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT)Z ($i_AXI4_to_ipbus/length_cntr_reg[4]/C JFDREXhzr> Jclock pessimismXhB p &"i_AXI4_to_ipbus/length_cntr_reg[4]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh`; J arrival timeXh?/ JXh4 JslackXh= Ti_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT2=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}WZ>I ??`=Gaʡ=/>v>33?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_in_bin[6] Jnet (fo=6, routed)Xh > i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff[5]_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff[5]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT2Xhzr< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/gray_enc[5] Jnet (fo=1, routed)XhA`e< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/rd_clk Jnet (fo=930, routed)XhI ?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]/C JFDREXhzr> Jclock pessimismXhGa i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhW; J arrival timeXhJ ?/ JXh4 JslackXh`= c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/CGCi_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg/S""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuSc>}+ǿhͿ{?5><߯?h? #=Ga9H=&1>v>%?L7>C?_(rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzr9H= ?;i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_any_sync Jnet (fo=11, routed)Xh&1>y GCi_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg/S JFDSEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=930, routed)Xh<߯?X2Y4 (CLOCK_ROOT) c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C JFDPEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xhh?X2Y4 (CLOCK_ROOT)y GCi_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg/C JFDSEXhzr> Jclock pessimismXhGa EAi_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_regHold_DFF2_SLICEL_C_S JFDSEXh ף;/ JXh< J required timeXh+ǿ; J arrival timeXhI?/ JXh4 JslackXh #= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[2][7]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsudI>}4a=Т?a?+=U D=u>v>?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[2][7]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/D[7] Jnet (fo=6, routed)Xhu> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk Jnet (fo=930, routed)XhТ?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[2][7]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/rd_clk Jnet (fo=930, routed)Xha?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]/C JFDREXhzr> Jclock pessimismXhU  i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh4; J arrival timeXh2?/ JXh4 JslackXh+=Ui_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT2=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsuo>}WZ>I ??Q8=Ga-=V->v>33?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_in_bin[6] Jnet (fo=6, routed)Xh > i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff[6]_i_1/I1 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff[6]_i_1/OProp_G5LUT_SLICEL_I1_O JLUT2Xhzr= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/gray_enc[6] Jnet (fo=1, routed)XhD< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/rd_clk Jnet (fo=930, routed)XhI ?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]/C JFDREXhzr> Jclock pessimismXhGa i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]Hold_GFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhW; J arrival timeXh?/ JXh4 JslackXhQ8=i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[2][1]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsul>}d k`>\J@ k@>=4*lT>"y>ff&? @z4?S=@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[2][1]/QProp_BFF2_SLICEL_C_Q JFDREXhzr= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff[2][1] Jnet (fo=2, routed)Xh@5^> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_out_bin[1]_INST_0/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_out_bin[1]_INST_0/OProp_C5LUT_SLICEM_I0_O JLUT3Xhzr1= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/D[1] Jnet (fo=1, routed)Xh/< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk Jnet (fo=930, routed)Xh\J@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[2][1]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/wr_clk Jnet (fo=930, routed)Xh k@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]/C JFDREXhzr> Jclock pessimismXh4*l i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]Hold_CFF2_SLICEM_C_D JFDREXh>/ JXh< J required timeXhd; J arrival timeXh|g@/ JXh4 JslackXh>=i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT6=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}e;v>??%@=GaF=*\>v>}??L7>̜?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/Q[0] Jnet (fo=12, routed)Xh= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/gen_pf_ic_rc.ram_empty_i_i_1/I1 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/gen_pf_ic_rc.ram_empty_i_i_1/OProp_C6LUT_SLICEL_I1_O JLUT6Xhzr)\= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/ram_empty_i0 Jnet (fo=1, routed)Xho< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/D JFDSEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_clk Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_clk Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/C JFDSEXhzr> Jclock pessimismXhGa i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_regHold_CFF_SLICEL_C_D JFDSEXhA`e=/ JXh< J required timeXhe;; J arrival timeXh~??/ JXh4 JslackXh%@=  '#i_AXI4_to_ipbus/i_r_FIFO/a_reg[3]/C+'i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ (SRL16E=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsuth>}e;K7>&??@H=Gav=R>v>M?L7>̜?_(rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR)t '#i_AXI4_to_ipbus/i_r_FIFO/a_reg[3]/QProp_CFF_SLICEM_C_Q JFDSEXhzrD=c i_AXI4_to_ipbus/i_r_FIFO/A3 Jnet (fo=38, routed)XhF>d 62i_AXI4_to_ipbus/i_r_FIFO/g_FIFO[32].SRL16E_inst/A3 JXhzr 51i_AXI4_to_ipbus/i_r_FIFO/g_FIFO[32].SRL16E_inst/QProp_A6LUT_SLICEM_A3_Q JSRL16EXhzr<j '#i_AXI4_to_ipbus/i_r_FIFO/dout_i[32] Jnet (fo=1, routed)XhD<] +'i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr} $ i_AXI4_to_ipbus/i_r_FIFO/CLKFBIN Jnet (fo=930, routed)Xh&?X2Y4 (CLOCK_ROOT)Y '#i_AXI4_to_ipbus/i_r_FIFO/a_reg[3]/C JFDSEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr} $ i_AXI4_to_ipbus/i_r_FIFO/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT)] +'i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]/C JFDREXhzr> Jclock pessimismXhGas )%i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhe;; J arrival timeXh?/ JXh4 JslackXh@H=&i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[3]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT5=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsuG=}1A ף;X9?A?@H="[o=j<=v>B`?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR)  i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[3]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/Q[3] Jnet (fo=6, routed)XhC = i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[5]_i_1__3/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[5]_i_1__3/OProp_A6LUT_SLICEL_I0_O JLUT5Xhzru< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[5]_i_1__3_n_0 Jnet (fo=1, routed)XhD< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/rd_clk Jnet (fo=930, routed)XhX9?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[3]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/rd_clk Jnet (fo=930, routed)XhA?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]/C JFDREXhzr> Jclock pessimismXh"[ i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh1; J arrival timeXhM?/ JXh4 JslackXh@H=i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT5=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsun>}<߿@~=?<߿?K=8=9H=v>}??L7>h?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]_0[0] Jnet (fo=12, routed)XhP= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[1]_i_1__2/I1 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[1]_i_1__2/OProp_F6LUT_SLICEL_I1_O JLUT5XhzrQ8= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[1]_i_1__2_n_0 Jnet (fo=1, routed)XhD< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_clk Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/rd_clk Jnet (fo=930, routed)Xh<߿?X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]/C JFDREXhzr> Jclock pessimismXh8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhff?/ JXh4 JslackXhK= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2_reg[1]/Ceai_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(BUFGCE=1 LUT6=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu罹@}A 1A14K߾sha@14@AY=А==W@>F>l@z4?I4@ff&?n @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2_reg[1]/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1] Jnet (fo=1273, routed)Xhr@ i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1]_BUFG_inst/I JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1]_BUFG_inst/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= {wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer/axi_c2c_link_status_out Jnet (fo=166521, routed)XhI@ i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer/resetOnEven_gen.rst_rstoneven_s_i_1/I1 JXhzr i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer/resetOnEven_gen.rst_rstoneven_s_i_1/OProp_B6LUT_SLICEL_I1_O JLUT6Xhzr!r> gci_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer_n_0 Jnet (fo=1, routed)Xh+= eai_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/m_aclk Jnet (fo=930, routed)Xhsha@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2_reg[1]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr GCi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/CLKFBIN Jnet (fo=930, routed)Xh14@X2Y4 (CLOCK_ROOT) eai_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXhY c_i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_regSetup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXh 1A; J arrival timeXh / JXh4 JslackXhW@  ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C:6i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg/S""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@8.000ns - clk125 rise@0.000nsu~@}A4AW}A`>vN@W@AY=А==W@ph=V>J @z4?X!@ff&?V.@_(rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzrV>y 62i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_sync Jnet (fo=7, routed)XhJ @l :6i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg/S JFDSEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=930, routed)XhvN@X2Y4 (CLOCK_ROOT) ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)XhW@X2Y4 (CLOCK_ROOT)l :6i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg/C JFDSEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY 84i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_regSetup_HFF2_SLICEL_C_S JFDSEXh\½/ JXh< J required timeXh4A; J arrival timeXh_/ JXh4 JslackXhW@f51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsurh@}A1y*AJx-b@J@AY=А==E_@Jm>h-?V=@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)XhA`e? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[1] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXhO/ JXh4 JslackXhE_@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsuObh@}A1y*AJx-b@J@AY=А==fU_@Jm>h-?<@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)Xhe? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXhG/ JXh4 JslackXhfU_@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsu h@}A1y*AJx-b@J@AY=А==_@Jm>h-?j<@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)Xhd? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[3] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXh&/ JXh4 JslackXh_@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsuwg@}A1y*AJx-b@J@AY=А===_@Jm>h-?Z<@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)Xh\b? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[2] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXh/ JXh4 JslackXh=_@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsunc@}A1y*AJx-b@J@AY=А==Fd@Jm>h-?7@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)Xh;O? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[5] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXh/ JXh4 JslackXhFd@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsub@}A1y*AJx-b@J@AY=А==d@Jm>h-?l7@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)XhN? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[6] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXh~/ JXh4 JslackXhd@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsub@}A1y*AJx-b@J@AY=А==2d@Jm>h-?)\7@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)XhN? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[7] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXhv/ JXh4 JslackXh2d@Ef51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4]""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1 LUT4=2)j)clk125 rise@8.000ns - clk125 rise@0.000nsu#a@}A1y*AJx-b@J@AY=А==e@Jm>h-?v6@z4?V5@ff&?K7!@_(rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})c(rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/QProp_BFF_SLICEM_C_Q JFDCEXhzrV>q -)i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] Jnet (fo=69, routed)XhF3?a 3/i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/I3 JXhzr 2.i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/OProp_C6LUT_SLICEL_I3_O JLUT4XhzrX9= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid Jnet (fo=1, routed)Xh ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_C5LUT_SLICEM_I0_O JLUT4XhzrC> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=40, routed)Xh K? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] JRAMB36E2XhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrt i_AXI4_to_ipbus/CLKFBIN Jnet (fo=930, routed)Xh-b@X2Y4 (CLOCK_ROOT)g 51i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C JFDCEXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=930, routed)XhJ@X2Y4 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhJm>@ Jclock uncertaintyXhY i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[4] JRAMB36E2Xhsh1/ JXh< J required timeXh1y*A; J arrival timeXh/ JXh4 JslackXhe@E clk250clk250!)?1@9A?I@eQ'>hq}t=$?pBB rise - rise rise - rise  i 51g_clock_rate_din[41].i_rate_ngccm_status0/q_reg/C?;g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsuxi>}~D>??t=@D=Q8>>?">D?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) 51g_clock_rate_din[41].i_rate_ngccm_status0/q_reg/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=v 2.g_clock_rate_din[41].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)XhQ8>q ?;g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[41].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[41].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[41].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]/C JFDREXhzr> Jclock pessimismXh@ <8g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]Hold_EFF_SLICEL_C_CE JFDREXh/ JXh< J required timeXh~; J arrival timeXh?/ JXh4 JslackXht=bY B>stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/reset_r_reg[3]/CEAstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsuPz>}̡0>Ƌ?? 0=@A`='1>>&?">IL?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) B>stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/reset_r_reg[3]/QProp_GFF_SLICEM_C_Q JFDREXhzrD={ 84stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/p_9_in Jnet (fo=2, routed)XhF=t FBstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst[3]_i_1/I1 JXhzr EAstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst[3]_i_1/OProp_F5LUT_SLICEM_I1_O JLUT3Xhzro= GCstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst[3]_i_1_n_0 Jnet (fo=1, routed)XhA`e<w EAstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 84stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)XhƋ?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]t B>stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/reset_r_reg[3]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 84stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]w EAstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]/C JFDREXhzr> Jclock pessimismXh@ C?stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]Hold_FFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXh̡; J arrival timeXh"?/ JXh4 JslackXh 0= JFg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK95g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsu>}p=>C??D=@/=X9>>ˡE?">t?e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) LHg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/P[33]!Prop_DSP_OUTPUT_DSP48E2_CLK_P[33] J DSP_OUTPUTXhzr/=r /+g_clock_rate_din[28].i_rate_test_comm/P[33] Jnet (fo=1, routed)XhX9>k 95g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr :6g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/CLK Jnet (fo=17693, routed)XhC?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] JFg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 0,g_clock_rate_din[28].i_rate_test_comm/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]k 95g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]/C JFDREXhzr> Jclock pessimismXh@ 73g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhA?/ JXh4 JslackXhD= mistat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C=9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT2=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu;^:>}y=Zd??F=,v=E=>TE?">Il?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) mistat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD=~ ;7stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_sync_1 Jnet (fo=2, routed)XhP=l >:stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d[1]_i_1/I1 JXhzr =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d[1]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT2XhzrQ8= =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/p_3_out[1] Jnet (fo=1, routed)Xhu<o =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr _[stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/dest_clk Jnet (fo=17693, routed)XhZd?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] mistat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]o =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]/C JFDREXhzr> Jclock pessimismXh, ;7stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhy; J arrival timeXh"?/ JXh4 JslackXhF= %!stat_regs_inst/addr_cntr_reg[7]/C*&stat_regs_inst/ram_addra_cntr_reg[7]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsuX9>}pL7Z=!?L7?JM=Ͻ9H=+>>z?">5?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR)r %!stat_regs_inst/addr_cntr_reg[7]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=g #stat_regs_inst/addr_cntr_reg[7] Jnet (fo=20, routed)Xh+>\ *&stat_regs_inst/ram_addra_cntr_reg[7]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17693, routed)Xh!?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]W %!stat_regs_inst/addr_cntr_reg[7]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17693, routed)XhL7?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]\ *&stat_regs_inst/ram_addra_cntr_reg[7]/C JFDREXhzr> Jclock pessimismXhϽs ($stat_regs_inst/ram_addra_cntr_reg[7]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhp; J arrival timeXh#ۙ?/ JXh4 JslackXhJM=u C?stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg[0]/CFBstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu@>}8󫿍ȓ=~??S=={=>D?">Ck?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) C?stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg[0]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD= FBstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg_n_0_[0] Jnet (fo=2, routed)XhP=u GCstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst[0]_i_1/I1 JXhzr FBstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst[0]_i_1/OProp_C5LUT_SLICEL_I1_O JLUT3XhzrGa= HDstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst[0]_i_1_n_0 Jnet (fo=1, routed)XhX94<x FBstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)Xh~?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]u C?stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg[0]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]x FBstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]/C JFDREXhzr> Jclock pessimismXh D@stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh8󫿐; J arrival timeXh]?/ JXh4 JslackXhS=t C?stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg[0]/CFBstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsuR%>}F%GU=K?G?x]\=Skl=9H=>.=?">ˡe?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) C?stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg[0]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= FBstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg_n_0_[0] Jnet (fo=2, routed)XhP=u GCstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst[0]_i_1/I1 JXhzr FBstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst[0]_i_1/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzro= HDstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst[0]_i_1_n_0 Jnet (fo=1, routed)XhD<x FBstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)XhK?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]u C?stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg[0]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)XhG?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]x FBstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]/C JFDREXhzr> Jclock pessimismXhSk D@stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhF%; J arrival timeXh1?/ JXh4 JslackXhx]\= JFg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK95g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsu> >}p=>C??"/]=@S=j<>>ˡE?">t?e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) LHg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/P[32]!Prop_DSP_OUTPUT_DSP48E2_CLK_P[32] J DSP_OUTPUTXhzrS=r /+g_clock_rate_din[28].i_rate_test_comm/P[32] Jnet (fo=1, routed)Xhj<>k 95g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr :6g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/CLK Jnet (fo=17693, routed)XhC?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] JFg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 0,g_clock_rate_din[28].i_rate_test_comm/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]k 95g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]/C JFDREXhzr> Jclock pessimismXh@ 73g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh%?/ JXh4 JslackXh"/]=I .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/C.*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT6=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu =}Ƌ~ ף;?~?"/]=/o=`P=>> ?">d8?_(rising edge-triggered cell FDSE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDSE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR){ .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/QProp_DFF_SLICEL_C_Q JFDSEXhzr9H=k '#stat_regs_inst/i_cntr_rst_ctrl/B[0] Jnet (fo=13, routed)Xh)\=] /+stat_regs_inst/i_cntr_rst_ctrl/SR[0]_i_1/I0 JXhzr~ .*stat_regs_inst/i_cntr_rst_ctrl/SR[0]_i_1/OProp_D6LUT_SLICEL_I0_O JLUT6Xhzru<s 0,stat_regs_inst/i_cntr_rst_ctrl/SR[0]_i_1_n_0 Jnet (fo=1, routed)Xho<` .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/D JFDSEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]` .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/C JFDSEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh~?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]` .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/C JFDSEXhzr> Jclock pessimismXh/v ,(stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]Hold_DFF_SLICEL_C_D JFDSEXhA`e=/ JXh< J required timeXhƋ; J arrival timeXh!?/ JXh4 JslackXh"/]=  mistat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C=9stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT2=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsuϡE>}x>=v?x?b=G=j=>2L?">v?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) mistat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=~ ;7stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_sync_1 Jnet (fo=2, routed)Xh-=l >:stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d[1]_i_1/I1 JXhzr =9stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d[1]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT2XhzrY= =9stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/p_3_out[1] Jnet (fo=1, routed)Xhu<o =9stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr _[stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/dest_clk Jnet (fo=17693, routed)Xhv?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] mistat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/clk250 Jnet (fo=17693, routed)Xhx?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]o =9stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]/C JFDREXhzr> Jclock pessimismXhG ;7stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh+?/ JXh4 JslackXhb= 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsu^z@}@@/=G>y>@/=@@d=А==Q'>kc>O >^q@}??v??G?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xh^q@p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xh/=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]o =9g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd ;7g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh@; J arrival timeXhk/ JXh4 JslackXhQ'>b 2.stat_regs_inst/load_count_cntr_reg_replica_2/Ceastat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsu<@}@@-:uO@-:@@d=А==Q7>]=I >m3@}??@?C?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 2.stat_regs_inst/load_count_cntr_reg_replica_2/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > SOstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CEA2 Jnet (fo=102, routed)Xhm3@ eastat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2 J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17693, routed)XhO@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]d 2.stat_regs_inst/load_count_cntr_reg_replica_2/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr RNstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK Jnet (fo=17693, routed)Xh-:@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] d`stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXh]=@ Jclock uncertaintyXhd `\stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST#Setup_DSP_A_B_DATA_DSP48E2_CLK_CEA2 J DSP_A_B_DATAXh/ JXh< J required timeXh@; J arrival timeXh$/ JXh4 JslackXhQ7>f 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C?;g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuv@}@@ˡ=N>y>@ˡ=@@d=А==i>kc>O >m@}??v??-?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xhm@q ?;g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xhˡ=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd <8g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXhi>b 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuv@}@@ˡ=N>y>@ˡ=@@d=А==i>kc>O >m@}??v??-?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xhm@p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xhˡ=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]o =9g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd ;7g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]Setup_FFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXhi>b 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuv@}@@ˡ=N>y>@ˡ=@@d=А==i>kc>O >m@}??v??-?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xhm@p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xhˡ=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]o =9g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd ;7g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXhi>b 2.stat_regs_inst/load_count_cntr_reg_replica_2/Ceastat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsu79@}@"@M:JsO@M:@@d=А==k>]=I >0@}??@??_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 2.stat_regs_inst/load_count_cntr_reg_replica_2/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > SOstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/CEA2 Jnet (fo=102, routed)Xh0@ eastat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2 J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17693, routed)XhO@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]d 2.stat_regs_inst/load_count_cntr_reg_replica_2/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr RNstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/CLK Jnet (fo=17693, routed)XhM:@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] d`stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXh]=@ Jclock uncertaintyXhd `\stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST#Setup_DSP_A_B_DATA_DSP48E2_CLK_CEA2 J DSP_A_B_DATAXh/ JXh< J required timeXh"@; J arrival timeXht/ JXh4 JslackXhk>fG 51g_clock_rate_din[30].i_rate_ngccm_status0/q_reg/COKg_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/RSTP"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsu?5V@}@Bw@6A94=9@6@@d=А==l>]=V>OM@}????X9?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[30].i_rate_ngccm_status0/q_reg/QProp_DFF_SLICEM_C_Q JFDREXhzrV> ?;g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/RSTP Jnet (fo=98, routed)XhOM@ OKg_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/RSTP J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[30].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xh9@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[30].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr >:g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/CLK Jnet (fo=17693, routed)Xh6@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJg_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzr> Jclock pessimismXh]=@ Jclock uncertaintyXhd JFg_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST!Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP J DSP_OUTPUTXhVξ/ JXh< J required timeXhBw@; J arrival timeXhb/ JXh4 JslackXhl>b 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C?;g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuVv@}@(@ˡ=N>y>@ˡ=@@d=А== q>kc>O >m@}??v??-?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xhm@q ?;g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xhˡ=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd <8g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh(@; J arrival timeXh/ JXh4 JslackXh q>b 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C?;g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuVv@}@(@ˡ=N>y>@ˡ=@@d=А== q>kc>O >m@}??v??-?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xhm@q ?;g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xhˡ=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd <8g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]Setup_FFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh(@; J arrival timeXh/ JXh4 JslackXh q>b 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]/CE"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuVv@}@(@ˡ=N>y>@ˡ=@@d=А== q>kc>O >m@}??v??-?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/QProp_HFF_SLICEM_C_Q JFDREXhzrO >v 2.g_clock_rate_din[10].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xhm@p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhy>@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]g 51g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xhˡ=@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]o =9g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]/C JFDREXhzr> Jclock pessimismXhkc>@ Jclock uncertaintyXhd ;7g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh(@; J arrival timeXh/ JXh4 JslackXh q>b  fabric_clk fabric_clk!)Ë>(@1Ë>8@9AË>(@IË>8@e?@hq} < o=6ACC@ rise - rise rise - rise  okSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg/ChdSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuY%>}пOݿ=?O?<,.%==L7>-?@5>¥?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) okSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg/QProp_CFF_SLICEL_C_Q JFDREXhzfD= okSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg_0 Jnet (fo=12, routed)Xh= wsSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/statemachine.core_txd_i_1__571/I0 JXhzf vrSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/statemachine.core_txd_i_1__571/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzru< YUSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl_n_4 Jnet (fo=1, routed)Xho< hdSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr `\SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] okSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr WSSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)XhO?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] hdSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg/C JFDREXhzr> Jclock pessimismXh,. fbSFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_regHold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhп; J arrival timeXhk?/ JXh4 JslackXh< JvrSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall_reg/CxtSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu!Zd>})? >j??<v=>L7>Z9T?@5>P?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR)  vrSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= plSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall Jnet (fo=1, routed)Xhx= SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/bus_status_ctrl.sta_condition_i_1__170/I0 JXhzr SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/bus_status_ctrl.sta_condition_i_1__170/OProp_C6LUT_SLICEM_I0_O JLUT4XhzrQ8= b^SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sta_condition Jnet (fo=1, routed)Xho< xtSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr vrSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fabric_clk Jnet (fo=103803, routed)Xhj?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] vrSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall_reg/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] xtSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg/C JFDREXhzr> Jclock pessimismXh vrSFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_regHold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh); J arrival timeXh?/ JXh4 JslackXh< WSSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[1]/CSOSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuS>}?ʿcؿ=?c?b<1$o=5^=L7>Q?@5>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) WSSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= SOSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/dout[1] Jnet (fo=2, routed)Xh= c_SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[1]_i_1__323/I1 JXhzr b^SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[1]_i_1__323/OProp_C6LUT_SLICEM_I1_O JLUT4Xhzru< MISFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o[1] Jnet (fo=1, routed)Xho< SOSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] WSSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[1]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xhc?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] SOSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]/C JFDREXhzr> Jclock pessimismXh1$ QMSFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh?ʿ; J arrival timeXhv?/ JXh4 JslackXhb< WSSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/CSOSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu +>}˿yֿdQ=x?y?H <n\v=E=L7>+?@5>*\?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) WSSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD= SOSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/dout[7] Jnet (fo=2, routed)Xh-= c_SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[7]_i_1__557/I1 JXhzr b^SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[7]_i_1__557/OProp_A6LUT_SLICEM_I1_O JLUT4Xhzr< MISFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o[7] Jnet (fo=1, routed)XhD< SOSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)Xhx?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] WSSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xhy?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] SOSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/C JFDREXhzr> Jclock pessimismXhn\ QMSFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh˿; J arrival timeXh?/ JXh4 JslackXhH <xtSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/CgcSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu?5>}پެ=Т?پ?><ʡ=:=L7>&a?@5>K?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) xtSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/QProp_CFF_SLICEL_C_Q JFDREXhzfD= b^SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/c_state__0[1] Jnet (fo=15, routed)Xh= vrSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/statemachine.host_ack_i_1__253/I2 JXhzf uqSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/statemachine.host_ack_i_1__253/OProp_B6LUT_SLICEM_I2_O JLUT6Xhzr< YUSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/host_ack1_out Jnet (fo=1, routed)Xhu< gcSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)XhТ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] xtSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)Xhپ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] gcSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg/C JFDREXhzr> Jclock pessimismXh eaSFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_regHold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhx?/ JXh4 JslackXh><hxtSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[0]/CxtSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuN7>}µ0ݴ7^:>K?0ݴ?<1Hʡ=8A>L7>I?@5>z?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) xtSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDREXhzrD= b^SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/c_state__0[0] Jnet (fo=14, routed)Xh&1> SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_statemachine.c_state[1]_i_1__353/I2 JXhzr SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_statemachine.c_state[1]_i_1__353/OProp_D6LUT_SLICEM_I2_O JLUT6Xhzr< YUSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl_n_12 Jnet (fo=1, routed)Xho< xtSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)XhK?X2Y4 (CLOCK_ROOT) xtSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[0]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)Xh0ݴ?X2Y4 (CLOCK_ROOT) xtSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/C JFDREXhzr> Jclock pessimismXh1H vrSFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhµ; J arrival timeXh?/ JXh4 JslackXh< LHSFP_GEN[8].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/DataIn_local_reg[4]/CMISFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuC>}7῍῭v>>\??<qD=B`e>L7>A?@5>5^?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) LHSFP_GEN[8].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/DataIn_local_reg[4]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD= PLSFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/DataIn_local[4] Jnet (fo=1, routed)XhB`e> MISFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr @ Jclock pessimismXhq KGSFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh7ῐ; J arrival timeXhB`?/ JXh4 JslackXh< JFSFP_GEN[4].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/addr_local_reg[1]/CRNSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu >}w󸿍¿=L7??U<C%=Q=L7>m?@5>C?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) JFSFP_GEN[4].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/addr_local_reg[1]/QProp_EFF2_SLICEM_C_Q JFDREXhzfD= NJSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/addr_local[1] Jnet (fo=15, routed)Xhw= XTSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o[9]_i_1__290/I3 JXhzf WSSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o[9]_i_1__290/OProp_A6LUT_SLICEL_I3_O JLUT4Xhzru< LHSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o[9] Jnet (fo=1, routed)XhD< RNSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr @ Jclock pessimismXhC PLSFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhw󸿐; J arrival timeXh̼?/ JXh4 JslackXhU<^ MISFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/DataIn_local_reg[7]/CNJSFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuMb>}ڬҿ}?忭`=z?}??X<*M9H=j=L7>-?@5>.?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) MISFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/DataIn_local_reg[7]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= QMSFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/DataIn_local[7] Jnet (fo=1, routed)Xhj= NJSFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/clk_local Jnet (fo=103803, routed)Xhz?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] MISFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/DataIn_local_reg[7]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xh}??X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]/C JFDREXhzr> Jclock pessimismXh*M LHSFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhڬҿ; J arrival timeXh+?/ JXh4 JslackXhX<GjfSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_cmd_reg[1]/CsoSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu~>}onK =Q?K ?<F%=v=L7>2L?@5>t?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) jfSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_cmd_reg[1]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= vrSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg_0[1] Jnet (fo=8, routed)Xhʡ= yuSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_i_1__553/I2 JXhzr xtSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_i_1__553/OProp_G6LUT_SLICEL_I2_O JLUT6Xhzru< zvSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_i_1__553_n_0 Jnet (fo=1, routed)XhA`e< soSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)XhQ?X2Y4 (CLOCK_ROOT) jfSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_cmd_reg[1]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)XhK ?X2Y4 (CLOCK_ROOT) soSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg/C JFDREXhzr> Jclock pessimismXhF qmSFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_regHold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhon; J arrival timeXhI?/ JXh4 JslackXh<bi2c_clk_en_reg_rep__8/Cc_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1 LUT6=2)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsu A}Ad;AZ\GaKo@Z\@A~>А={>?@ᥛ=>zAף?.@m?` @e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >%Z\@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhƀAD JXhSLR Crossing[1->0] gcSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__51/I5 JXhzr fbSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__51/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr`P=y 62SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_reg_2 Jnet (fo=2, routed)Xhv>i ;7SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_4__51/I2 JXhzr :6SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_4__51/OProp_B5LUT_SLICEL_I2_O JLUT3XhzrM> c_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg_0 Jnet (fo=1, routed)XhQ> hdSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__51/I2 JXhzr gcSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__51/OProp_C6LUT_SLICEL_I2_O JLUT6Xhzr`P= ieSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__51_n_0 Jnet (fo=1, routed)XhP= c_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)XhZ\@X2Y4 (CLOCK_ROOT) c_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh>@ Jclock uncertaintyXh~ a]SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_regSetup_CFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXhd;A; J arrival timeXh/ JXh4 JslackXh?@*i2c_clk_en_reg_rep__8/Cc_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1 LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuq=A}ALA\7 WKo@\@A~>А={>@ᥛ=l? Aף?.@m?7!@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %\@-m?5 i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh€AD JXhSLR Crossing[1->0] yuSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/I5 JXhzr xtSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> zvSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 Jnet (fo=6, routed)Xh> hdSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__51/I1 JXhzr gcSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__51/OProp_H6LUT_SLICEM_I1_O JLUT3Xhzr"y> ieSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__51_n_0 Jnet (fo=1, routed)Xh*\= c_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh\@X2Y4 (CLOCK_ROOT) c_SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ a]SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_regSetup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhLA; J arrival timeXh&/ JXh4 JslackXh@bi2c_clk_en_reg_rep__8/Cc_SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1 LUT6=2)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuA}AAn[uKo@n[@A~>А={>M@ᥛ=@5>"Aף?.@m?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %n[@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh#AD JXhSLR Crossing[1->0] gcSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__52/I5 JXhzr fbSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__52/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr`P=y 62SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_reg_3 Jnet (fo=2, routed)Xh'1>i ;7SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_4__52/I2 JXhzr :6SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_4__52/OProp_A5LUT_SLICEM_I2_O JLUT3XhzrF> c_SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg_0 Jnet (fo=1, routed)XhSc> hdSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__52/I2 JXhzr gcSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__52/OProp_C6LUT_SLICEM_I2_O JLUT6Xhzr`P= ieSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__52_n_0 Jnet (fo=1, routed)Xh= c_SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhn[@X2Y4 (CLOCK_ROOT) c_SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ a]SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_regSetup_CFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhA; J arrival timeXh/ JXh4 JslackXhM@hi2c_clk_en_reg_rep__8/CuqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuA}A>FAX9\ScKo@X9\@A~>А={>n@ᥛ=>X9Aף?.@m? @e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %X9\@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh€AD JXhSLR Crossing[1->0] yuSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/I5 JXhzr xtSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> zvSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 Jnet (fo=6, routed)Xh-> uqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)XhX9\@X2Y4 (CLOCK_ROOT) tpSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ rnSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh>FA; J arrival timeXhj/ JXh4 JslackXhn@hi2c_clk_en_reg_rep__8/CuqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuaA}A3A[{nKo@[@A~>А={>@ᥛ=>Aף?.@m?c @e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %[@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh€AD JXhSLR Crossing[1->0] yuSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/I5 JXhzr xtSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> zvSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 Jnet (fo=6, routed)Xhȶ> uqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh[@X2Y4 (CLOCK_ROOT) tpSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ rnSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh3A; J arrival timeXhΣ/ JXh4 JslackXh@hi2c_clk_en_reg_rep__8/CuqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuƅA}ARA\ /]Ko@\@A~>А={>n@ᥛ=>~Aף?.@m?&!@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) a%\@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh€AD JXhSLR Crossing[1->0] yuSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/I5 JXhzr xtSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> zvSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 Jnet (fo=6, routed)Xh> uqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh\@X2Y4 (CLOCK_ROOT) tpSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXha@ Jclock uncertaintyXh~ rnSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhRA; J arrival timeXh"/ JXh4 JslackXhn@1i2c_clk_en_reg_rep__8/CmiSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuB`A}AwA!Z^{Ko@!Z@A~>А={>J@ᥛ=y>ĂAף?.@m?d;@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %!Z@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhzAD JXhSLR Crossing[1->0] qmSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52/I1 JXhzr plSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52/OProp_C5LUT_SLICEL_I1_O JLUT3Xhzr@> rnSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52_n_0 Jnet (fo=8, routed)Xh.? miSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh!Z@X2Y4 (CLOCK_ROOT) lhSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ jfSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhwA; J arrival timeXhI/ JXh4 JslackXhJ@0i2c_clk_en_reg_rep__8/CmiSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuXA}AA!Z^{Ko@!Z@A~>А={>s@ᥛ=y>jAף?.@m?d;@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %!Z@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhzAD JXhSLR Crossing[1->0] qmSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52/I1 JXhzr plSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52/OProp_C5LUT_SLICEL_I1_O JLUT3Xhzr@> rnSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52_n_0 Jnet (fo=8, routed)Xhh-? miSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh!Z@X2Y4 (CLOCK_ROOT) lhSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ jfSFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhA; J arrival timeXhA/ JXh4 JslackXhs@hi2c_clk_en_reg_rep__8/CuqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuEA}AyTA\(\Ko@\@A~>А={>x@ᥛ=>Aף?.@m?K7!@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) u%\@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh€AD JXhSLR Crossing[1->0] yuSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/I5 JXhzr xtSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> zvSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 Jnet (fo=6, routed)Xhَ> uqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh\@X2Y4 (CLOCK_ROOT) tpSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXhu@ Jclock uncertaintyXh~ rnSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhyTA; J arrival timeXh// JXh4 JslackXhx@hi2c_clk_en_reg_rep__8/CuqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuq=A}AMAj\}A`Ko@j\@A~>А={>g@ᥛ=>Aף?.@m? @e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) &%j\@-m?5i i2c_clk_en_reg_rep__8/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > lhSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)Xh€AD JXhSLR Crossing[1->0] yuSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/I5 JXhzr xtSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> zvSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 Jnet (fo=6, routed)Xȟ> uqSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)XhKo@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]M i2c_clk_en_reg_rep__8/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr _[SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhj\@X2Y4 (CLOCK_ROOT) tpSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/C JFDREXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh&@ Jclock uncertaintyXh~ rnSFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhMA; J arrival timeXh&/ JXh4 JslackXhg@ ipb_clkipb_clk!)/@1?@9A/@I?@en @hq}<pA DDC rise - rise rise - rise  OKSFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_DataOut_reg[15]/C[WSFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu!>}[둿e=t??<b⽥%=\=p=>ˡE?R>o?b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) OKSFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_DataOut_reg[15]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD= RNSFP_GEN[31].ngFEC_module/bram_array[9].RAM/data_pro_test.status_rep_reg[7][10] Jnet (fo=4, routed)XhT= VRSFP_GEN[31].ngFEC_module/bram_array[9].RAM/data_pro_test.status_rep[7]_i_1__411/I2 JXhzr UQSFP_GEN[31].ngFEC_module/bram_array[9].RAM/data_pro_test.status_rep[7]_i_1__411/OProp_G6LUT_SLICEM_I2_O JLUT6Xhzru< ^ZSFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]_2[6] Jnet (fo=1, routed)XhA`e< [WSFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_clk Jnet (fo=204768, routed)Xht?X2Y4 (CLOCK_ROOT) OKSFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_DataOut_reg[15]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT) [WSFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]/C JFDCEXhzr> Jclock pessimismXhb⽐ YUSFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh[; J arrival timeXhS?/ JXh4 JslackXh<0 NJSFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[30]/C{SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsup=>}j%|>?%?< 9H=C >p=>l?R>?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) NJSFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[30]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= TPSFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/dinb[30] Jnet (fo=2, routed)XhC > {SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr B>SFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[30]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr PLSFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh%?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] }ySFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh  soSFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1*Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[12] JRAMB36E2Xhi</ JXh< J required timeXhj; J arrival timeXhȶ?/ JXh4 JslackXh< A=SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[11]/C{SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[11]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuT>}* S,=? ?'<CQ D==p=> ׃?R>ף?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) A=SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[11]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= TPSFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/dinb[11] Jnet (fo=2, routed)Xh= {SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[11] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]s A=SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[11]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr PLSFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] }ySFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhCQ  soSFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0*Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[11] JRAMB36E2Xhi</ JXh< J required timeXh*; J arrival timeXhv?/ JXh4 JslackXh'<$ MISFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ngccm_din_reg[13]/C~zSFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[13]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuϡE>}Ա >??8<D=z>p=>}??R>?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ngccm_din_reg[13]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= SOSFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/dinb[13] Jnet (fo=2, routed)Xhz> ~zSFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[13] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] MISFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ngccm_din_reg[13]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh rnSFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0*Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[13] JRAMB36E2Xhi</ JXh< J required timeXhԱ; J arrival timeXh̡?/ JXh4 JslackXh8<a @}"۩KѴ=D?"۩?b<PD==p=>^i?R>|?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) @ Jclock pessimismXhP rnSFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[0] JRAMB36E2Xhi</ JXh< J required timeXh; J arrival timeXh*\?/ JXh4 JslackXhb< NJSFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[15]/CxtSFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[15]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuX9>}Zh=K?Z?R<|ֽ9H=+>p=>e;_?R>?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB18E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) NJSFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[15]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= TPSFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/dina[15] Jnet (fo=2, routed)Xh+> xtSFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[15] JRAMB18E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr B>SFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)XhK?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[15]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr PLSFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhZ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] vrSFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB18E2Xhzr> Jclock pessimismXh|ֽ lhSFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg-Hold_RAMB18E2_L_RAMB180_CLKBWRCLK_DINADIN[15] JRAMB18E2Xhi</ JXh< J required timeXh; J arrival timeXhv?/ JXh4 JslackXhR< LHSFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[1]/C}ySFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu@>} /\>-?/?<j･9H=V>p=>2l?R>В?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) LHSFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[1]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= RNSFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/dinb[1] Jnet (fo=2, routed)XhV> }ySFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh-?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]~ LHSFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[1]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh/?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhjｐ rnSFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[1] JRAMB36E2Xhi</ JXh< J required timeXh ; J arrival timeXh¥?/ JXh4 JslackXh<% MISFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[30]/C~zSFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuv>>}v۽˿iP>#۩??<s D=O >p=>-?R>&?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[30]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= SOSFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/dinb[30] Jnet (fo=2, routed)XhO > ~zSFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh#۩?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] MISFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[30]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXhs  rnSFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1*Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[12] JRAMB36E2Xhi</ JXh< J required timeXhv۽; J arrival timeXh?/ JXh4 JslackXh<" MISFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[24]/C}ySFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu>}ݓ5^ʿ߾=?5^?<4D==p=>A?R>?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[24]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= SOSFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/dinb[24] Jnet (fo=2, routed)Xh= }ySFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] MISFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[24]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh5^?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh4 rnSFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6] JRAMB36E2Xhi</ JXh< J required timeXhݓ; J arrival timeXh[d?/ JXh4 JslackXh< LHSFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[1]/C}ySFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuC>}#ɿ-Z>y?#?aI< 3D=n>p=>d;?R>|?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) LHSFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[1]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= RNSFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/dinb[1] Jnet (fo=2, routed)Xhn> }ySFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ipb_clk Jnet (fo=204768, routed)Xhy?X2Y4 (CLOCK_ROOT)~ LHSFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[1]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh#?X2Y4 (CLOCK_ROOT) |xSFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh 3 rnSFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[1] JRAMB36E2Xhi</ JXh< J required timeXh; J arrival timeXh*\?/ JXh4 JslackXhaI< $ ctrl_regs_inst/regs_reg[2][14]/C#i_I2C_if/prescale_cnt_reg[14]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuRA}B B&1x.>@&1@Bڭ=А=>n @P94=~j>TA ?@/?@b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) "%&1@-/?5q $ ctrl_regs_inst/regs_reg[2][14]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#i_I2C_if/prescale_cnt_reg[15]_0[14] Jnet (fo=579, routed)XhAD JXhSLR Crossing[1->0]R $ i_I2C_if/prescale_cnt[14]_i_1/I0 JXhzrs #i_I2C_if/prescale_cnt[14]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=` i_I2C_if/prescale_cnt[14] Jnet (fo=1, routed)XhC =U #i_I2C_if/prescale_cnt_reg[14]/D JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh>@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[2][14]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzrp i_I2C_if/ipb_clk Jnet (fo=204768, routed)Xh&1@X2Y4 (CLOCK_ROOT)U #i_I2C_if/prescale_cnt_reg[14]/C JFDREXhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh"@ Jclock uncertaintyXhڭl !i_I2C_if/prescale_cnt_reg[14]Setup_GFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXh B; J arrival timeXhu/ JXh4 JslackXhn @,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CyuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsu}?A}BBVFSb33[@VF@Bڭ=А=>?jQ@P94=?5?MA ?+7@/?%@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) $ƾ%VF@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh`AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__591/I4 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__591/OProp_E6LUT_SLICEL_I4_O JLUT5Xhzr֣p> QMSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xhp=> yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr xtSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzr"y> zvSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)Xh? yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhVF@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh$ƾ@ Jclock uncertaintyXhڭ rnSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0] JRAMB36E2Xhsh1/ JXh< J required timeXhB; J arrival timeXh/ JXh4 JslackXh?jQ@U,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CyuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[1]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsup=A}BBVFSb33[@VF@Bڭ=А=>zQ@P94=?5?KA ?+7@/?%@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) $ƾ%VF@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh`AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__591/I4 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__591/OProp_E6LUT_SLICEL_I4_O JLUT5Xhzr֣p> QMSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xhp=> yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr xtSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzr"y> zvSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)Xh ד? yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[1] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhVF@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh$ƾ@ Jclock uncertaintyXhڭ rnSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[1] JRAMB36E2Xhsh1/ JXh< J required timeXhB; J arrival timeXhף/ JXh4 JslackXhzQ@U $ ctrl_regs_inst/regs_reg[2][15]/C#i_I2C_if/prescale_cnt_reg[15]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuXA}B= BX1#gf>@X1@Bڭ=А=>S@P94=㥛>xA ?5^@/? @b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %X1@-/?5q $ ctrl_regs_inst/regs_reg[2][15]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>l '#i_I2C_if/prescale_cnt_reg[15]_0[15] Jnet (fo=579, routed)XhAD JXhSLR Crossing[1->0]R $ i_I2C_if/prescale_cnt[15]_i_1/I5 JXhzrs #i_I2C_if/prescale_cnt[15]_i_1/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzr(>` i_I2C_if/prescale_cnt[15] Jnet (fo=1, routed)XhP=U #i_I2C_if/prescale_cnt_reg[15]/D JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xhgf>@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[2][15]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzrp i_I2C_if/ipb_clk Jnet (fo=204768, routed)XhX1@X2Y4 (CLOCK_ROOT)U #i_I2C_if/prescale_cnt_reg[15]/C JFDREXhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh@ Jclock uncertaintyXhڭl !i_I2C_if/prescale_cnt_reg[15]Setup_CFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh= B; J arrival timeXh$/ JXh4 JslackXhS@,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CzvSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuA}BBEFa吾33[@EF@Bڭ=А=>]@P94=K?A ?+7@/?W%@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3ƾ%EF@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh}?AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__599/I4 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__599/OProp_F6LUT_SLICEM_I4_O JLUT5XhzrGz> RNSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xhˡ> zvSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr yuSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_B5LUT_SLICEM_I0_O JLUT2XhzrS> {wSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)Xh#ۉ? zvSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr PLSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhEF@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] }ySFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh3ƾ@ Jclock uncertaintyXhڭ soSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0] JRAMB36E2Xhsh1/ JXh< J required timeXhB; J arrival timeXh|/ JXh4 JslackXh]@U,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CyuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsu$A}BaBCS33[@C@Bڭ=А=>;h@P94=?5?33A ?+7@/?"@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) iMþ%C@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh`AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__591/I4 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__591/OProp_E6LUT_SLICEL_I4_O JLUT5Xhzr֣p> QMSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xhp=> yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr xtSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzr"y> zvSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)XhD? yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhC@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXhiMþ@ Jclock uncertaintyXhڭ rnSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[1] JRAMB36E2Xhsh1/ JXh< J required timeXhaB; J arrival timeXhC/ JXh4 JslackXh;h@U,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CyuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuA}BaBCS33[@C@Bڭ=А=>}h@P94=?5?+A ?+7@/?"@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) iMþ%C@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh`AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__591/I4 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__591/OProp_E6LUT_SLICEL_I4_O JLUT5Xhzr֣p> QMSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xhp=> yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr xtSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzr"y> zvSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)XhC? yuSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhC@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXhiMþ@ Jclock uncertaintyXhڭ rnSFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0] JRAMB36E2Xhsh1/ JXh< J required timeXhaB; J arrival timeXh/ JXh4 JslackXh}h@U,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CzvSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuA}BBEFa吾33[@EF@Bڭ=А=>pbj@P94=K?ZdA ?+7@/?W%@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3ƾ%EF@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh}?AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__599/I4 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__599/OProp_F6LUT_SLICEM_I4_O JLUT5XhzrGz> RNSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xhˡ> zvSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr yuSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_B5LUT_SLICEM_I0_O JLUT2XhzrS> {wSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)Xha? zvSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr PLSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)XhEF@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] }ySFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh3ƾ@ Jclock uncertaintyXhڭ soSFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[1] JRAMB36E2Xhsh1/ JXh< J required timeXhB; J arrival timeXh/ JXh4 JslackXhpbj@U ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CQMSFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuEA}B B9:333[@9@Bڭ=А=>0m@P94=(>A ?+7@/?@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RR%9@-/?5y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)XhrAD JXhSLR Crossing[0->1]^ 0,i_AXI4_to_ipbus/input_size_i[12]_i_1__598/I3 JXhzr /+i_AXI4_to_ipbus/input_size_i[12]_i_1__598/OProp_E6LUT_SLICEL_I3_O JLUT6Xhzr)> SOSFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[12]_0[0] Jnet (fo=11, routed)Xh~? @ QMSFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/ipb_clk Jnet (fo=204768, routed)Xh9@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLSFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]/C JFDCEXhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXhRR@ Jclock uncertaintyXhڭ NJSFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]Setup_HFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh B; J arrival timeXh/ JXh4 JslackXh0m@U,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/CyuSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0]"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1 LUT5=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsulA}BB0D(33[@0D@Bڭ=А=>zn@P94=A?jA ?+7@/?#@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `ľ%0D@-/?5 y ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>q *&i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] Jnet (fo=10950, routed)Xh"AD JXhSLR Crossing[0->1]T &"i_AXI4_to_ipbus/BRAM_l_i_1__597/I3 JXhzru %!i_AXI4_to_ipbus/BRAM_l_i_1__597/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> QMSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/wea[0] Jnet (fo=1, routed)Xh㥛= yuSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/I0 JXhzr xtSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/OProp_H5LUT_SLICEM_I0_O JLUT2Xhzr= zvSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 Jnet (fo=8, routed)Xh? yuSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrw i_AXI4_to_ipbus/ipb_clk Jnet (fo=204768, routed)Xh33[@X2Y4 (CLOCK_ROOT)^ ,(i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204768, routed)Xh0D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhP94=E Jinter-SLR compensationXh`ľ@ Jclock uncertaintyXhڭ rnSFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1&Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0] JRAMB36E2Xhsh1/ JXh< J required timeXhB; J arrival timeXh/ JXh4 JslackXhzn@U  refclk125 refclk125!)@1@9A@I@hq}?EE<  DRPclk_dcm DRPclk_dcm!)#@13@9A#@I3@hq}MAFF?  clk125_dcm clk125_dcm!)@1@9A@I@hq}L7@GG  clk250_dcm clk250_dcm!)?1@9A?I@hq}n@HH  ipb_clk_dcm ipb_clk_dcm!)/@1?@9A/@I?@hq}MAIID rxoutclk_out[0]rxoutclk_out[0]!)6 @16@9A6 @I6@et@hq} Z< p>JJ rise - rise rise - rise  uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[14]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[14]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsu)>}5:O=(?O?Z<⽥9H=9=q=->=?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})l(rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[14]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[14] Jnet (fo=2, routed)Xh9= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[14] JFIFO36E2Xhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhl>X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[14]/C JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk Jnet (fo=617, routed)Xh/$?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK JFIFO36E2Xhzr> Jclock pessimismXh⽐ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2"Hold_FIFO36E2_FIFO36_WRCLK_DIN[14] JFIFO36E2Xhi</ JXh< J required timeXh5:; J arrival timeXhA?/ JXh4 JslackXhZ<uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[15]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[15]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsuK>}cEO\ >?O?=D=>q=>=?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})l(rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[15]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[15] Jnet (fo=2, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[15] JFIFO36E2Xhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh>X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[15]/C JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk Jnet (fo=617, routed)Xh/$?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK JFIFO36E2Xhzr> Jclock pessimismXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2"Hold_FIFO36E2_FIFO36_WRCLK_DIN[15] JFIFO36E2Xhi</ JXh< J required timeXhcE; J arrival timeXhhM?/ JXh4 JslackXh=uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[24]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[24]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsu8>}DOC>I ?O?*=*\D=Q>q=>=?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})l(rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[24]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[24] Jnet (fo=2, routed)XhQ> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[24] JFIFO36E2Xhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh(>X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[24]/C JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk Jnet (fo=617, routed)Xh/$?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK JFIFO36E2Xhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2"Hold_FIFO36E2_FIFO36_WRCLK_DIN[24] JFIFO36E2Xhi</ JXh< J required timeXhD; J arrival timeXhVM?/ JXh4 JslackXh*=uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[30]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[30]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsu>}DO=H>  ?O?\=*\D=Y>q=Zd>=?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})l(rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[30]/QProp_FFF2_SLICEM_C_Q JFDREXhzrD= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[30] Jnet (fo=2, routed)XhY> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[30] JFIFO36E2Xhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh>X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[30]/C JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk Jnet (fo=617, routed)Xh/$?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK JFIFO36E2Xhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2"Hold_FIFO36E2_FIFO36_WRCLK_DIN[30] JFIFO36E2Xhi</ JXh< J required timeXhD; J arrival timeXhhM?/ JXh4 JslackXh\=uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[39]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DINP[7]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsuo>}DOC>I ?O?t=*\9H=S>q=>=?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})l(rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[39]/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[71] Jnet (fo=1, routed)XhS> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DINP[7] JFIFO36E2Xhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh(>X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[39]/C JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk Jnet (fo=617, routed)Xh/$?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK JFIFO36E2Xhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2"Hold_FIFO36E2_FIFO36_WRCLK_DINP[7] JFIFO36E2Xhi</ JXh< J required timeXhD; J arrival timeXhM?/ JXh4 JslackXht=nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[4]/Cpli_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsu|>}7濍J ⿭ɪ> ?J ?7=}Žl=>=KW?x=淪?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[4]/QProp_FFF2_SLICEM_C_Q JFDREXhzrl= qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg_n_0_[4] Jnet (fo=1, routed)Xh> pli_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh p?X5Y0 (CLOCK_ROOT) nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[4]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh}??X5Y0 (CLOCK_ROOT) pli_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]/C JFDREXhzr> Jclock pessimismXh}Ž nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]Hold_AFF_SLICEL_C_D JFDREXh>/ JXh< J required timeXh7濐; J arrival timeXhH?/ JXh4 JslackXh7=uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[25]/Cuqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsuX9>}%忍῭>O??B=QŽ"=µ>=k[?x=ff?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[25]/QProp_FFF_SLICEM_C_Q JFDREXhzr"= nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/en32_fifo_din_i[25] Jnet (fo=2, routed)Xhµ> uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhjt?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[25]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]/C JFDREXhzr> Jclock pessimismXhQŽ soi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]Hold_FFF2_SLICEL_C_D JFDREXhI >/ JXh< J required timeXh%忐; J arrival timeXh5^?/ JXh4 JslackXhB=jfi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxheader_to_fifo_i_reg[1]/Cwsi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsu k>}`c7*\/=y?*\/?v&=9H=X9>q=33>= >h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})j(rising edge-triggered cell SRL16E clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) jfi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxheader_to_fifo_i_reg[1]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= _[i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/Q[1] Jnet (fo=2, routed)XhX9> wsi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1/D JSRL16EXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxusrclk_out Jnet (fo=617, routed)Xhsh>X5Y0 (CLOCK_ROOT) jfi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxheader_to_fifo_i_reg[1]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1/CLK JSRL16EXhzr> Jclock pessimismXh uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1Hold_C5LUT_SLICEM_CLK_D JSRL16EXhl=/ JXh< J required timeXh`c7; J arrival timeXhA?/ JXh4 JslackXhv&=tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[4]/Ctpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsun>}4w?D;=?w??A)=RS˽D=[=q=>=M?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[4]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD= mii_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/en32_fifo_din_i[4] Jnet (fo=2, routed)Xh[= tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh>X5Y0 (CLOCK_ROOT) tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[4]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]/C JFDREXhzr> Jclock pessimismXhRS˽ rni_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]Hold_AFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh4; J arrival timeXhe;??/ JXh4 JslackXhA)=tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[8]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[40]"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsu?5>}S=O/=H?O?-=ɽD=>q=">=?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})l(rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fastrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[8]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[40] Jnet (fo=1, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[40] JFIFO36E2Xhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)XhX>X5Y0 (CLOCK_ROOT) tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[8]/C JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk Jnet (fo=617, routed)Xh/$?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK JFIFO36E2Xhzr> Jclock pessimismXhɽ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2"Hold_FIFO36E2_FIFO36_WRCLK_DIN[40] JFIFO36E2Xhi</ JXh< J required timeXhS=; J arrival timeXh'1H?/ JXh4 JslackXh-=qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C}i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT4=1 LUT5=2)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu@}@@p=e;??@=А=t@=> 7??x= ׃?=}?U?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/QProp_BFF2_SLICEM_C_Q JFDREXhzrO > tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg_n_0_[28] Jnet (fo=2, routed)Xh"? ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7/I2 JXhzr }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7/OProp_H6LUT_SLICEM_I2_O JLUT4Xhzr"y> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7_n_0 Jnet (fo=1, routed)Xh!> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5/I4 JXhzr }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5/OProp_G6LUT_SLICEM_I4_O JLUT5XhzrE= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 Jnet (fo=1, routed)XhS> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_2/I4 JXhzr }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_2/OProp_H6LUT_SLICEM_I4_O JLUT5Xhzr"y> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect Jnet (fo=2, routed)Xhp> }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhn?X5Y0 (CLOCK_ROOT) qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh{n?X5Y0 (CLOCK_ROOT) }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh {i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_regSetup_AFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh@; J arrival timeXh// JXh4 JslackXht@\qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/Cuqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT4=1 LUT5=2)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsuJ7@}@e@^|?e;?^?@=А=?~@=> 7?x?x= ׃?=jT?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/QProp_BFF2_SLICEM_C_Q JFDREXhzrO > tpi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg_n_0_[28] Jnet (fo=2, routed)Xh"? ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7/I2 JXhzr }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7/OProp_H6LUT_SLICEM_I2_O JLUT4Xhzr"y> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7_n_0 Jnet (fo=1, routed)Xh!> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5/I4 JXhzr }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5/OProp_G6LUT_SLICEM_I4_O JLUT5XhzrE= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 Jnet (fo=1, routed)XhS> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_2/I4 JXhzr }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_2/OProp_H6LUT_SLICEM_I4_O JLUT5Xhzr"y> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect Jnet (fo=2, routed)Xh&> uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhn?X5Y0 (CLOCK_ROOT) qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhim?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh soi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_regSetup_GFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXhe@; J arrival timeXhx/ JXh4 JslackXh?~@{i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/Crni_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT3=1 LUT4=1 LUT5=1)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsun @}@<.@I3\?I?@=А=F@=0,?پ?x=Nb?=#Y?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/Q[28] Jnet (fo=2, routed)XhJ > {i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/I0 JXhzr ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/OProp_H6LUT_SLICEL_I0_O JLUT4Xhzf +> |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3_n_0 Jnet (fo=4, routed)Xh^I> }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2/I4 JXhzf |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2/OProp_C6LUT_SLICEL_I4_O JLUT5XhzfA`> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2_n_0 Jnet (fo=1, routed)Xh> }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_1/I0 JXhzf |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzr> _[i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/D[1] Jnet (fo=2, routed)Xh}?? rni_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh!r?X5Y0 (CLOCK_ROOT) rni_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh pli_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_regSetup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh<.@; J arrival timeXhQp/ JXh4 JslackXhF@`uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[36]/C}yi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT5=1 LUT6=2)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu(?}@@I_/-?I?@=А=B@w=ˡ?X?x=Ȗ?=#Y?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[36]/QProp_CFF2_SLICEL_C_Q JFDREXhzrV> nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/en32_fifo_din_i[76] Jnet (fo=2, routed)XhVN? ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_7/I5 JXhzr }yi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_7/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr+> {i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0 Jnet (fo=1, routed)Xho> ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_2/I5 JXhzr }yi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_2/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrE= |xi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT1__15 Jnet (fo=1, routed)Xh> ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_1/I2 JXhzr }yi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_1/OProp_H6LUT_SLICEL_I2_O JLUT5Xhzr+> {i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0 Jnet (fo=1, routed)Xh*\= }yi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)XhB`?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[36]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh!r?X5Y0 (CLOCK_ROOT) }yi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg/C JFDREXhzr> Jclock pessimismXhw=@ Jclock uncertaintyXh {wi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_regSetup_HFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh@; J arrival timeXh+o/ JXh4 JslackXhB@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/Cuqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT3=1 LUT4=1 LUT5=1)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsuI@}@3@^#?^?@=А=k@= nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/Q[28] Jnet (fo=2, routed)XhJ > {i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/I0 JXhzr ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/OProp_H6LUT_SLICEL_I0_O JLUT4Xhzf +> |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3_n_0 Jnet (fo=4, routed)Xh^I> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_2/I0 JXhzf i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_2/OProp_C5LUT_SLICEL_I0_O JLUT5Xhzfx> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_2_n_0 Jnet (fo=1, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_1/I1 JXhzf i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3Xhzr|?> _[i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/D[0] Jnet (fo=1, routed)Xh33> uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhim?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh soi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]Setup_CFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh3@; J arrival timeXh-j/ JXh4 JslackXhk@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/Cuqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT3=1 LUT4=1 LUT5=1)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu(@}@<.@CO ?C?@=А=(@=0,?M?x=Nb?=4^Z?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> nji_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/Q[28] Jnet (fo=2, routed)XhJ > {i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/I0 JXhzr ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/OProp_H6LUT_SLICEL_I0_O JLUT4Xhzf +> |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3_n_0 Jnet (fo=4, routed)Xh^I> }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2/I4 JXhzf |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2/OProp_C6LUT_SLICEL_I4_O JLUT5XhzfA`> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2_n_0 Jnet (fo=1, routed)Xh> }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_1/I0 JXhzf |i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzr> _[i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/D[1] Jnet (fo=2, routed)XhQ> uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]/D JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh33s?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh soi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]Setup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXh<.@; J arrival timeXhJ j/ JXh4 JslackXh(@qoki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/Cvri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]/CE"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT6=1)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsuW?}@@^G?^?@=А=lj@=a>?x=~?=jT?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) oki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/QProp_DFF2_SLICEM_C_Q JFDREXhzrI > a]i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/p_1_in Jnet (fo=4, routed)Xh? vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage[39]_i_1/I4 JXhzr uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage[39]_i_1/OProp_F6LUT_SLICEL_I4_O JLUT6Xhzr> gci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/mod_do_wr_en Jnet (fo=43, routed)Xh? vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]/CE JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh{?X5Y0 (CLOCK_ROOT) oki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhim?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh soi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh@; J arrival timeXh[/ JXh4 JslackXhlj@+qoki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/Cvri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/CE"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZ(LUT6=1)j;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsuW?}@@^G?^?@=А=lj@=a>?x=~?=jT?h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) oki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/QProp_DFF2_SLICEM_C_Q JFDREXhzrI > a]i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/p_1_in Jnet (fo=4, routed)Xh? vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage[39]_i_1/I4 JXhzr uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage[39]_i_1/OProp_F6LUT_SLICEL_I4_O JLUT6Xhzr> gci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/mod_do_wr_en Jnet (fo=43, routed)Xh? vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/CE JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xh{?X5Y0 (CLOCK_ROOT) oki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/C JFDREXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> vri_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhim?X5Y0 (CLOCK_ROOT) uqi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh soi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh@; J arrival timeXh[/ JXh4 JslackXhlj@+i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu}?@}@z@X/ݼ5^?X?@=А=B@=-?ףP?x=]?=S?q(rising edge-triggered cell GTHE3_CHANNEL clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXBUFSTATUS[2]+Prop_GTHE3_CHANNEL_RXUSRCLK2_RXBUFSTATUS[2] J GTHE3_CHANNELXhzr-? yui_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/rxbufstatus_out[0] Jnet (fo=1, routed)XhףP? i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg/D JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk2_in[0] Jnet (fo=617, routed)Xh"{?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/gtwiz_userclk_rx_usrclk_out Jnet (fo=617, routed)Xhl?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh }i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_regSetup_EFF2_SLICEL_C_D JFDREXh=/ JXh< J required timeXhz@; J arrival timeXhnb/ JXh4 JslackXhB@;i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]/D"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu@}@@~t5^?~?@=А=@=$?yf?x=]?=EV?q(rising edge-triggered cell GTHE3_CHANNEL clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})h(rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slowrxoutclk_out[0]rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[24]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[24] J GTHE3_CHANNELXhzr$? hdi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_rxdata_from_gtx_i[24] Jnet (fo=1, routed)Xhyf? qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]/D JFDREXhzrS J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk2_in[0] Jnet (fo=617, routed)Xh"{?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> [Wi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxusrclk_out Jnet (fo=617, routed)Xho?X5Y0 (CLOCK_ROOT) qmi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh oki_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh@; J arrival timeXha/ JXh4 JslackXh@ txoutclk_out[0]_48txoutclk_out[0]_48!)6 @16@9A6 @I6@hq}Ob>KK axi_c2c_phy_clkaxi_c2c_phy_clk!)6@16)@9A6@I6)@ex@hq}-<z?? LL= rise - rise rise - rise  i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[22]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[22]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsuv>>}Ԃo0d" G?0d?-<D=O >'>>D>x ?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})r(rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[22]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[22] Jnet (fo=1, routed)XhO > i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[22] J GTHE3_CHANNELXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_1 Jnet (fo=1684, routed)Xhx)?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[22]/C JFDREXhzrS J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=1684, routed)Xh:?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[22] J GTHE3_CHANNELXh'>/ JXh< J required timeXhԂo; J arrival timeXhKw?/ JXh4 JslackXh-<i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[7]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/D"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1)j;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsuv>}H኿O>A`?O?=o=}?5>'>d?D>e;??i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[7]/QProp_AFF2_SLICEM_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_in_bin[7] Jnet (fo=4, routed)XhT%> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff[6]_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff[6]_i_1/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzru< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/gray_enc[6] Jnet (fo=1, routed)Xhu< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/D JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/wr_clk Jnet (fo=1684, routed)XhK B?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[7]/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk Jnet (fo=1684, routed)XhNbp?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/C JFDREXhzr> Jclock pessimismXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhH኿; J arrival timeXh?/ JXh4 JslackXh=w~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[3]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsuK7>}bm0d:*'1H?0d?y=D=$>'>?D>x ?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})r(rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[3]/QProp_CFF_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[3] Jnet (fo=1, routed)Xh$> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3] J GTHE3_CHANNELXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_1 Jnet (fo=1684, routed)Xh)?X5Y0 (CLOCK_ROOT) ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[3]/C JFDREXhzrS J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=1684, routed)Xh:?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[3] J GTHE3_CHANNELXh >/ JXh< J required timeXhbm; J arrival timeXhv?/ JXh4 JslackXhy=;c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[7]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]/D"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu X9>}~r*^=Y?r?*\=D='1>'>rh?D>5?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[7]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/axi_c2c_aurora_rx_tdata[7] Jnet (fo=3, routed)Xh'1> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]/D JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= lhi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_SRC_RDY_N_reg_inv_1 Jnet (fo=1684, routed)XhZd;?X5Y0 (CLOCK_ROOT) c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[7]/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xhf?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]/C JFDREXhzr> Jclock pessimismXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]Hold_FFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh~; J arrival timeXh?/ JXh4 JslackXh*\=i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[4]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6]/D"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT6=1)j;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu>}}m狿w=`?m? =G!%=Q='>?D>j i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/wr_clk Jnet (fo=1684, routed)Xhim?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6]/C JFDREXhzr> Jclock pessimismXhG! i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh}; J arrival timeXh?/ JXh4 JslackXh =i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[3]/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]/D"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT6=1)j;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu>}Cyak= \??O;=#%=X9='>z?D>7?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR)  i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[3]/QProp_CFF_SLICEL_C_Q JFDREXhzrD= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/Q[3] Jnet (fo=8, routed)Xht= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i[6]_i_1__0/I3 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i[6]_i_1__0/OProp_D6LUT_SLICEL_I3_O JLUT6Xhzru< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i[6]_i_1__0_n_0 Jnet (fo=1, routed)Xho< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]/D JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/wr_clk Jnet (fo=1684, routed)Xhv>?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[3]/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/wr_clk Jnet (fo=1684, routed)Xhh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]/C JFDREXhzr> Jclock pessimismXh# i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhCy; J arrival timeXh?/ JXh4 JslackXhO;=gci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/txseq_counter_i_reg[4]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXSEQUENCE[4]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsuz>}fb0dlG?0d?R"=N,9H=='>v>D>x ?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})r(rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) gci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/txseq_counter_i_reg[4]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txsequence_in[4] Jnet (fo=8, routed)Xh= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXSEQUENCE[4] J GTHE3_CHANNELXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= YUi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/stg3_reg_0 Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) gci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/txseq_counter_i_reg[4]/C JFDREXhzrS J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=1684, routed)Xh:?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXhN, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST*Hold_GTHE3_CHANNEL_TXUSRCLK2_TXSEQUENCE[4] J GTHE3_CHANNELXhO >/ JXh< J required timeXhfb; J arrival timeXhCl?/ JXh4 JslackXhR"=x~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[7]/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[7]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu\I>}Hp0d:*'1H?0d?p%=9H=P>'>?D>x ?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})r(rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[7]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[7] Jnet (fo=1, routed)XhP> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[7] J GTHE3_CHANNELXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_1 Jnet (fo=1684, routed)Xh)?X5Y0 (CLOCK_ROOT) ~i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[7]/C JFDREXhzrS J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=1684, routed)Xh:?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[7] J GTHE3_CHANNELXh +>/ JXh< J required timeXhHp; J arrival timeXhz?/ JXh4 JslackXhp%=c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_PE_DATA_reg[34]/Cd`i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]/D"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu[94>}{Ȇ|=XY?Ȇ?(=S'D=o>'>&?D>-2?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_PE_DATA_reg[34]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD= [Wi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/D[29] Jnet (fo=1, routed)Xho> d`i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]/D JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_DATA_REG_reg[0]_0 Jnet (fo=1684, routed)Xh";?X5Y0 (CLOCK_ROOT) c_i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_PE_DATA_reg[34]/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> lhi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_SRC_RDY_N_reg_inv_1 Jnet (fo=1684, routed)XhSc?X5Y0 (CLOCK_ROOT) d`i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]/C JFDREXhzr> Jclock pessimismXhS' b^i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]Hold_AFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh{; J arrival timeXh43?/ JXh4 JslackXh(=i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]/D"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT6=1)j;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu)>}srffQ)K=W?ff? )=y-!o=='>?D>sh1?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fastaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 Jnet (fo=1, routed)XhL7= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][2]_i_1/I1 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][2]_i_1/OProp_C6LUT_SLICEL_I1_O JLUT6Xhzru< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg[2] Jnet (fo=1, routed)Xho< i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]/D JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb Jnet (fo=1684, routed)Xh9?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb Jnet (fo=1684, routed)Xh\b?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]/C JFDREXhzr> Jclock pessimismXhy-! i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhsr; J arrival timeXhp}?/ JXh4 JslackXh )=T xti_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/tdm_data_valid_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/REGCEAREGCE"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=2 LUT6=1)jC? d@>?h>sh?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) xti_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/tdm_data_valid_reg/QProp_HFF_SLICEL_C_Q JFDREXhzfO > i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/tdm_user_data_valid Jnet (fo=8, routed)Xh? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/FSM_onehot_state[0]_i_1/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/FSM_onehot_state[0]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3Xhzf1,> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/FSM_onehot_state[0]_i_1_n_0 Jnet (fo=2, routed)Xh/ݤ> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/s_ready_i_i_1/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/s_ready_i_i_1/OProp_B6LUT_SLICEL_I0_O JLUT6XhzrA`> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/pwropt Jnet (fo=2, routed)Xh:? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_REGCEAREGCE_cooolgate_en_gate_1/I1 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_REGCEAREGCE_cooolgate_en_gate_1/OProp_G6LUT_SLICEL_I1_O JLUT3Xhzrjt> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_REGCEAREGCE_cooolgate_en_sig_1 Jnet (fo=1, routed)Xhap? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/REGCEAREGCE JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> soi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) xti_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/tdm_data_valid_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK JRAMB36E2Xhzr> Jclock pessimismXhFM>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg+Setup_RAMB36E2_RAMB36_CLKARDCLK_REGCEAREGCE JRAMB36E2XhE/ JXh< J required timeXhWiA; J arrival timeXh/ JXh4 JslackXhx@"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?1$@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)XhI ? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[5] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXh/ JXh4 JslackXhA1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?#@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xh7? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[6] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXh/ JXh4 JslackXhA1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?F#@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xhrh? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[7] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXh/ JXh4 JslackXh(A1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?"@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xh? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[4] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXh~/ JXh4 JslackXhA1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?: @>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)XhZd? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[1] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXhp/ JXh4 JslackXhA1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?Nb @>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xh? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXhG/ JXh4 JslackXh&A1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?E&@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xh,? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg'Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN JRAMB36E2Xh/ JXh< J required timeXh)iA; J arrival timeXhY9/ JXh4 JslackXh} A1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?#@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xh-? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[3] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXh/ JXh4 JslackXhV A1"i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2]"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT2=1 LUT3=1 LUT4=1)j]?x@>t?h>^?i(rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})m(rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slowaxi_c2c_phy_clkaxi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy Jnet (fo=49, routed)XhX? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/I0 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/OProp_B5LUT_SLICEM_I0_O JLUT2Xhzf> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy Jnet (fo=2, routed)XhA> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/I1 JXhzf i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/OProp_D5LUT_SLICEM_I1_O JLUT3Xhzr|> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en Jnet (fo=4, routed)Xh> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/I0 JXhzr i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/OProp_G6LUT_SLICEM_I0_O JLUT4XhzrZd> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena Jnet (fo=38, routed)Xh? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2] JRAMB36E2Xhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk Jnet (fo=1684, routed)XhI@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C JFDREXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh^L>@ Jclock uncertaintyXh i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg(Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[2] JRAMB36E2Xhsh1/ JXh< J required timeXhXgA; J arrival timeXhҹ/ JXh4 JslackXho A1  tx_wordclk tx_wordclk!)M@1M @9AM@IM @e/+>hq}<D8>NN rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuX->} ^俍\:=\?\?<*v=5^=/>X?~j>t?c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/Q[6] Jnet (fo=12, routed)Xhʡ= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[4]_i_1__122/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[4]_i_1__122/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[4] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]/D JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh\?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh\?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh* g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ^俐; J arrival timeXh'1?/ JXh4 JslackXh< {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[88]/Cieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT4=1 MUXF7=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuc>}t㿍-⿭\I>o?-?<zj<n>)\>/>#ۉ?~j>o?c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[88]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/data4[8] Jnet (fo=1, routed)XhI > njg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[8]_i_3__20/I0 JXhzr mig_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[8]_i_3__20/OProp_A6LUT_SLICEM_I0_O JLUT4Xhzrrh= okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[8]_i_3__20_n_0 Jnet (fo=1, routed)Xh rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]_i_1__20/I1 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]_i_1__20/OProp_F7MUX_AB_SLICEM_I1_O JMUXF7Xhzrj< sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]_i_1__20_n_0 Jnet (fo=1, routed)XhT< ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]/D JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xho?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[88]/C JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh-?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]/C JFDCEXhzr> Jclock pessimismXhzj< gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXht㿐; J arrival timeXhK?/ JXh4 JslackXh<Cg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ (CARRY8=3)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsunm>}ۿIܿ>?I?<}-2>im=/>r?~j>/?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[3]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg_n_0_[3] Jnet (fo=1, routed)XhD= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1__23/S[3] JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1__23/CO[7]Prop_CARRY8_SLICEL_S[3]_CO[7] JCARRY8Xhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1__23_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__23/CI JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__23/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__23_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__23/CI JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__23/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__23_n_15 Jnet (fo=1, routed)Xh #< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[3]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27445, routed)XhI?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]/C JFDREXhzr> Jclock pessimismXh} g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhۿ; J arrival timeXh*\?/ JXh4 JslackXh< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[3]/C{wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZbL Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5j3tx_wordclk rise@41.585ns - tx_wordclk rise@41.585nsuj>}6d;>f@d;@*<D{=>S?$@?+G@c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[3]/QProp_GFF_SLICEL_C_Q JFDCEXhzr= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/TX_FRAME_I[80] Jnet (fo=15, routed)Xh> {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]/D JFDCEXhzrN J(clock tx_wordclk rise edge)Xhzr W&BO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhf@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzrN J(clock tx_wordclk rise edge)Xhzr W&BO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xhd;@X2Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]/C JFDCEXhzr> Jclock pessimismXhD{ yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]Hold_GFF_SLICEL_C_D JFDCEXh>/ JXh< J required timeXh6; J arrival timeXh_6B/ JXh4 JslackXh*< !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_20/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu>}}c<=i?c?{<>?,=u=/>;H?~j>q?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr9H=\ fabric_clk_div2_q[3] Jnet (fo=70, routed)XhX94=L TX_CLKEN_i_1_replica_20/I0 JXhzrm TX_CLKEN_i_1_replica_20/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzro<_ TX_CLKEN_i_1_n_0_repN_20 Jnet (fo=1, routed)Xho<O TX_CLKEN_reg_replica_20/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xhi?X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xhc?X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_20/C JFDREXhzr> Jclock pessimismXh>?,e TX_CLKEN_reg_replica_20Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh}; J arrival timeXhi?/ JXh4 JslackXh{<F1g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/C|xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZbL Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5j3tx_wordclk rise@41.585ns - tx_wordclk rise@41.585nsu(>}6l,̿=sh??v< 9H=i=/>Nbp?~j>ҍ?c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/TX_FRAME_I[74] Jnet (fo=9, routed)Xhi= |xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]/D JFDCEXhzrN J(clock tx_wordclk rise edge)Xhzr W&BO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhsh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzrN J(clock tx_wordclk rise edge)Xhzr W&BO tx_wordclk_bufg/O JBUFGCEXhzr b^g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]/C JFDCEXhzr> Jclock pessimismXh  zvg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh6l,; J arrival timeXhE,B/ JXh4 JslackXhv<  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu +>}X׿T忭Ҥ=+?T?%<w(9H==/>O?~j>Ȧ?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21] Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27445, routed)Xh+?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27445, routed)XhT?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]/C JFDREXhzr> Jclock pessimismXhw( g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]Hold_AFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhX׿; J arrival timeXhl?/ JXh4 JslackXh%<g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[2]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT6=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu{?5>}.ֿ!⿭3=t?!?~<cʡ=9=/>p=?~j>?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[2]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst/Q[2] Jnet (fo=16, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst/rxuserrdy_out_i_1/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst/rxuserrdy_out_i_1/OProp_D6LUT_SLICEL_I0_O JLUT6Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1 Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_clk_freerun_in[0] Jnet (fo=27445, routed)Xht?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[2]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_clk_freerun_in[0] Jnet (fo=27445, routed)Xh!?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg/C JFDREXhzr> Jclock pessimismXhc g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_regHold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh.ֿ; J arrival timeXh?/ JXh4 JslackXh~<gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address_reg[2]/Cieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ (MUXF7=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu>}mOmĠ>Q@Om@<;E6>+>S?@?&@c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address_reg[2]/QProp_DFF2_SLICEM_C_Q JFDCEXhzrl= a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address[2] Jnet (fo=21, routed)Xh:> plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]_i_1__6/S JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]_i_1__6/OProp_F7MUX_CD_SLICEM_S_O JMUXF7XhzrGa= rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]_i_1__6_n_0 Jnet (fo=1, routed)Xh/< ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]/D JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhQ@X2Y4 (CLOCK_ROOT) gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address_reg[2]/C JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhOm@X2Y4 (CLOCK_ROOT) ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]/C JFDCEXhzr> Jclock pessimismXh; gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]Hold_DFF_SLICEM_C_D JFDCEXhI >/ JXh< J required timeXhm; J arrival timeXho@/ JXh4 JslackXh<vg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/D"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu~>}E~l>L7i@~@<C l=>S?P'@?,=@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3_reg/QProp_CFF2_SLICEM_C_Q JFDREXhzrl= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3 Jnet (fo=1, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_clk_freerun_in[0] Jnet (fo=27445, routed)XhL7i@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3_reg/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_clk_freerun_in[0] Jnet (fo=27445, routed)Xh~@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C JFDREXhzr> Jclock pessimismXhC  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_regHold_EFF_SLICEM_C_D JFDREXh>/ JXh< J required timeXhE; J arrival timeXhC@/ JXh4 JslackXh< TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuS@}oA8Ai>^@i@oA=А=$WN>/+>_9=V>H@?|@S? (@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ɾ%i@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)XhH@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]/CE JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhi@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXhɾ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh8A; J arrival timeXh)\5/ JXh4 JslackXh/+>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuS@}oA8Ai>^@i@oA=А=$WN>/+>_9=V>H@?|@S? (@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ɾ%i@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)XhH@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/CE JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhi@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/C JFDPEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXhɾ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]Setup_FFF_SLICEL_C_CE JFDPEXhGa/ JXh< J required timeXh8A; J arrival timeXh)\5/ JXh4 JslackXh/+>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuS@}oA8Ai>^@i@oA=А=$WN>/+>_9=V>H@?|@S? (@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ɾ%i@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)XhH@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]/CE JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhi@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXhɾ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh8A; J arrival timeXh)\5/ JXh4 JslackXh/+>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu[d@}oA$8AMjG7>^@Mj@oA=А=$WN>M0>_9=V>@?|@S?ף(@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3^ʾ%Mj@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)Xh@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/CE JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhMj@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh3^ʾ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh$8A; J arrival timeXh[d5/ JXh4 JslackXhM0>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu[d@}oA$8AMjG7>^@Mj@oA=А=$WN>M0>_9=V>@?|@S?ף(@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3^ʾ%Mj@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)Xh@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]/CE JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhMj@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]/C JFDPEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh3^ʾ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]Setup_GFF_SLICEM_C_CE JFDPEXhGa/ JXh< J required timeXh$8A; J arrival timeXh[d5/ JXh4 JslackXhM0>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu[d@}oA$8AMjG7>^@Mj@oA=А=$WN>M0>_9=V>@?|@S?ף(@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3^ʾ%Mj@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)Xh@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/CE JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhMj@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh3^ʾ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh$8A; J arrival timeXh[d5/ JXh4 JslackXhM0>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu{@}oA_7Ahu>^@h@oA=А=$WN>B>_9=V>ˡ@?|@S?&@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 7Ⱦ%h@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)Xhˡ@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]/CE JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhh@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh7Ⱦ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh_7A; J arrival timeXhk4/ JXh4 JslackXhB>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu{@}oA_7Ahu>^@h@oA=А=$WN>B>_9=V>ˡ@?|@S?&@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 7Ⱦ%h@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)Xhˡ@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/CE JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhh@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh7Ⱦ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh_7A; J arrival timeXhk4/ JXh4 JslackXhB>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuw@}oAQ7ANbh;s>^@Nbh@oA=А=$WN>]>_9=V>K@?|@S?R&@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `Ⱦ%Nbh@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)XhK@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]/CE JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhNbh@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]/C JFDPEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh`Ⱦ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]Setup_HFF_SLICEM_C_CE JFDPEXhGa/ JXh< J required timeXhQ7A; J arrival timeXhi3/ JXh4 JslackXh]>^ TX_CLKEN_reg_replica_45/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/CE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuw@}oAQ7ANbh;s>^@Nbh@oA=А=$WN>]>_9=V>K@?|@S?R&@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `Ⱦ%Nbh@-S?5j TX_CLKEN_reg_replica_45/QProp_FFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias Jnet (fo=94, routed)XhK@D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/CE JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh^@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_45/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhNbh@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/C JFDPEXhzr> Jclock pessimismXh_9=E Jinter-SLR compensationXh`Ⱦ@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]Setup_GFF_SLICEM_C_CE JFDPEXhGa/ JXh< J required timeXhQ7A; J arrival timeXhi3/ JXh4 JslackXh]>^ ipb_clkclk250!)/@1?@9A?I@ex(?hq}"="DB rise - rise rise - rise  T #ctrl_regs_inst/regs_reg[7][3]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu?>}f ;^:>F? ?Q>А=>==D=>p=>bX?">9?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q #ctrl_regs_inst/regs_reg[7][3]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[3] Jnet (fo=2, routed)Xh>h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)XhF?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #ctrl_regs_inst/regs_reg[7][3]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh ?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhf; J arrival timeXh%?/ JXh4 JslackXh=T #ctrl_regs_inst/regs_reg[7][2]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsuK ?}1̜@H>F?̜?Q>А=>=XQ=D=>p=>bX?"> h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)XhF?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #ctrl_regs_inst/regs_reg[7][2]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh̜?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1; J arrival timeXhk?/ JXh4 JslackXhXQ=T #ctrl_regs_inst/regs_reg[7][1]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu'1?}̜"/]>&?̜?Q>А=>=_e=9H=K>p=>R?"> h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh&?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #ctrl_regs_inst/regs_reg[7][1]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh̜?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh}??/ JXh4 JslackXh_e=U #ctrl_regs_inst/regs_reg[7][6]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu ?} F ϡE>M? ?Q>А=>=U=D=>p=>}?U?">9?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q #ctrl_regs_inst/regs_reg[7][6]/QProp_CFF2_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[6] Jnet (fo=2, routed)Xh>h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)XhM?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #ctrl_regs_inst/regs_reg[7][6]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh ?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh F; J arrival timeXh?/ JXh4 JslackXhU= %!stat_regs_inst/ipb_clk_div2_reg/C'#stat_regs_inst/ipb_clk_div2_r_reg/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsun?}+ƛL>-?ƛ?Q>А=>==D=$?p=>T?">:?b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)r %!stat_regs_inst/ipb_clk_div2_reg/QProp_HFF_SLICEL_C_Q JFDREXhzrD=b stat_regs_inst/ipb_clk_div2 Jnet (fo=3, routed)Xh$?Y '#stat_regs_inst/ipb_clk_div2_r_reg/D JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv stat_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh-?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]W %!stat_regs_inst/ipb_clk_div2_reg/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17693, routed)Xhƛ?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]Y '#stat_regs_inst/ipb_clk_div2_r_reg/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>o %!stat_regs_inst/ipb_clk_div2_r_regHold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh+; J arrival timeXhZd?/ JXh4 JslackXh=U #ctrl_regs_inst/regs_reg[7][4]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsub?}̜T>-?̜?Q>А=>=">D= ?p=>T?"> 1]U #ctrl_regs_inst/regs_reg[7][4]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh̜?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh?5?/ JXh4 JslackXh">Y $ ctrl_regs_inst/regs_reg[7][30]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu/?}1̜T>-?̜?Q>А=>=>D=`?p=>T?"> 1]V $ ctrl_regs_inst/regs_reg[7][30]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh̜?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1; J arrival timeXh?/ JXh4 JslackXh>S #ctrl_regs_inst/regs_reg[7][8]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu?5?}1̜F W>?̜?Q>А=>=>9H=?p=>zT?"> 1]U #ctrl_regs_inst/regs_reg[7][8]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh̜?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1; J arrival timeXh%?/ JXh4 JslackXh>U #ctrl_regs_inst/regs_reg[7][7]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsuT%?}1̜S>M?̜?Q>А=>=n8>D=?p=>}?U?"> 1]U #ctrl_regs_inst/regs_reg[7][7]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh̜?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1; J arrival timeXh}??/ JXh4 JslackXhn8>W $ ctrl_regs_inst/regs_reg[7][29]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu9(?}󓾿/bX>-?/?Q>А=>=Ù?>D=j?p=>T?">p=?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)r $ ctrl_regs_inst/regs_reg[7][29]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[9] Jnet (fo=2, routed)Xhj?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh-?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][29]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh/?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh󓾿; J arrival timeXh+?/ JXh4 JslackXhÙ?>U #ctrl_regs_inst/regs_reg[7][0]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZj*clk250 rise@4.000ns - ipb_clk rise@0.000nsu@}@@C#l羵'1@@C#@@Q>А=>=x(?I >~j? ?(@?p?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)q #ctrl_regs_inst/regs_reg[7][0]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrI >x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[0] Jnet (fo=2, routed)Xh~j?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]U #ctrl_regs_inst/regs_reg[7][0]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)XhC#@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]Setup_EFF_SLICEL_C_D JFDCEXho=/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXhx(?Z %!stat_regs_inst/ipb_clk_div2_reg/C*&stat_regs_inst/clk_phase_reg[2]_srl3/D"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT2=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuА=>=1G?l>? ?أ@??b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})a(rising edge-triggered cell SRL16E clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r %!stat_regs_inst/ipb_clk_div2_reg/QProp_HFF_SLICEL_C_Q JFDREXhzrO >b stat_regs_inst/ipb_clk_div2 Jnet (fo=3, routed)Xh)\?] /+stat_regs_inst/clk_phase_reg[2]_srl3_i_1/I0 JXhzr~ .*stat_regs_inst/clk_phase_reg[2]_srl3_i_1/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzr7A>` stat_regs_inst/p_1_out[0] Jnet (fo=1, routed)XhO ?^ *&stat_regs_inst/clk_phase_reg[2]_srl3/D JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv stat_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh<@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]W %!stat_regs_inst/ipb_clk_div2_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17693, routed)XhH"@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]` ,(stat_regs_inst/clk_phase_reg[2]_srl3/CLK JSRL16EXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQy ($stat_regs_inst/clk_phase_reg[2]_srl3Setup_A6LUT_SLICEM_CLK_D JSRL16EXhGa/ JXh< J required timeXh@; J arrival timeXhM/ JXh4 JslackXh1G? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu?}@@-" '1@@-"@@Q>А=>=?\B>n? ?(@?C?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhX>i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh-"@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh@; J arrival timeXhȖ/ JXh4 JslackXh? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu3^?}@@-" '1@@-"@@Q>А=>=U?\B>J ? ?(@?C?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh>i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh-"@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh@; J arrival timeXh / JXh4 JslackXhU? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuC?}@Zi@Zd#hf澵'1@@Zd#@@Q>А=>=շ?\B>Y9? ?(@?.?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhA?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)XhZd#@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhZi@; J arrival timeXhd;/ JXh4 JslackXhշ? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuv?}@fk@!_9'1@@!@@Q>А=>=?\B>$? ?(@?p=?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh'1>i 73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)Xh!@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhfk@; J arrival timeXhF/ JXh4 JslackXh? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu6?}@38@C#l羵'1@@C#@@Q>А=>=F?\B>L7? ?(@?p?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xhz>i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)XhC#@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh38@; J arrival timeXhz/ JXh4 JslackXhF? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu6?}@38@C#l羵'1@@C#@@Q>А=>=F?\B>L7? ?(@?p?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xhz>i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)XhC#@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh38@; J arrival timeXhz/ JXh4 JslackXhF? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu6?}@38@C#l羵'1@@C#@@Q>А=>=F?\B>L7? ?(@?p?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xhz>i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)XhC#@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh38@; J arrival timeXhz/ JXh4 JslackXhF? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE"$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT:X2Y6BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu6?}@38@C#l羵'1@@C#@@Q>А=>=F?\B>L7? ?(@?p?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)r $ ctrl_regs_inst/regs_reg[7][31]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_E6LUT_SLICEM_I1_O JLUT3Xhzr`P=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xhz>i 73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrv ctrl_regs_inst/ipb_clk Jnet (fo=204768, routed)Xh'1@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17693, routed)XhC#@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]Setup_HFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh38@; J arrival timeXhz/ JXh4 JslackXhF? clk250ipb_clk!)?1@9A/@I?@e9 ?hq}6<6BD rise - rise rise - rise  =9g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg[33]/C;7g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsun?}cvN?)@vN@Q>А=>=<l=)\O??G? ?n*@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) =9g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg[33]/QProp_HFF_SLICEM_C_Q JFDREXhzrl= @1]o =9g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg[33]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 40g_clock_rate_din[5].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)XhvN@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 95g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33]Hold_HFF2_SLICEL_C_D JFDREXho>/ JXh< J required timeXhc; J arrival timeXh-e@/ JXh4 JslackXh< <8g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg[3]/C:6g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}?#ۙ^d;>n?#ۙ?Q>А=>=֨<9H=>>?R>~?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) <8g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg[3]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H= ?;g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg_n_0_[3] Jnet (fo=1, routed)Xh>l :6g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 3/g_clock_rate_din[3].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhn?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg[3]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 40g_clock_rate_din[3].i_rate_ngccm_status0/ipb_clk Jnet (fo=204768, routed)Xh#ۙ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 84g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]Hold_HFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh?; J arrival timeXh?/ JXh4 JslackXh֨< >:g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg[18]/C<8g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu53>}/sVj<>?V?Q>А=>=<9H=>>?R>!?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg[18]/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= A=g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg_n_0_[18] Jnet (fo=1, routed)Xh>n <8g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[14].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg[18]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[14].i_rate_ngccm_status0/ipb_clk Jnet (fo=204768, routed)XhV?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh/s; J arrival timeXhM?/ JXh4 JslackXh< >:g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[33]/C<8g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}ſZG>Zd?Z?Q>А=>=<9H=w>>T%?R>?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[33]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg_n_0_[33] Jnet (fo=1, routed)Xhw>n <8g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[18].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)XhZd?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[33]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[18].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)XhZ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]Hold_FFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhſ; J arrival timeXh?/ JXh4 JslackXh< >:g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg[46]/C<8g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu4^>}ſK>"??Q>А=>=<9H=G>>B`%?R>q=?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg[46]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg_n_0_[46] Jnet (fo=1, routed)XhG>n <8g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[19].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xh"?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg[46]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[19].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXhſ; J arrival timeXh^?/ JXh4 JslackXh< >:g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg[14]/C<8g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsuC>}O/>l?O?Q>А=>=<9H=t>>?R>?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg[14]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= A=g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg_n_0_[14] Jnet (fo=1, routed)Xht>n <8g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[21].i_rate_ngccm_status0/clk250 Jnet (fo=17693, routed)Xhl?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg[14]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[21].i_rate_ngccm_status0/ipb_clk Jnet (fo=204768, routed)XhO?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh\?/ JXh4 JslackXh< 95g_clock_rate_din[34].i_rate_test_comm/rate_i_reg[7]/C73g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}/sοW>#ۙ?W?Q>А=>=<9H=:>>B?R>!?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) 95g_clock_rate_din[34].i_rate_test_comm/rate_i_reg[7]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= <8g_clock_rate_din[34].i_rate_test_comm/rate_i_reg_n_0_[7] Jnet (fo=1, routed)Xh:>i 73g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 0,g_clock_rate_din[34].i_rate_test_comm/clk250 Jnet (fo=17693, routed)Xh#ۙ?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]k 95g_clock_rate_din[34].i_rate_test_comm/rate_i_reg[7]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[34].i_rate_test_comm/ipb_clk Jnet (fo=204768, routed)XhW?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 51g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh/sο; J arrival timeXhM?/ JXh4 JslackXh< >:g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg[37]/C<8g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu >}CX->ˡ?C?Q>А=>=<9H=>>5^?R>a?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg[37]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg_n_0_[37] Jnet (fo=1, routed)Xh>n <8g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[40].i_rate_ngccm_status1/clk250 Jnet (fo=17693, routed)Xhˡ?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg[37]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[40].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)XhC?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh; J arrival timeXhMb?/ JXh4 JslackXh< >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[14]/C<8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsuw>}׹u+1>P?u?Q>А=>=<D=>>?5?R>j|?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[14]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD= A=g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg_n_0_[14] Jnet (fo=1, routed)Xh>n <8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[43].i_rate_ngccm_status1/clk250 Jnet (fo=17693, routed)XhP?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[14]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[43].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)Xhu?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]Hold_FFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXh׹; J arrival timeXh.?/ JXh4 JslackXh< >:g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg[20]/C<8g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsux>}"(>?"?Q>А=>=<9H=Mb>>"?R>Ā?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg[20]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg_n_0_[20] Jnet (fo=1, routed)XhMb>n <8g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[47].i_rate_ngccm_status1/clk250 Jnet (fo=17693, routed)Xh?X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg[20]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[47].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)Xh"?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]Hold_FFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXh< =9g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg[24]/C;7g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuY9<@}@ Bh%Q8@Ah%@BQ>А=>=9 ?V>S3@}??[d?/?Z@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg[24]/QProp_EFF_SLICEM_C_Q JFDREXhzrV> @1]o =9g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg[24]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 40g_clock_rate_din[1].i_rate_ngccm_status0/ipb_clk Jnet (fo=204768, routed)Xhh%@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24]Setup_EFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXh B; J arrival timeXhH/ JXh4 JslackXh9 ? =9g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg[7]/C;7g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsush9@}@! BE&rS;@AE&@BQ>А=>="?V>0@}??sh?/?V@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg[7]/QProp_BFF_SLICEL_C_Q JFDREXhzrV> @1]o =9g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg[7]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[30].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)XhE&@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7]Setup_BFF2_SLICEM_C_D JFDREXh+=/ JXh< J required timeXh! B; J arrival timeXhK/ JXh4 JslackXh"? =9g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg[5]/C;7g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu 8@}@ B$:@A$@BQ>А=>=C#?O >K/@}??A?/?F@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg[5]/QProp_FFF2_SLICEM_C_Q JFDREXhzrO > @1]o =9g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg[5]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[36].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)Xh$@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5]Setup_DFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh B; J arrival timeXh./ JXh4 JslackXhC#? >:g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg[36]/C<8g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu+7@}@ B$E;@A$@BQ>А=>=$?)\>?5.@}???/?@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg[36]/QProp_AFF_SLICEM_C_Q JFDREXhzr)\> A=g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg_n_0_[36] Jnet (fo=1, routed)Xh?5.@n <8g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[34].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)Xh;@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg[36]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[34].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)Xh$@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh B; J arrival timeXh,/ JXh4 JslackXh$? >:g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[12]/C<8g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu0<@}@ Bt3jD@At3@BQ>А=>=c8(?V>"3@}???/?q=@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[12]/QProp_AFF2_SLICEM_C_Q JFDREXhzrV> A=g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg_n_0_[12] Jnet (fo=1, routed)Xh"3@n <8g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[22].i_rate_ngccm_status1/clk250 Jnet (fo=17693, routed)XhjD@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[12]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[22].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)Xht3@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]Setup_GFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXh B; J arrival timeXh+/ JXh4 JslackXhc8(? 95g_clock_rate_din[42].i_rate_test_comm/rate_i_reg[7]/C73g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu0@}@A BX9پzT@AX9@BQ>А=>=+?V>b(@}??# @/? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 95g_clock_rate_din[42].i_rate_test_comm/rate_i_reg[7]/QProp_FFF_SLICEM_C_Q JFDREXhzrV> <8g_clock_rate_din[42].i_rate_test_comm/rate_i_reg_n_0_[7] Jnet (fo=1, routed)Xhb(@i 73g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 0,g_clock_rate_din[42].i_rate_test_comm/clk250 Jnet (fo=17693, routed)XhzT@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]k 95g_clock_rate_din[42].i_rate_test_comm/rate_i_reg[7]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[42].i_rate_test_comm/ipb_clk Jnet (fo=204768, routed)XhX9@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 51g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]Setup_GFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXhA B; J arrival timeXh W/ JXh4 JslackXh+? >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[17]/C<8g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu;@}@ BC39tC@AC3@BQ>А=>=,?V>2@}???/?I @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[17]/QProp_GFF_SLICEL_C_Q JFDREXhzrV> A=g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg_n_0_[17] Jnet (fo=1, routed)Xh2@n <8g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[10].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)XhtC@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[17]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[10].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)XhC3@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]Setup_EFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXh B; J arrival timeXh/ JXh4 JslackXh,? >:g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[28]/C<8g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuK :@}@ɜ BH2ƋZD@AH2@BQ>А=>=-?V>&1@}??t?/?@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[28]/QProp_CFF2_SLICEM_C_Q JFDREXhzrV> A=g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg_n_0_[28] Jnet (fo=1, routed)Xh&1@n <8g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[18].i_rate_ngccm_status2/clk250 Jnet (fo=17693, routed)XhZD@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[28]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[18].i_rate_ngccm_status2/ipb_clk Jnet (fo=204768, routed)XhH2@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]Setup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhɜ B; J arrival timeXhf/ JXh4 JslackXh-? >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[15]/C<8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu}?5@}@ B$|n:@A$@BQ>А=>=0?O >j,@}???/?t@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[15]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > A=g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg_n_0_[15] Jnet (fo=1, routed)Xhj,@n <8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[43].i_rate_ngccm_status1/clk250 Jnet (fo=17693, routed)Xhn:@X2Y6 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[15]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[43].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)Xh$@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]Setup_DFF2_SLICEL_C_D JFDREXhL7=/ JXh< J required timeXh B; J arrival timeXh/ JXh4 JslackXh0? =9g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[2]/C;7g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2]/D"$RCLK_CLEL_R_L_X46Y449/CLK_VDISTR_BOT*X2Y62$RCLK_CLEL_R_L_X32Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsup3@}@ B~":@A~"@BQ>А=>=%.1?O >q=*@}???/?G@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[2]/QProp_CFF_SLICEM_C_Q JFDREXhzrO > @1]o =9g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[2]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 51g_clock_rate_din[34].i_rate_ngccm_status1/ipb_clk Jnet (fo=204768, routed)Xh~"@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh B; J arrival timeXh/ JXh4 JslackXh%.1?  fabric_clk tx_wordclk!)Ë>(@1Ë>8@9AM@IM @e@hq}`<CN rise - rise rise - rise  -)SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[52]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuŸ?}p33ӿ>?33?}>А={>=`<=?L7>j|?~j>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[52]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] Jnet (fo=1, routed)XhX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[10]_i_1__233/I1 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[10]_i_1__233/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[27].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[52]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh33?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]Hold_DFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXhp; J arrival timeXh?/ JXh4 JslackXh`<,(SFP_GEN[9].ngCCM_gbt/TX_Word_o_reg[29]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu*?} /ݿ~>\?/?}>А={>=R<`=ף?L7>A?~j>|?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) y ,(SFP_GEN[9].ngCCM_gbt/TX_Word_o_reg[29]/QProp_EFF_SLICEM_C_Q JFDREXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] Jnet (fo=1, routed)Xhh ? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[8]_i_1__64/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[8]_i_1__64/OProp_A6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[8] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[9].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh\?X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[9].ngCCM_gbt/TX_Word_o_reg[29]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh/?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]Hold_AFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh ; J arrival timeXh@/ JXh4 JslackXhR<,(SFP_GEN[8].ngCCM_gbt/TX_Word_o_reg[70]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuC+?}꿭>w??}>А={>=ɑ<A`=?L7>p?~j>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) y ,(SFP_GEN[8].ngCCM_gbt/TX_Word_o_reg[70]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[7] Jnet (fo=1, routed)Xh ? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[7]_i_1__62/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[7]_i_1__62/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzro= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[7] Jnet (fo=1, routed)Xhu< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[8].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhw?X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[8].ngCCM_gbt/TX_Word_o_reg[70]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh @/ JXh4 JslackXhɑ<U-)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[56]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu/$?}⿭S>"??}>А={>=ɑ<=C ?L7>Ԉ?~j>G?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[56]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_DATA_I[12] Jnet (fo=1, routed)Xh+? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[14]_i_1__125/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[14]_i_1__125/OProp_H6LUT_SLICEL_I0_O JLUT3XhzrT= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[14] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[22].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh"?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[56]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]Hold_HFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh@/ JXh4 JslackXhɑ<\-)SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu233?} Zd>w??}>А={>=ɑ<l=E?L7>p?~j>|?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[18]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[18] Jnet (fo=1, routed)Xh-? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[18]_i_1__159/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[18]_i_1__159/OProp_C6LUT_SLICEL_I2_O JLUT3Xhzro= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[18] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[13].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhw?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[18]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXh @/ JXh4 JslackXhɑ<R,(SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu+?}m ￭C>??}>А={>=ɑ<v=?L7>?~j>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z ,(SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[2]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[2] Jnet (fo=1, routed)Xh ? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[2]_i_1__143/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[2]_i_1__143/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[2] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[16].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]^ ,(SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[2]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhm ; J arrival timeXh @/ JXh4 JslackXhɑ<]-)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[55]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu?}M⿭>M?M?}>А={>=ɑ<A`=>L7>?~j>43?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[55]/QProp_FFF2_SLICEM_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[11] Jnet (fo=1, routed)Xhx> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[13]_i_1__129/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[13]_i_1__129/OProp_D6LUT_SLICEL_I1_O JLUT3Xhzro= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[19].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhM?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[55]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhM?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]Hold_DFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh,@/ JXh4 JslackXhɑ<[-)SFP_GEN[21].ngCCM_gbt/TX_Word_o_reg[64]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuI "?}A߿>X??}>А={>=ɑ<l=?L7>> ?~j>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[21].ngCCM_gbt/TX_Word_o_reg[64]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[1] Jnet (fo=2, routed)Xh%? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[20]_i_1__162/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[20]_i_1__162/OProp_C6LUT_SLICEL_I1_O JLUT5Xhzro= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[20] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[21].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[21].ngCCM_gbt/TX_Word_o_reg[64]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhA; J arrival timeXh/@/ JXh4 JslackXhɑ<d-)SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[52]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu|?}7w2ܿ>> ?2?}>А={>=ɑ<A`=?L7>k?~j>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[52]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] Jnet (fo=1, routed)Xhp> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[10]_i_1__241/I1 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[10]_i_1__241/OProp_C6LUT_SLICEL_I1_O JLUT3Xhzro= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[35].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh> ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[52]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh2?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]Hold_CFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh7w; J arrival timeXhZd@/ JXh4 JslackXhɑ<-)SFP_GEN[29].ngCCM_gbt/TX_Word_o_reg[35]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu?}% &ѿq=>?&?}>А={>=ɑ<=K>L7>vx?~j>J ?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[29].ngCCM_gbt/TX_Word_o_reg[35]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[14] Jnet (fo=1, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[14]_i_1__224/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[14]_i_1__224/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzrt= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[14] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[29].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[29].ngCCM_gbt/TX_Word_o_reg[35]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh&?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]Hold_BFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh% ; J arrival timeXhl?/ JXh4 JslackXhɑ<t !fabric_clk_div2_reg_replica/C#fabric_clk_div2_q_reg[2]_srl3/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsu ;@}oA8E)A&A  lc@&A@oA}>А={>=@V>2@ף?#@S??e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell SRL16E clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) I%&A@-5o !fabric_clk_div2_reg_replica/QProp_AFF2_SLICEL_C_Q JFDREXhzrV>j &"fabric_clk_div2_bufg_place_replica Jnet (fo=51, routed)Xh2@D JXhSLR Crossing[1->0]W #fabric_clk_div2_q_reg[2]_srl3/D JSRL16EXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xhlc@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]S !fabric_clk_div2_reg_replica/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27445, routed)Xh&A@X2Y4 (CLOCK_ROOT)Y %!fabric_clk_div2_q_reg[2]_srl3/CLK JSRL16EXhzr> Jclock pessimismXhE Jinter-SLR compensationXhI羐@ Jclock uncertaintyXh}r !fabric_clk_div2_q_reg[2]_srl3Setup_A6LUT_SLICEM_CLK_D JSRL16EXhGa/ JXh< J required timeXh8E)A; J arrival timeXht/ JXh4 JslackXh@3Z,(SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsu/\@}oAN8AZԸq@Z@oA}>А={>=B>@>/D@ף?1@S?&@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z ,(SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/QProp_HFF2_SLICEM_C_Q JFDREXhzrI > g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[1] Jnet (fo=2, routed)XhB@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[20]_i_1__335/I1 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[20]_i_1__335/OProp_D6LUT_SLICEL_I1_O JLUT5XhzrFs> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[20] Jnet (fo=1, routed)Xh*\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[42].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhq@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]^ ,(SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhZ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]Setup_DFF_SLICEL_C_D JFDPEXh%=/ JXh< J required timeXhN8A; J arrival timeXhZd/ JXh4 JslackXhB>@-)SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[32]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuwW@}oAj8AGY ףm@GY@oA}>А={>=J@>K?@ף?p-@S?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z -)SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[32]/QProp_EFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[11] Jnet (fo=1, routed)Xh=@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[11]_i_1__232/I1 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[11]_i_1__232/OProp_B6LUT_SLICEM_I1_O JLUT3Xhzrx> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[11] Jnet (fo=1, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[27].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhm@X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[32]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhGY@X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]Setup_BFF_SLICEM_C_D JFDCEXh}=/ JXh< J required timeXhj8A; J arrival timeXh/ JXh4 JslackXhJ@V-)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[69]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuZdC@}oA=y7ApUHS{@pU@oA}>А={>=R@v>+@ף? ;@S?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) { -)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[69]/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[6] Jnet (fo=1, routed)XhK7)@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[6]_i_1__130/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[6]_i_1__130/OProp_C6LUT_SLICEL_I1_O JLUT3Xhzr֣p> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[6] Jnet (fo=1, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[19].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhS{@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[69]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhpU@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh=y7A; J arrival timeXh(\/ JXh4 JslackXhR@S,(SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuE@}oA8AC[{?q@C[@oA}>А={>=@~j>+7@ף?1@S?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z ,(SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/QProp_HFF2_SLICEM_C_Q JFDREXhzrI > g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[1] Jnet (fo=2, routed)Xh4@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[1]_i_1__287/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[1]_i_1__287/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[1] Jnet (fo=1, routed)Xh*\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[42].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhq@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]^ ,(SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhC[@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh8A; J arrival timeXh</ JXh4 JslackXh@V-)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[14]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuN@}oA`T=A/lM]y@/l@oA}>А={>=@X>l7@ף?qh9@S?33+@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) { -)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[14]/QProp_HFF2_SLICEM_C_Q JFDREXhzrI > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/TX_DATA_I[14] Jnet (fo=1, routed)Xh/5@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[14]_i_1__123/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[14]_i_1__123/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrgff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[14] Jnet (fo=1, routed)Xh*\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[22].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh]y@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[14]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xh/l@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh`T=A; J arrival timeXh(/ JXh4 JslackXh@^-)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[60]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsut3@}oA7AS/^4^z@S@oA}>А={>=7<@>H@ף?H :@S?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) { -)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[60]/QProp_EFF2_SLICEM_C_Q JFDREXhzrO > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[16] Jnet (fo=1, routed)Xh:@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[18]_i_1__129/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[18]_i_1__129/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzrl{> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[18] Jnet (fo=1, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[19].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh4^z@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[60]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhS@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]Setup_GFF_SLICEM_C_D JFDCEXho=/ JXh< J required timeXh7A; J arrival timeXhw/ JXh4 JslackXh7<@]-)SFP_GEN[41].ngCCM_gbt/TX_Word_o_reg[38]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuF@}oA=y3AEc吾W@E@oA}>А={>=ϗ@㥛>333@ף?K@S? @e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z -)SFP_GEN[41].ngCCM_gbt/TX_Word_o_reg[38]/QProp_HFF_SLICEM_C_Q JFDREXhzrO > g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[17] Jnet (fo=1, routed)Xh1@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[17]_i_1__308/I1 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[17]_i_1__308/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[17] Jnet (fo=1, routed)Xh+= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[41].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhW@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[41].ngCCM_gbt/TX_Word_o_reg[38]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]Setup_BFF_SLICEL_C_D JFDPEXh}=/ JXh< J required timeXh=y3A; J arrival timeXh"/ JXh4 JslackXhϗ@^-)SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[32]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuF@}oA~А={>=@v>.@ף?S;@S?G)@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) { -)SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[32]/QProp_HFF2_SLICEM_C_Q JFDREXhzrI > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[11] Jnet (fo=1, routed)Xhz,@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[11]_i_1__152/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[11]_i_1__152/OProp_C6LUT_SLICEL_I1_O JLUT3Xhzr֣p> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[11] Jnet (fo=1, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[14].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh{@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[32]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhj@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh~ W@B@oA}>А={>=͘@X>*@ף?S@S?r@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z ,(SFP_GEN[31].ngCCM_gbt/TX_Word_o_reg[7]/QProp_FFF2_SLICEM_C_Q JFDREXhzrO > g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[7] Jnet (fo=1, routed)XhQ(@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[7]_i_1__247/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[7]_i_1__247/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrA`e> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[7] Jnet (fo=1, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[31].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh> W@X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[31].ngCCM_gbt/TX_Word_o_reg[7]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)XhB@X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7]Setup_CFF_SLICEM_C_D JFDPEXh%=/ JXh< J required timeXh?2A; J arrival timeXhz/ JXh4 JslackXh͘@ **async_default**DRPclkDRPclk!)#@13@9A#@I3@e}vAhq}>d rise - rise rise - rise  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/Czvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu>}m绿>=A?m?> 8X9=u>8?'1>#ۙ?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/QProp_CFF_SLICEM_C_Q JFDREXhzfD= PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 Jnet (fo=2, routed)Xhw= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/I1 JXhzf QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh'> zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk Jnet (fo=4215, routed)XhA?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xhm?X2Y4 (CLOCK_ROOT) xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh 8 vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh>  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C{wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsue>}I !=A?I?M_> 7X9=V>u>8?'1>q=?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/QProp_CFF_SLICEM_C_Q JFDREXhzfD= PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 Jnet (fo=2, routed)Xhw= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/I1 JXhzf QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk Jnet (fo=4215, routed)XhA?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhI?X2Y4 (CLOCK_ROOT) yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXh 7 wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRemov_DFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhM_>  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C|xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsue>}I !=A?I?M_> 7X9=V>u>8?'1>q=?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/QProp_CFF_SLICEM_C_Q JFDREXhzfD= PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 Jnet (fo=2, routed)Xhw= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/I1 JXhzf QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.> |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk Jnet (fo=4215, routed)XhA?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhI?X2Y4 (CLOCK_ROOT) zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXh 7 xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRemov_AFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhM_>  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C|xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsue>}I !=A?I?M_> 7X9=V>u>8?'1>q=?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/QProp_CFF_SLICEM_C_Q JFDREXhzfD= PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 Jnet (fo=2, routed)Xhw= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/I1 JXhzf QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.> |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk Jnet (fo=4215, routed)XhA?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhI?X2Y4 (CLOCK_ROOT) zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXh 7 xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRemov_BFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhM_>  YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C|xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsue>}I !=A?I?M_> 7X9=V>u>8?'1>q=?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/QProp_CFF_SLICEM_C_Q JFDREXhzfD= PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 Jnet (fo=2, routed)Xhw= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/I1 JXhzf QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.> |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk Jnet (fo=4215, routed)XhA?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhI?X2Y4 (CLOCK_ROOT) zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXh 7 xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRemov_CFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhM_> /YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C{wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu ->}shӥ=?sh?(>Q [=8>u>Ȇ?'1>)\?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/QProp_FFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 Jnet (fo=2, routed)Xh-= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj<= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhX94> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xhsh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhQ  wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRemov_DFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXh(> *YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/Czvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu ->}shӥ=?sh?(>Q [=8>u>Ȇ?'1>)\?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/QProp_FFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 Jnet (fo=2, routed)Xh-= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj<= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhX94> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xhsh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhQ  vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRemov_AFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXh(> 3YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu ->}shӥ=?sh?(>Q [=8>u>Ȇ?'1>)\?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/QProp_FFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 Jnet (fo=2, routed)Xh-= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj<= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhX94> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xhsh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhQ  xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRemov_AFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXh(> 3YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu ->}shӥ=?sh?(>Q [=8>u>Ȇ?'1>)\?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/QProp_FFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 Jnet (fo=2, routed)Xh-= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj<= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhX94> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xhsh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhQ  xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRemov_BFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXh(> 3YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu ->}shӥ=?sh?(>Q [=8>u>Ȇ?'1>)\?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/QProp_FFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 Jnet (fo=2, routed)Xh-= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj<= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhX94> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xhsh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhQ  xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRemov_CFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXh(> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C|xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuA@}A'ܵA/-Wm"1D@/-@A =А=k>}vA$K>> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)Xhsh? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf|> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhV? |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xh/-@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXh$K>@ Jclock uncertaintyXh  xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRecov_DFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh'ܵA; J arrival timeXhE/ JXh4 JslackXh}vA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuA@}A'ܵA/-Wm"1D@/-@A =А=k>}vA$K>> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)Xhsh? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf|> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhV? }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xh/-@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXh$K>@ Jclock uncertaintyXh  yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRecov_AFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh'ܵA; J arrival timeXhE/ JXh4 JslackXh}vA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuA@}A'ܵA/-Wm"1D@/-@A =А=k>}vA$K>> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)Xhsh? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf|> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhV? }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xh/-@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXh$K>@ Jclock uncertaintyXh  yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRecov_BFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh'ܵA; J arrival timeXhE/ JXh4 JslackXh}vA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuA@}A'ܵA/-Wm"1D@/-@A =А=k>}vA$K>> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)Xhsh? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf|> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhV? }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xh/-@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXh$K>@ Jclock uncertaintyXh  yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRecov_CFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh'ܵA; J arrival timeXhE/ JXh4 JslackXh}vA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C{wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu1@}AصAV-Rt$1D@V-@A =А=k> vAk)K>>lw@t3?+@A`%?F@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/QProp_HFF_SLICEM_C_Q JFDREXhzfO > QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)Xhsh? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf|> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xhp? {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh1D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhV-@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhk)K>@ Jclock uncertaintyXh  wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRecov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXhصA; J arrival timeXhJ / JXh4 JslackXh vA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C|xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu5^@}A`AV.w23K@V.@A =А=k>xAI>Cl>u@t3?V@A`%?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 Jnet (fo=2, routed)Xh|? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xhj? |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh23K@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhV.@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhI>@ Jclock uncertaintyXh  xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRecov_DFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh`A; J arrival timeXh/ JXh4 JslackXhxA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu5^@}A`AV.w23K@V.@A =А=k>xAI>Cl>u@t3?V@A`%?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 Jnet (fo=2, routed)Xh|? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xhj? }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh23K@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhV.@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhI>@ Jclock uncertaintyXh  yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRecov_AFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh`A; J arrival timeXh/ JXh4 JslackXhxA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu5^@}A`AV.w23K@V.@A =А=k>xAI>Cl>u@t3?V@A`%?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 Jnet (fo=2, routed)Xh|? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xhj? }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh23K@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhV.@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhI>@ Jclock uncertaintyXh  yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRecov_BFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh`A; J arrival timeXh/ JXh4 JslackXhxA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu5^@}A`AV.w23K@V.@A =А=k>xAI>Cl>u@t3?V@A`%?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 Jnet (fo=2, routed)Xh|? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xhj? }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh23K@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)XhV.@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhI>@ Jclock uncertaintyXh  yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRecov_CFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh`A; J arrival timeXh/ JXh4 JslackXhxA ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C{wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X41Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuI @}ARA?5.23K@?5.@A =А=k>!xA;I>Cl>Ou@t3?V@A`%?/@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzfV> QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 Jnet (fo=2, routed)Xh|? SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzfj= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh"? {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr VRg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk Jnet (fo=4215, routed)Xh23K@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=4215, routed)Xh?5.@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh;I>@ Jclock uncertaintyXh  wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRecov_EFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhRA; J arrival timeXh/ JXh4 JslackXh!xA  **async_default** TTC_rxusrclk TTC_rxusrclk!)Ë>?1Ë>@9AË>?IË>@e,>hq} =d rise - rise rise - rise  M 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuF>}ڿw￭i(=?w? =q-9H=z>-2?Vm?lG?1?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] Jnet (fo=29, routed)Xhz> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 73i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)k 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr LHi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]/C JFDCEXhzr> Jclock pessimismXhq- WSi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhڿ; J arrival timeXhr?/ JXh4 JslackXh =L 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuK>}ڿ￭3F=?? =Ro-9H=>-2?Vm?lG?I?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] Jnet (fo=29, routed)Xh> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 73i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)k 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr LHi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]/C JFDCEXhzr> Jclock pessimismXhRo- WSi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhڿ; J arrival timeXh?/ JXh4 JslackXh =L 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuK>}ڿ￭3F=?? =Ro-9H=>-2?Vm?lG?I?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] Jnet (fo=29, routed)Xh> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 73i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)k 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr LHi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]/C JFDCEXhzr> Jclock pessimismXhRo- WSi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhڿ; J arrival timeXh?/ JXh4 JslackXh =M 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuK>}ڿ￭3F=?? =Ro-9H=>-2?Vm?lG?I?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] Jnet (fo=29, routed)Xh> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 73i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)k 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr LHi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]/C JFDCEXhzr> Jclock pessimismXhRo- WSi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhڿ; J arrival timeXh?/ JXh4 JslackXh =L 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuK>}ڿ￭3F=?? =Ro-9H=>-2?Vm?lG?I?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] Jnet (fo=29, routed)Xh> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 73i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)k 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr LHi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]/C JFDCEXhzr> Jclock pessimismXhRo- WSi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhڿ; J arrival timeXh?/ JXh4 JslackXh =L 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuK>}ڿ￭3F=?? =Ro-9H=>-2?Vm?lG?I?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= EAi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] Jnet (fo=29, routed)Xh> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 73i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT)k 95i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr LHi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]/C JFDCEXhzr> Jclock pessimismXhRo- WSi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhڿ; J arrival timeXh?/ JXh4 JslackXh =j d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CEAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsu>}33㿍V%>w?V?Y=jD=Zd>-2?Om?lG??e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)XhZd>w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xhw?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)XhV?X3Y2 (CLOCK_ROOT)u C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhj A=i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh33㿐; J arrival timeXhn?/ JXh4 JslackXhY=o d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CFBi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuҍ>}㿍Q>w?Q?<=jD=~j>-2?Om?lG? ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)Xh~j>x FBi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xhw?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)XhQ?X3Y2 (CLOCK_ROOT)v D@i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhj B>i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_regRemov_DFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㿐; J arrival timeXh53?/ JXh4 JslackXh<=s d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CGCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuҍ>}㿍Q>w?Q?<=jD=~j>-2?Om?lG? ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)Xh~j>y GCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xhw?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)XhQ?X3Y2 (CLOCK_ROOT)w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhj C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_regRemov_AFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㿐; J arrival timeXh53?/ JXh4 JslackXh<=s d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CGCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuҍ>}㿍Q>w?Q?<=jD=~j>-2?Om?lG? ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)Xh~j>y GCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xhw?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)XhQ?X3Y2 (CLOCK_ROOT)w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhj C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_regRemov_BFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㿐; J arrival timeXh53?/ JXh4 JslackXh<= \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@@X9l=w@X9l@G@=А=,>R>)\>3@Mb?l@V?V @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhX9l@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXhR>@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh,> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXhd>@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXhd>@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXhd>@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]Recov_FFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu<@}G@#!@jlE=w@jl@G@=А= >d>)\>3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh3@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXh > \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203]/CLR"$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X50Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsuj<@}G@#!@jlE=w@jl@G@=А=B#>d>)\>t3@Mb?l@V?}? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xht3@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhw@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXhd>@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh#!@; J arrival timeXh/ JXh4 JslackXhB#> **async_default**axi_c2c_phy_clkaxi_c2c_phy_clk!)6@16)@9A6@I6)@e]J*Ahq}A0>d rise - rise rise - rise  |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu >}rUYKw =lG?Kw?A0>#9H=>'>v>D>n?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhWM?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]/C JFDCEXhzr> Jclock pessimismXh# i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhrUY; J arrival timeXhv?/ JXh4 JslackXhA0>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu >}rUYKw =lG?Kw?A0>#9H=>'>v>D>n?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhWM?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]/C JFDCEXhzr> Jclock pessimismXh# i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhrUY; J arrival timeXhv?/ JXh4 JslackXhA0>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu5^>}P6]"{=lG?"{?ʎ>|9H=G>'>v>D>x?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhG> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhaP?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]/C JFDCEXhzr> Jclock pessimismXh| i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhP6]; J arrival timeXhM?/ JXh4 JslackXhʎ>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu5^>}P6]"{=lG?"{?ʎ>|9H=G>'>v>D>x?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhG> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhaP?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]/C JFDCEXhzr> Jclock pessimismXh| i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhP6]; J arrival timeXhM?/ JXh4 JslackXhʎ>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu5^>}P6]"{=lG?"{?ʎ>|9H=G>'>v>D>x?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhG> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhaP?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]/C JFDCEXhzr> Jclock pessimismXh| i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhP6]; J arrival timeXhM?/ JXh4 JslackXhʎ>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu5^>}P6]"{=lG?"{?ʎ>|9H=G>'>v>D>x?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhG> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhaP?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]/C JFDCEXhzr> Jclock pessimismXh| i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhP6]; J arrival timeXhM?/ JXh4 JslackXhʎ>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu5^>}P6]"{=lG?"{?ʎ>|9H=G>'>v>D>x?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhG> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhaP?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]/C JFDCEXhzr> Jclock pessimismXh| i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhP6]; J arrival timeXhM?/ JXh4 JslackXhʎ>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu5^>}P6]"{=lG?"{?ʎ>|9H=G>'>v>D>x?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhG> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhaP?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]/C JFDCEXhzr> Jclock pessimismXh| i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhP6]; J arrival timeXhM?/ JXh4 JslackXhʎ>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu>}g[Xy1=lG?Xy?錘>9H=l>'>v>D>?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xhl> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhO?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]/C JFDCEXhzr> Jclock pessimismXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhg[; J arrival timeXh ד?/ JXh4 JslackXh錘>|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZj;axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000nsu>}g[Xy1=lG?Xy?錘>9H=l>'>v>D>?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})f(removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Fast**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk(DCD - SCD - CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xhl> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xht< uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)XhL7)?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh)\= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhO?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]/C JFDCEXhzr> Jclock pessimismXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhg[; J arrival timeXh ד?/ JXh4 JslackXh錘>Xi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjV>d;?>?h>µ?i(rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> rni_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] Jnet (fo=144, routed)Xhd;? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> |i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C JFDPEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> |xi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh&?X5Y0 (CLOCK_ROOT) ~i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg/C JFDCEXhzr> Jclock pessimismXhRM>@ Jclock uncertaintyXh |i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_regRecov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhkwpA; J arrival timeXhZ/ JXh4 JslackXh]J*AIi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C}i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjV>d;?>?h>µ?i(rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> rni_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] Jnet (fo=144, routed)Xhd;? }i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> |i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C JFDPEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> |xi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh&?X5Y0 (CLOCK_ROOT) {i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg/C JFDCEXhzr> Jclock pessimismXhRM>@ Jclock uncertaintyXh }yi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_regRecov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhkwpA; J arrival timeXhZ/ JXh4 JslackXh]J*ARi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]/PRE"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjV>gf?>?h>T?i(rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> rni_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] Jnet (fo=144, routed)Xhgf? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]/PRE JFDPEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> |i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C JFDPEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> |xi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)XhG?X5Y0 (CLOCK_ROOT) }i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]/C JFDPEXhzr> Jclock pessimismXhOM>@ Jclock uncertaintyXh {i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]Recov_DFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhz{pA; J arrival timeXh$/ JXh4 JslackXh i+ARi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Ci_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjV>?>?h>ˡ?i(rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> rni_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] Jnet (fo=144, routed)Xh? i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> |i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C JFDPEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> |xi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh%?X5Y0 (CLOCK_ROOT) }i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]/C JFDCEXhzr> Jclock pessimismXh UM>@ Jclock uncertaintyXh {i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh^spA; J arrival timeXh҉/ JXh4 JslackXh+AHi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C}i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjV>?>?h>ˡ?i(rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> rni_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] Jnet (fo=144, routed)Xh? }i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> |i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh@X5Y0 (CLOCK_ROOT) i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C JFDPEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> |xi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk Jnet (fo=1684, routed)Xh%?X5Y0 (CLOCK_ROOT) {i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg/C JFDCEXhzr> Jclock pessimismXh UM>@ Jclock uncertaintyXh }yi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_regRecov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh^spA; J arrival timeXh҉/ JXh4 JslackXh+AI|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjI >n?>㥻?h><ߟ?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xhn? i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhC?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]/C JFDCEXhzr> Jclock pessimismXhXG>@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΡmA; J arrival timeXhףX/ JXh4 JslackXhx7AJ|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjI >n?>㥻?h><ߟ?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xhn? i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhC?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]/C JFDCEXhzr> Jclock pessimismXhXG>@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΡmA; J arrival timeXhףX/ JXh4 JslackXhx7AI|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjI >n?>㥻?h><ߟ?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xhn? i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhC?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]/C JFDCEXhzr> Jclock pessimismXhXG>@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΡmA; J arrival timeXhףX/ JXh4 JslackXhx7AJ|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjI >n?>㥻?h><ߟ?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)Xhn? i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)XhC?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]/C JFDCEXhzr> Jclock pessimismXhXG>@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΡmA; J arrival timeXhףX/ JXh4 JslackXhx7AJ|i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]/CLR"#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_R_X89Y89/CLK_VDISTR_BOT:X5Y0BJZjI >O?>㥻?h>G?i(rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})g(recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns})Slow**async_default**axi_c2c_phy_clkaxi_c2c_phy_clk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > ~zi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 Jnet (fo=19, routed)XhO? i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]/CLR JFDCEXhzf S J!(clock axi_c2c_phy_clk rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)Xh5^= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXhzr uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> MIi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) |i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C JFDCEXhzr S J!(clock axi_c2c_phy_clk rise edge)XhzrLA i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzr OKi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk Jnet (fo=3, routed)XhT= uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I JXh uqi_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> zvi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 Jnet (fo=1684, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhjmA; J arrival timeXh`P/ JXh4 JslackXh9A  **async_default**clk125clk125!)@1@9A@I@e0@hq})vk>)d rise - rise rise - rise   IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Cjfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuƋ>}~m˿\=?m?vk>Bd89H=B`e>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)XhB`e> jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=930, routed)Xhm?X2Y4 (CLOCK_ROOT) hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhBd8 fbi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh~; J arrival timeXh?/ JXh4 JslackXhvk> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Ckgi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuَ>}㵿I̿'=?I?0n>T89H=k>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)Xhk> kgi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=930, routed)XhI?X2Y4 (CLOCK_ROOT) iei_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhT8 gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_regRemov_DFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㵿; J arrival timeXhF?/ JXh4 JslackXh0n>! IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Clhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuَ>}㵿I̿'=?I?0n>T89H=k>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)Xhk> lhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=930, routed)XhI?X2Y4 (CLOCK_ROOT) jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhT8 hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_regRemov_AFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㵿; J arrival timeXhF?/ JXh4 JslackXh0n>! IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Clhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuَ>}㵿I̿'=?I?0n>T89H=k>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)Xhk> lhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=930, routed)XhI?X2Y4 (CLOCK_ROOT) jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhT8 hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_regRemov_BFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㵿; J arrival timeXhF?/ JXh4 JslackXh0n>! IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Clhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuَ>}㵿I̿'=?I?0n>T89H=k>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)Xhk> lhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=930, routed)XhI?X2Y4 (CLOCK_ROOT) jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhT8 hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_regRemov_CFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh㵿; J arrival timeXhF?/ JXh4 JslackXh0n> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Cfbi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu7^>}YWͿ=?W?Џ>vʡ=>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= KGi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 Jnet (fo=7, routed)Xhw= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in Jnet (fo=5, routed)XhS> fbi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=930, routed)XhW?X2Y4 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhv b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_regRemov_HFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhY; J arrival timeXh?/ JXh4 JslackXhЏ> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Ceai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu7^>}YWͿ=?W?Џ>vʡ=>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= KGi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 Jnet (fo=7, routed)Xhw= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in Jnet (fo=5, routed)XhS> eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=930, routed)XhW?X2Y4 (CLOCK_ROOT) c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhv a]i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhY; J arrival timeXh?/ JXh4 JslackXhЏ> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Cgci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu7^>}YWͿ=?W?Џ>vʡ=>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= KGi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 Jnet (fo=7, routed)Xhw= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in Jnet (fo=5, routed)XhS> gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=930, routed)XhW?X2Y4 (CLOCK_ROOT) eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhv c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_regRemov_EFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhY; J arrival timeXh?/ JXh4 JslackXhЏ> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Cgci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu7^>}YWͿ=?W?Џ>vʡ=>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= KGi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 Jnet (fo=7, routed)Xhw= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in Jnet (fo=5, routed)XhS> gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=930, routed)XhW?X2Y4 (CLOCK_ROOT) eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhv c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_regRemov_FFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhY; J arrival timeXh?/ JXh4 JslackXhЏ> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Cgci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu7^>}YWͿ=?W?Џ>vʡ=>v>&?L7>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_DFF2_SLICEL_C_Q JFDREXhzf9H= KGi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 Jnet (fo=7, routed)Xhw= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in Jnet (fo=5, routed)XhS> gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=930, routed)Xh?X2Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=930, routed)XhW?X2Y4 (CLOCK_ROOT) eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhv c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_regRemov_GFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhY; J arrival timeXh?/ JXh4 JslackXhЏ>g ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C]Yi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu`@}A+A 3eq@ 3@AY=А==0@ph=I> @z4?CD@ff&?p= @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.? ]Yi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=930, routed)Xh 3@X2Y4 (CLOCK_ROOT) [Wi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY YUi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRecov_DFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ / JXh4 JslackXh0@ k ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu`@}A+A 3eq@ 3@AY=А==0@ph=I> @z4?CD@ff&?p= @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.? ^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=930, routed)Xh 3@X2Y4 (CLOCK_ROOT) \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRecov_AFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ / JXh4 JslackXh0@ k ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu`@}A+A 3eq@ 3@AY=А==0@ph=I> @z4?CD@ff&?p= @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.? ^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=930, routed)Xh 3@X2Y4 (CLOCK_ROOT) \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRecov_BFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ / JXh4 JslackXh0@ k ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu`@}A+A 3eq@ 3@AY=А==0@ph=I> @z4?CD@ff&?p= @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.? ^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=930, routed)Xh 3@X2Y4 (CLOCK_ROOT) \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRecov_CFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ / JXh4 JslackXh0@ b ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C\Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu@}Aɹ+AF3ɡeq@F3@AY=А==@ph=I>l@z4?CD@ff&? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)XhI,? \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=930, routed)XhF3@X2Y4 (CLOCK_ROOT) ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY XTi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_regRecov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXhɹ+A; J arrival timeXh / JXh4 JslackXh@  ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Cc_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuV@}A+Al31dq@l3@AY=А==Q @ph=I>I@z4?CD@ff&?M @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)Xh)\? c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=930, routed)Xhl3@X2Y4 (CLOCK_ROOT) a]i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY _[i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_regRecov_DFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhQ @  ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Cd`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuV@}A+Al31dq@l3@AY=А==Q @ph=I>I@z4?CD@ff&?M @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)Xh)\? d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=930, routed)Xhl3@X2Y4 (CLOCK_ROOT) b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_regRecov_AFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhQ @  ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Cd`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuV@}A+Al31dq@l3@AY=А==Q @ph=I>I@z4?CD@ff&?M @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)Xh)\? d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=930, routed)Xhl3@X2Y4 (CLOCK_ROOT) b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_regRecov_BFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhQ @  ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Cd`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuV@}A+Al31dq@l3@AY=А==Q @ph=I>I@z4?CD@ff&?M @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)Xh)\? d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=930, routed)Xhl3@X2Y4 (CLOCK_ROOT) b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_regRecov_CFF2_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhQ @  ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Cb^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT1:X2Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuԘ@}A+A3B`eq@3@AY=А== @ph=I>b@z4?CD@ff&?- @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV>c ctrl_regs_inst/reset_all_out Jnet (fo=2, routed)Xhjt@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I2 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_D5LUT_SLICEL_I2_O JLUT3Xhzf> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)Xhi ? b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN Jnet (fo=930, routed)Xhq@X2Y4 (CLOCK_ROOT)m ;7i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=930, routed)Xh3@X2Y4 (CLOCK_ROOT) `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhph=@ Jclock uncertaintyXhY ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_regRecov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh @  **async_default** fabric_clk fabric_clk!)Ë>(@1Ë>8@9AË>(@IË>8@eR Ahq}Yp=Yd rise - rise rise - rise  J 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C3/SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuƋ>}(\Ͽ+ֿ|?>ȶ?+?p=-yD=fff>L7>z?@5>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[39].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xhfff>e 3/SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xhȶ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[39].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh+?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]c 1-SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg/C JFDCEXhzr> Jclock pessimismXh-y| /+SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(\Ͽ; J arrival timeXh_?/ JXh4 JslackXhp=s 73SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuMb>}=ǿw߿$=?w?>$ID=&1>L7>I?@5>'1?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[16].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh&1>o =9SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[16].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhw?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]/C JFDCEXhzr> Jclock pessimismXh$I 95SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh=ǿ; J arrival timeXhI?/ JXh4 JslackXh>s 73SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsurh>}$Ŀ׿w=??v#>o"D=K7>L7>L7?@5>A?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[36].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhK7>o =9SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[36].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]/C JFDPEXhzr> Jclock pessimismXho" 95SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]Remov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh$Ŀ; J arrival timeXhv?/ JXh4 JslackXhv#> 73SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C@}l=?l?"%> D=8A>L7>?U?@5>w?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[24].ngCCM_gbt/out[0] Jnet (fo=377, routed)Xh8A>r @1]i 73SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[24].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhl?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]p >:SFP_GEN[24].ngCCM_gbt/ngccmPinsOutReg_reg[bkp_reset_qie]/C JFDCEXhzr> Jclock pessimismXh  <8SFP_GEN[24].ngCCM_gbt/ngccmPinsOutReg_reg[bkp_reset_qie]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXh"%> 62SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuZ>}=¿^ٿh:=ƻ?^?c&>AD=(>L7>x?@5>-?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=d SFP_GEN[7].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh(>n <8SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xhƻ?X2Y4 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[7].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh^?X2Y4 (CLOCK_ROOT)l :6SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/C JFDPEXhzr> Jclock pessimismXhA 84SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]Remov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh=¿; J arrival timeXh? ?/ JXh4 JslackXhc&>s 73SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu(\>}lx+ǿ~=?+?/>g*D= +>L7>}?u?@5>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[46].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh +>o =9SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[46].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh+?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/C JFDPEXhzr> Jclock pessimismXhg* 95SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]Remov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhlx; J arrival timeXhr?/ JXh4 JslackXh/>t 73SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu(\>}lx+ǿ~=?+?/>g*D= +>L7>}?u?@5>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[46].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh +>o =9SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[46].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh+?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]/C JFDPEXhzr> Jclock pessimismXhg* 95SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]Remov_EFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhlx; J arrival timeXhr?/ JXh4 JslackXh/>s 73SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsur>}ſXٿh= ?X?0>Z"D=T>L7>:?@5>ʡ?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[37].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhT>o =9SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[37].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/C JFDPEXhzr> Jclock pessimismXhZ" 95SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]Remov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhſ; J arrival timeXh?/ JXh4 JslackXh0>t 73SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsur>}ſXٿh= ?X?0>Z"D=T>L7>:?@5>ʡ?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[37].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhT>o =9SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[37].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]/C JFDPEXhzr> Jclock pessimismXhZ" 95SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]Remov_EFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhſ; J arrival timeXh?/ JXh4 JslackXh0>V 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C62SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuI>}aÿEֿH=ȶ?E?{3>(CD=lg>L7>z?@5>S?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[39].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xhlg>h 62SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xhȶ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[39].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhE?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]f 40SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]/C JFDCEXhzr> Jclock pessimismXh(C 2.SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhaÿ; J arrival timeXh$?/ JXh4 JslackXh{3>4 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuKsA}AAHjt@H@A~>А={>R Aᥛ=V>oqAף?z4@m?A` @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhoqAD JXhSLR Crossing[0->1]n <8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ 84SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhA; J arrival timeXh|?/ JXh4 JslackXhR A5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuKsA}AAHjt@H@A~>А={>R Aᥛ=V>oqAף?z4@m?A` @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhoqAD JXhSLR Crossing[0->1]n <8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ 84SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhA; J arrival timeXh|?/ JXh4 JslackXhR A8 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuqA}Ag"AJt@J@A~>А={> Aᥛ=V>anAף?z4@m?|@e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) /%J@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhanAD JXhSLR Crossing[0->1]o =9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhJ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/C JFDPEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh/@ Jclock uncertaintyXh~ 95SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]Recov_AFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXhg"A; J arrival timeXh(/ JXh4 JslackXh A8 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]o =9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 95SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A9 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]o =9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 95SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A8 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]o =9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]/C JFDPEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 95SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]Recov_FFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A9 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]o =9SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/C JFDPEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 95SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]Recov_FFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A4 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]n <8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 84SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]n <8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 84SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A4 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]/CLR""RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0*X2Y42"RCLK_DSP_L_X41Y329/CLK_VDISTR_BOT0:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsunA}A7AHt@H@A~>А={>L Aᥛ=V>nlAף?z4@m?O @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %H@-m?5 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[2].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhnlAD JXhSLR Crossing[0->1]n <8SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[2].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhH@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]/C JFDCEXhzr> Jclock pessimismXhᥛ=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 84SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhL A> **async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]!)y@1y @9Ay@Iy @e{@hq}->d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuV>}طiͿ=?i?->29H=~j>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh~j> uqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzr> Jclock pessimismXh2 qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXhh?/ JXh4 JslackXh->RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuV>}طiͿ=?i?->29H=~j>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh~j> uqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzr> Jclock pessimismXh2 qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXhh?/ JXh4 JslackXh->RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuV>}طiͿ=?i?->29H=~j>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh~j> uqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzr> Jclock pessimismXh2 qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXhh?/ JXh4 JslackXh->RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuV>}طiͿ=?i?->29H=~j>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh~j> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]/C JFDCEXhzr> Jclock pessimismXh2 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXhh?/ JXh4 JslackXh->RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuَ>}طiͿ=?i?.>29H=k>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]/C JFDCEXhzr> Jclock pessimismXh2 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXh-?/ JXh4 JslackXh.>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuَ>}طiͿ=?i?.>29H=k>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]/C JFDCEXhzr> Jclock pessimismXh2 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXh-?/ JXh4 JslackXh.>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuَ>}طiͿ=?i?.>29H=k>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]/C JFDCEXhzr> Jclock pessimismXh2 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXh-?/ JXh4 JslackXh.>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuَ>}طiͿ=?i?.>29H=k>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]/C JFDCEXhzr> Jclock pessimismXh2 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXh-?/ JXh4 JslackXh.>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuَ>}طiͿ=?i?.>29H=k>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]/C JFDCEXhzr> Jclock pessimismXh2 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXh-?/ JXh4 JslackXh.>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuَ>}طiͿ=?i?.>29H=k>*?  ?|??th1?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]/C JFDCEXhzr> Jclock pessimismXh2 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhط; J arrival timeXh-?/ JXh4 JslackXh.>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT2=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu @}Aa:A!Jy> g@!J@A=А={@>|>+?#?l?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/I0 JXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf֣p> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)XhK? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhףH@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhK71@X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha:A; J arrival timeXhG/ JXh4 JslackXh{@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZ(LUT2=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu @}Aa:A!Jy> g@!J@A=А={@>|>+?#?l?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/I0 JXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf֣p> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)XhK? YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhףH@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhK71@X3Y0 (CLOCK_ROOT) WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha:A; J arrival timeXhG/ JXh4 JslackXh{@ d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu?}A6b8AG@`j@G@A=А=@Z>I >}??#?h?r?W9?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh6b8A; J arrival timeXh/ JXh4 JslackXh@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu?}A6b8AG@`j@G@A=А=@Z>I >}??#?h?r?W9?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh6b8A; J arrival timeXh/ JXh4 JslackXh@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu?}A6b8AG@`j@G@A=А=@Z>I >}??#?h?r?W9?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh6b8A; J arrival timeXh/ JXh4 JslackXh@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun?}AZ8AGdfj@G@A=А=ګ@Z>I >5^?#?h?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ8A; J arrival timeXh1/ JXh4 JslackXhګ@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun?}AZ8AGdfj@G@A=А=ګ@Z>I >5^?#?h?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ8A; J arrival timeXh1/ JXh4 JslackXhګ@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun?}AZ8AGdfj@G@A=А=ګ@Z>I >5^?#?h?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ8A; J arrival timeXh1/ JXh4 JslackXhګ@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun?}AZ8AGdfj@G@A=А=ګ@Z>I >5^?#?h?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]Recov_FFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ8A; J arrival timeXh1/ JXh4 JslackXhګ@Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0*X3Y02!RCLK_DSP_L_X51Y89/CLK_VDISTR_BOT0:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun?}AZ8AGdfj@G@A=А=ګ@Z>I >5^?#?h?r??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEK@X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5.@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ8A; J arrival timeXh1/ JXh4 JslackXhګ@RB **async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1!)y@1y @9Ay@Iy @eQj@hq}<@>d rise - rise rise - rise  SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}Wo=$?W?<@>\9H=V>X9>^ ?x ?gf&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh\ d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXh<@>5eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cuqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}1.dI= ?.?A>D=Zd>X9>?x ?'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= kgg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhZd> uqg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhв?/ JXh4 JslackXhA>RZeag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C~zg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}1.dI= ?.?A>D=Zd>X9>?x ?'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= kgg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhZd> ~zg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT) |xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh zvg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhв?/ JXh4 JslackXhA>RSOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu}>}ҭ"=$?ҭ?z0P>=9H=K>X9>^ ?x ?'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:?X4Y2 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr> Jclock pessimismXh= d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhİ?/ JXh4 JslackXhz0P>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu}>}ҭ"=$?ҭ?z0P>=9H=K>X9>^ ?x ?'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK> ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:?X4Y2 (CLOCK_ROOT) gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]/C JFDCEXhzr> Jclock pessimismXh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhİ?/ JXh4 JslackXhz0P>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu}>}ҭ"=$?ҭ?z0P>=9H=K>X9>^ ?x ?'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:?X4Y2 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]/C JFDCEXhzr> Jclock pessimismXh= d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhİ?/ JXh4 JslackXhz0P>73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}3O>=*\?O?u\>3D=%>X9>gf?x ?y&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh%>` .*SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X4Y2 (CLOCK_ROOT)i 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y2 (CLOCK_ROOT)^ ,(SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh3w *&SFP_GEN[10].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXhµ?/ JXh4 JslackXhu\>4SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}ҳ̬g=$?̬?l>9H=>X9>^ ?x ?V%?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhҳ; J arrival timeXhK?/ JXh4 JslackXhl>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}ҳ̬g=$?̬?l>9H=>X9>^ ?x ?V%?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhҳ; J arrival timeXhK?/ JXh4 JslackXhl>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu>}ҳ̬g=$?̬?l>9H=>X9>^ ?x ?V%?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]/C JFDCEXhzr> Jclock pessimismXh eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhҳ; J arrival timeXhK?/ JXh4 JslackXhl>0g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu^)@}A!3Ac0IS@c0@A=А=Qj@>(>?5@-??A`?Χ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhZD?} KGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT){ IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh!3A; J arrival timeXhپ/ JXh4 JslackXhQj@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@(>$@-??A`?Q?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C JFDCEXhzr> Jclock pessimismXhl>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhо/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@(>$@-??A`?Q?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXhl>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhо/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@(>$@-??A`?Q?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXhl>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhо/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@(>-@-??A`?(1?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhMB?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-3A; J arrival timeXh/ JXh4 JslackXh.ħ@ $g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuk$@}A_ 3A/JTS@/@A=А=@>(>L7@-??A`?= ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhMb0?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?5@X4Y2 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh_ 3A; J arrival timeXhZ/ JXh4 JslackXh@ %g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuk$@}A_ 3A/JTS@/@A=А=@>(>L7@-??A`?= ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhMb0?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?5@X4Y2 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh_ 3A; J arrival timeXhZ/ JXh4 JslackXh@ $g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuk$@}A_ 3A/JTS@/@A=А=@>(>L7@-??A`?= ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhMb0?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?5@X4Y2 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh_ 3A; J arrival timeXhZ/ JXh4 JslackXh@ $g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuk$@}A_ 3A/JTS@/@A=А=@>(>L7@-??A`?= ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhMb0?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?5@X4Y2 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh_ 3A; J arrival timeXhZ/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@(>p @-??A`?c?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf)> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhG!?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhh5@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)XhR@X4Y2 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C JFDCEXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)3A; J arrival timeXhv/ JXh4 JslackXhܫ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!)y@1y @9Ay@Iy @e@hq}>d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuX9>}[|F{<s?F?>{/9H=+>G>?µ>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh+> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh{/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh[|; J arrival timeXh&?/ JXh4 JslackXh>d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuv>}1$=y?$?+>~9H=D>G> ?µ>+'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhD> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh[d[?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh~ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXh䥛?/ JXh4 JslackXh+>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuv>}1$=y?$?+>~9H=D>G> ?µ>+'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhD> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh[d[?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh~ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXh䥛?/ JXh4 JslackXh+>RRNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuq=>}W =s??g4>9H=Mb>G>?µ>y&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xha?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW ; J arrival timeXhD?/ JXh4 JslackXhg4>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuq=>}W =s??g4>9H=Mb>G>?µ>y&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xha?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW ; J arrival timeXhD?/ JXh4 JslackXhg4>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsǔ>}Llffȼ=s?ff?x6>9H=lg>G>?µ>'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhlg> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhLl; J arrival timeXh/?/ JXh4 JslackXhx6>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsǔ>}Llffȼ=s?ff?x6>9H=lg>G>?µ>'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhlg> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhLl; J arrival timeXh/?/ JXh4 JslackXhx6>-62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu>}(ۂ=Fs??|>>#D=@5^>G>0?µ>"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) 62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[8].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>c 1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]/C JFDCEXhzr> Jclock pessimismXh#z -)SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhƛ?/ JXh4 JslackXh|>>4.62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu>}(ۂ=Fs??|>>#D=@5^>G>0?µ>"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) 62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[8].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>c 1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXh#{ -)SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhƛ?/ JXh4 JslackXh|>>4-62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu>}(ۂ=Fs??|>>#D=@5^>G>0?µ>"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) 62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[8].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>c 1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]/C JFDCEXhzr> Jclock pessimismXh#z -)SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhƛ?/ JXh4 JslackXh|>>4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu[2@}Aʞ+AI]n:@I@A=А=@a>ȶ>F@9??'?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhˡ?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhʞ+A; J arrival timeXh~/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu[2@}Aʞ+AI]n:@I@A=А=@a>ȶ>F@9??'?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhˡ?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhʞ+A; J arrival timeXh~/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu[2@}Aʞ+AI]n:@I@A=А=@a>ȶ>F@9??'?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhˡ?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhʞ+A; J arrival timeXh~/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu+/@}A;+ANn:@@A=А=@~a>ȶ>Q@9??'?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C JFDCEXhzr> Jclock pessimismXh~a>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;+A; J arrival timeXh̴/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu-@}AI+A/7ͻn:@/@A=А=뿣@|a>ȶ>E@9??'??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/C JFDCEXhzr> Jclock pessimismXh|a>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhI+A; J arrival timeXhƳ/ JXh4 JslackXh뿣@ 2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu.@}A`],AKHn:@K@A=А=i@za>ȶ>+@9??'?Χ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C JFDCEXhzr> Jclock pessimismXhza>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh`],A; J arrival timeXhX9/ JXh4 JslackXhi@ 3g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu.@}A`],AKHn:@K@A=А=i@za>ȶ>+@9??'?Χ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C JFDCEXhzr> Jclock pessimismXhza>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh`],A; J arrival timeXhX9/ JXh4 JslackXhi@ 2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu.@}A`],AKHn:@K@A=А=i@za>ȶ>+@9??'?Χ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzr> Jclock pessimismXhza>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh`],A; J arrival timeXhX9/ JXh4 JslackXhi@ 2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu.@}A`],AKHn:@K@A=А=i@za>ȶ>+@9??'?Χ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C JFDCEXhzr> Jclock pessimismXhza>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh`],A; J arrival timeXhX9/ JXh4 JslackXhi@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1*X4Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu@}A+An:@@A=А=趫@aa>ȶ>@9??'?W9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzfe;_> @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhb?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C JFDCEXhzr> Jclock pessimismXhaa>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh / JXh4 JslackXh趫@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!)y@1y @9Ay@Iy @e5@hq}b->d rise - rise rise - rise  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuhff>}sĐ4=n?Đ?b->99H=X94>Ġ>A?µ>j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh9 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhs; J arrival timeXhX9?/ JXh4 JslackXhb->Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuhff>}sĐ4=n?Đ?b->99H=X94>Ġ>A?µ>j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh9 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhs; J arrival timeXhX9?/ JXh4 JslackXhb->R62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C-)SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuV>}u|=2l?|?z.>Ţ)D=/$>Ġ>I>µ>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/$>_ -)SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhkt?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhŢ)v )%SFP_GEN[9].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhu; J arrival timeXhĐ?/ JXh4 JslackXhz.>4+d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuSc>}{ʑh>.=n?ʑ?2>b'9H=&1>Ġ>A?µ>v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh&1> tpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhXy?X4Y3 (CLOCK_ROOT) rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhb' plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXh ד?/ JXh4 JslackXh2>RPd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuhff>}{J 6=n?J ?3>4Z'9H=X94>Ġ>A?µ>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhX94> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh$y?X4Y3 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh4Z' yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXhX9?/ JXh4 JslackXh3>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuO>}C S=n?S?=>it9H=rh>Ġ>A?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhrh> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhit g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC ; J arrival timeXh?/ JXh4 JslackXh=>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuO>}C S=n?S?=>it9H=rh>Ġ>A?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhrh> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhit g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC ; J arrival timeXh?/ JXh4 JslackXh=>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuO>}C S=n?S?=>it9H=rh>Ġ>A?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhrh> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhit g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC ; J arrival timeXh?/ JXh4 JslackXh=>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuO>}C S=n?S?=>it9H=rh>Ġ>A?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhrh> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhit g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC ; J arrival timeXh?/ JXh4 JslackXh=>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuO>}C S=n?S?=>it9H=rh>Ġ>A?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhrh> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhit g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC ; J arrival timeXh?/ JXh4 JslackXh=>Rg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuD<@}Aj+Azw7@z@A=А=5@)b>>M*@5^:??(?8?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C JFDCEXhzr> Jclock pessimismXh)b>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXh$/ JXh4 JslackXh5@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuD<@}Aj+Azw7@z@A=А=5@)b>>M*@5^:??(?8?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C JFDCEXhzr> Jclock pessimismXh)b>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXh$/ JXh4 JslackXh5@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuD<@}Aj+Azw7@z@A=А=5@)b>>M*@5^:??(?8?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C JFDCEXhzr> Jclock pessimismXh)b>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXh$/ JXh4 JslackXh5@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuz<@}A+Akw7@k@A=А=^@b>>q=*@5^:??(?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh+?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh^@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuz<@}A+Akw7@k@A=А=^@b>>q=*@5^:??(?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh+?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh^@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuz<@}A+Akw7@k@A=А=^@b>>q=*@5^:??(?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh+?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh^@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuz<@}A+Akw7@k@A=А=^@b>>q=*@5^:??(?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh+?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh^@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsum;@}AN+AZ w7@Z@A=А=w@].b>>)@5^:??(?G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C JFDCEXhzr> Jclock pessimismXh].b>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXhҹ/ JXh4 JslackXhw@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsum;@}AN+AZ w7@Z@A=А=w@].b>>)@5^:??(?G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C JFDCEXhzr> Jclock pessimismXh].b>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXhҹ/ JXh4 JslackXhw@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR""RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X67Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsum;@}AN+AZ w7@Z@A=А=w@].b>>)@5^:??(?G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh^? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhX@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C JFDCEXhzr> Jclock pessimismXh].b>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXhҹ/ JXh4 JslackXhw@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!)y@1y @9Ay@Iy @e&@hq}ܰ >d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu~j>}r8ѿ^=ٮ?8?ܰ >=9H=Q8>>C?C ?jm?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ8> fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh= b^g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_regRemov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhr; J arrival timeXh(?/ JXh4 JslackXhܰ >RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu~j>}r8ѿ^=ٮ?8?ܰ >=9H=Q8>>C?C ?jm?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ8> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzr> Jclock pessimismXh= c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhr; J arrival timeXh(?/ JXh4 JslackXhܰ >RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsugm>}ѿ|=ٮ??a> =9H=Zd;>>C?C ?|n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzr> Jclock pessimismXh = qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXha>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsugm>}ѿ|=ٮ??a> =9H=Zd;>>C?C ?|n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzr> Jclock pessimismXh = qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXha>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsugm>}ѿ|=ٮ??a> =9H=Zd;>>C?C ?|n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzr> Jclock pessimismXh = qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXha>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsugm>}ѿ|=ٮ??a> =9H=Zd;>>C?C ?|n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]/C JFDCEXhzr> Jclock pessimismXh = c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXha>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuxi>}0Gѿ;=ٮ?G?L>=9H=K7>>C?C ?Wm?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK7> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzr> Jclock pessimismXh= c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0; J arrival timeXh2?/ JXh4 JslackXhL>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuxi>}0Gѿ;=ٮ?G?L>=9H=K7>>C?C ?Wm?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK7> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXh= c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0; J arrival timeXh2?/ JXh4 JslackXhL>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsubX>}Ͽ=ٮ??>|>9H=T%>>C?C ?;h?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhT%> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh|> c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh#?/ JXh4 JslackXh>73SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuA`>}{ο@=W?{?*> XD=/>>@?C ?f?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) 73SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[12].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/>` .*SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT)i 73SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y6 (CLOCK_ROOT)^ ,(SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh Xw *&SFP_GEN[12].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh*>4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu k@}AT9AQPi;_xi@QP@A=А=&@433>>SS@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT9A; J arrival timeXh/ JXh4 JslackXh&@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu k@}AT9AQPi;_xi@QP@A=А=&@433>>SS@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT9A; J arrival timeXh/ JXh4 JslackXh&@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu k@}AT9AQPi;_xi@QP@A=А=&@433>>SS@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT9A; J arrival timeXh/ JXh4 JslackXh&@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu33k@}A%9A'1PGaxi@'1P@A=А=Fh@433>>!R@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)XhR6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%9A; J arrival timeXhV/ JXh4 JslackXhFh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu33k@}A%9A'1PGaxi@'1P@A=А=Fh@433>>!R@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)XhR6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%9A; J arrival timeXhV/ JXh4 JslackXhFh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuH b@}AT9AQPi;_xi@QP@A=А= @433>>7I@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT9A; J arrival timeXh/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuH b@}AT9AQPi;_xi@QP@A=А= @433>>7I@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)Xh6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT9A; J arrival timeXh/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuqha@}A%9A'1PGaxi@'1P@A=А=M@433>>`H@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)XhR6@X4Y6 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%9A; J arrival timeXhp/ JXh4 JslackXhM@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuqha@}A%9A'1PGaxi@'1P@A=А=M@433>>`H@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)XhR6@X4Y6 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%9A; J arrival timeXhp/ JXh4 JslackXhM@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR"$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT*X4Y62$RCLK_CLEL_R_L_X66Y449/CLK_VDISTR_BOT:X4Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuqha@}A%9A'1PGaxi@'1P@A=А=M@433>>`H@M?@…??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhoK@X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[1].gbtbank/CLK Jnet (fo=674, routed)XhR6@X4Y6 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C JFDCEXhzr> Jclock pessimismXh433>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%9A; J arrival timeXhp/ JXh4 JslackXhM@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!)y@1y @9Ay@Iy @e{@hq}>d rise - rise rise - rise  SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuv>>}:J~k!!=r?k?>(19H=I >Т>S?η>S#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhI > hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhkT?X4Y9 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y9 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh(1 d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:J~; J arrival timeXhG?/ JXh4 JslackXh>eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu<>}G恿둿K}=!r??L>HD=A`>Т>o?η>-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhA`> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXhH g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhG恿; J arrival timeXh ?/ JXh4 JslackXhL>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu>}ashl=!r?sh?ac>&SD=!r>Т>o?η> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh!r> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhvx?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh&S g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXha; J arrival timeXhҝ?/ JXh4 JslackXhac>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuN7>}"z8mj<!r?8?"r>[&D=Ga>Т>o?η>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh[& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh"z; J arrival timeXh䥛?/ JXh4 JslackXh"r>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuq=>}{<!r?? s> T&D=Sc>Т>o?η>/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh T& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXhm?/ JXh4 JslackXh s>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuq=>}{<!r?? s> T&D=Sc>Т>o?η>/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh T& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXhm?/ JXh4 JslackXh s>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu/>}J Ǽ=!r?J ?Du>kCD=>Т>o?η>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= kgg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh> ~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh$y?X4Y9 (CLOCK_ROOT) |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhkC zvg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhĠ?/ JXh4 JslackXhDu>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuD`>}IM߄=!r?M?>.>D=̌>Т>o?η>v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xȟ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh.> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhI; J arrival timeXh!?/ JXh4 JslackXh>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuD`>}IM߄=!r?M?>.>D=̌>Т>o?η>v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xȟ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh.> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhI; J arrival timeXh!?/ JXh4 JslackXh>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuD`>}IM߄=!r?M?>.>D=̌>Т>o?η>v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xȟ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhzT?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh.> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhI; J arrival timeXh!?/ JXh4 JslackXh>Rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu/@}A z0A'D\սz<@'@A=А={@$c>%>p=r@9??r(?c?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI,@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21/I0 JXhzr fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21/OProp_H6LUT_SLICEL_I0_O JLUT2XhzfFs> XTg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhl? UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh$@X4Y9 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh$c>@ Jclock uncertaintyXh QMg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh z0A; J arrival timeXhl/ JXh4 JslackXh{@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu/@}A z0A'D\սz<@'@A=А={@$c>%>p=r@9??r(?c?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI,@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21/I0 JXhzr fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21/OProp_H6LUT_SLICEL_I0_O JLUT2XhzfFs> XTg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhl? ZVg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh$@X4Y9 (CLOCK_ROOT) XTg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh$c>@ Jclock uncertaintyXh VRg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh z0A; J arrival timeXhl/ JXh4 JslackXh{@ Qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j> c@9??r(?<ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhlG?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C JFDCEXhzr> Jclock pessimismXhS[>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV+A; J arrival timeXh|/ JXh4 JslackXha~@ Pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j> c@9??r(?<ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhlG?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr> Jclock pessimismXhS[>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV+A; J arrival timeXh|/ JXh4 JslackXha~@ Pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j> c@9??r(?<ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhlG?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXhS[>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV+A; J arrival timeXh|/ JXh4 JslackXha~@ Pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j> c@9??r(?<ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhlG?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr> Jclock pessimismXhS[>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV+A; J arrival timeXh|/ JXh4 JslackXha~@ Pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j>43c@9??r(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh0D?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh ?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXh+/ JXh4 JslackXh~@ Pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j>43c@9??r(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh0D?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh ?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXh+/ JXh4 JslackXh~@ pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuSk@}A?2+AP޾z<@@A=А=}@[>~j> \@9??r(?R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh*?z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?2+A; J arrival timeXhl/ JXh4 JslackXh}@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1*X4Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuSk@}A?2+AP޾z<@@A=А=}@[>~j> \@9??r(?R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh*?z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh{@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?2+A; J arrival timeXhl/ JXh4 JslackXh}@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!)y@1y @9Ay@Iy @eS @hq}C4>d rise - rise rise - rise  73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}絿OͿ\=I?O?C4>`@D=Q>@5>? ?d?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh` .*SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y8 (CLOCK_ROOT)^ ,(SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh`@w *&SFP_GEN[23].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh絿; J arrival timeXhj?/ JXh4 JslackXhC4>4eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}aYȿo=L7??[F>@9H=T>Q>c8? ?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhT> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhaY; J arrival timeXh?/ JXh4 JslackXh[F>RSOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}*\D̿4> ?D?~j>/ݽ9H=h>Q>;? ?pc?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhh> ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhm?X4Y8 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl?X4Y8 (CLOCK_ROOT) gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]/C JFDCEXhzr> Jclock pessimismXh/ݽ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh*\; J arrival timeXh ?/ JXh4 JslackXh~j>SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}*\D̿4> ?D?~j>/ݽ9H=h>Q>;? ?pc?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhh> ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhm?X4Y8 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl?X4Y8 (CLOCK_ROOT) gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]/C JFDCEXhzr> Jclock pessimismXh/ݽ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh*\; J arrival timeXh ?/ JXh4 JslackXh~j>SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu$>}I̿> ?I?k>/ݽ9H=W>Q>;? ?^b?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhW> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhm?X4Y8 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]/C JFDCEXhzr> Jclock pessimismXh/ݽ d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXhk>SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu$>}I̿> ?I?k>/ݽ9H=W>Q>;? ?^b?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhW> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhm?X4Y8 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]/C JFDCEXhzr> Jclock pessimismXh/ݽ d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXhk>SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu$>}I̿> ?I?k>/ݽ9H=W>Q>;? ?^b?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhW> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhm?X4Y8 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]/C JFDCEXhzr> Jclock pessimismXh/ݽ d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXhk>SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu$>}I̿> ?I?k>/ݽ9H=W>Q>;? ?^b?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhW> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhm?X4Y8 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]/C JFDCEXhzr> Jclock pessimismXh/ݽ d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhC?/ JXh4 JslackXhk>73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}ݿpͿ`I:=I?p?Jv>ZD=x>Q>@5>? ?0d?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhx>d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXhZ{ .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhݿ; J arrival timeXh8?/ JXh4 JslackXhJv>473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}ݿpͿ`I:=I?p?Jv>ZD=x>Q>@5>? ?0d?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhx>d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr> Jclock pessimismXhZ| .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhݿ; J arrival timeXh8?/ JXh4 JslackXhJv>4Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu|@}Av6At;VξPg@t;@A=А=S @n>5^> ק@?*\?E?,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh?} KGg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh!@X4Y8 (CLOCK_ROOT){ IEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C JFDCEXhzr> Jclock pessimismXhn>@ Jclock uncertaintyXh GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhv6A; J arrival timeXhʡ/ JXh4 JslackXhS @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>@?*\?E?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh33?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh!@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C JFDCEXhzr> Jclock pessimismXho>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhr6A; J arrival timeXh/ JXh4 JslackXh @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>@?*\?E?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh33?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh!@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C JFDCEXhzr> Jclock pessimismXho>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhr6A; J arrival timeXh/ JXh4 JslackXh @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>@?*\?E?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh33?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh!@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C JFDCEXhzr> Jclock pessimismXho>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhr6A; J arrival timeXh/ JXh4 JslackXh @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>@?*\?E??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xho?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh"@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C JFDCEXhzr> Jclock pessimismXhk>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh~6A; J arrival timeXh/ JXh4 JslackXh# @ -g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>@?*\?E??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xho?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh"@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C JFDCEXhzr> Jclock pessimismXhk>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh~6A; J arrival timeXh/ JXh4 JslackXh# @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>@?*\?E??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xho?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh"@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C JFDCEXhzr> Jclock pessimismXhk>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh~6A; J arrival timeXh/ JXh4 JslackXh# @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>)\@?*\?E?ҽ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh-?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)XhI "@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C JFDCEXhzr> Jclock pessimismXhLm>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhz6A; J arrival timeXhYd/ JXh4 JslackXhY @ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>)\@?*\?E?ҽ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh-?r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)XhI "@X4Y8 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C JFDCEXhzr> Jclock pessimismXhLm>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhz6A; J arrival timeXhYd/ JXh4 JslackXhY @ Mg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuM@}A܂6A;̾Pg@;@A=А=}@j>5^>梨@?*\?E?z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhʡm@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh)\?z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh&I@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh-"@X4Y8 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh܂6A; J arrival timeXh= / JXh4 JslackXh}@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!)y@1y @9Ay@Iy @e@hq}>d rise - rise rise - rise  73SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuIz>}\~>U=1?~?>D=^I> >Z?A`?C`%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) 73SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[13].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^I>` .*SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$y?X4Y6 (CLOCK_ROOT)i 73SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[13].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X4Y6 (CLOCK_ROOT)^ ,(SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhw *&SFP_GEN[13].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh\; J arrival timeXhZd?/ JXh4 JslackXh>4d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuĠ>}󭿭*=-??Y>9H=> >?A`?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhU?/ JXh4 JslackXhY>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu>} =-??(Y>9H=> >?A`?r=*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/}?X4Y6 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhΗ?X4Y6 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh0ݴ?/ JXh4 JslackXh(Y>R RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A$2A,$F@,@A=А=@|>)\>%@~?E?p}??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh%@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXh|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh$2A; J arrival timeXhMb/ JXh4 JslackXh@!RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A$2A,$F@,@A=А=@|>)\>%@~?E?p}??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh%@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]/C JFDCEXhzr> Jclock pessimismXh|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh$2A; J arrival timeXhMb/ JXh4 JslackXh@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@!RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@!RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@!RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@!RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]/CLR"#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT*X4Y62#RCLK_CLE_M_L_X79Y449/CLK_VDISTR_BOT:X4Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}A 2A,%F@,@A=А=@O|>)\>@~?E?p}?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhMb(@X4Y6 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"@X4Y6 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]/C JFDCEXhzr> Jclock pessimismXhO|>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhZ/ JXh4 JslackXh@D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!)y@1y @9Ay@Iy @e]@hq}$>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCl>}%(=َ?(?$>69H=5^:> ף>h-?X>uhQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzr> Jclock pessimismXh6 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXhj?/ JXh4 JslackXh$>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCl>}%(=َ?(?$>69H=5^:> ף>h-?X>uhQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzr> Jclock pessimismXh6 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXhj?/ JXh4 JslackXh$>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCl>}%(=َ?(?$>69H=5^:> ף>h-?X>uhQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]/C JFDCEXhzr> Jclock pessimismXh6 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXhj?/ JXh4 JslackXh$>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCl>}%(=َ?(?$>69H=5^:> ף>h-?X>uhQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]/C JFDCEXhzr> Jclock pessimismXh6 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXhj?/ JXh4 JslackXh$>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCl>}%(=َ?(?$>69H=5^:> ף>h-?X>uhQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]/C JFDCEXhzr> Jclock pessimismXh6 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXhj?/ JXh4 JslackXh$>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuo>}gjڭ=َ?j?(>^49H=p=> ף>h-?X>Q?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhp=> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr> Jclock pessimismXh^4 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh̬?/ JXh4 JslackXh(>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuo>}gjڭ=َ?j?(>^49H=p=> ף>h-?X>Q?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhp=> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr> Jclock pessimismXh^4 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh̬?/ JXh4 JslackXh(>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuo>}gjڭ=َ?j?(>^49H=p=> ף>h-?X>Q?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhp=> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr> Jclock pessimismXh^4 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh̬?/ JXh4 JslackXh(>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuo>}gjڭ=َ?j?(>^49H=p=> ף>h-?X>Q?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhp=> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzr> Jclock pessimismXh^4 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh̬?/ JXh4 JslackXh(>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuo>}gjڭ=َ?j?(>^49H=p=> ף>h-?X>Q?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhp=> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]/C JFDCEXhzr> Jclock pessimismXh^4 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh̬?/ JXh4 JslackXh(>.g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsug@}AU2A.=@.@A=А=]@dg>>N@Yd;??q=*??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhU2A; J arrival timeXhM/ JXh4 JslackXh]@ .g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsug@}AU2A.=@.@A=А=]@dg>>N@Yd;??q=*??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhU2A; J arrival timeXhM/ JXh4 JslackXh]@ .g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsug@}AU2A.=@.@A=А=]@dg>>N@Yd;??q=*??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhU2A; J arrival timeXhM/ JXh4 JslackXh]@ Ng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuvf@}AM2A.Ż=@.@A=А=R@dg>>M@Yd;??q=*?}??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhM2A; J arrival timeXh/ JXh4 JslackXhR@ .g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuSc@}Ayr2Ae;/B;=@e;/@A=А=tz@dg>>J@Yd;??q=*?ff?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhyr2A; J arrival timeXhj/ JXh4 JslackXhtz@ .g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCc@}Aۂ2A|/c;=@|/@A=А=i@dg>>J@Yd;??q=*?w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhۂ2A; J arrival timeXhMb/ JXh4 JslackXhi@ /g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCc@}Aۂ2A|/c;=@|/@A=А=i@dg>>J@Yd;??q=*?w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhۂ2A; J arrival timeXhMb/ JXh4 JslackXhi@ .g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCc@}Aۂ2A|/c;=@|/@A=А=i@dg>>J@Yd;??q=*?w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhۂ2A; J arrival timeXhMb/ JXh4 JslackXhi@ Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsub@}A~2Al/;=@l/@A=А=Ԕ@dg>>MJ@Yd;??q=*??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh~2A; J arrival timeXh(/ JXh4 JslackXhԔ@ /g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1*X4Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsub@}A~2Al/;=@l/@A=А=Ԕ@dg>>MJ@Yd;??q=*??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ?;g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C JFDCEXhzr> Jclock pessimismXhdg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh~2A; J arrival timeXh(/ JXh4 JslackXhԔ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!)y@1y @9Ay@Iy @ek@hq}5G/>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu+>}3k4=أp?k?5G/>c 9H=(\>M>G?Q>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh(\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]/C JFDCEXhzr> Jclock pessimismXhc  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh5G/>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuq=>}=أp??jT2>^ 9H=Mb>M>G?Q> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]/C JFDCEXhzr> Jclock pessimismXh^  c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhjT2>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuq=>}=أp??jT2>^ 9H=Mb>M>G?Q> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]/C JFDCEXhzr> Jclock pessimismXh^  b^g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhjT2>,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu]b@}AC+A/žF;@/@A=А=k@[]>(>= O@5^:?p?)?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xhl?X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C JFDCEXhzr> Jclock pessimismXh[]>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhC+A; J arrival timeXh"/ JXh4 JslackXhk@ -g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu]b@}AC+A/žF;@/@A=А=k@[]>(>= O@5^:?p?)?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xhl?X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C JFDCEXhzr> Jclock pessimismXh[]>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhC+A; J arrival timeXh"/ JXh4 JslackXhk@ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu]b@}AC+A/žF;@/@A=А=k@[]>(>= O@5^:?p?)?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xhl?X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C JFDCEXhzr> Jclock pessimismXh[]>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhC+A; J arrival timeXh"/ JXh4 JslackXhk@ ,g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsua@}A&+AVƾF;@V@A=А=f@`]>(>ffN@5^:?p?)?-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh+?X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzr> Jclock pessimismXh`]>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh&+A; J arrival timeXh/ JXh4 JslackXhf@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuJ b@}Am+AB`5ľF;@B`@A=А=ň@S]>(>+N@5^:?p?)?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXhS]>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhm+A; J arrival timeXhH/ JXh4 JslackXhň@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuJ b@}Am+AB`5ľF;@B`@A=А=ň@S]>(>+N@5^:?p?)?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXhS]>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhm+A; J arrival timeXhH/ JXh4 JslackXhň@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuJ b@}Am+AB`5ľF;@B`@A=А=ň@S]>(>+N@5^:?p?)?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXhS]>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhm+A; J arrival timeXhH/ JXh4 JslackXhň@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu(\@}A{+ApvþF;@p@A=А=W@6Q]>(>֣H@5^:?p?)??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C JFDCEXhzr> Jclock pessimismXh6Q]>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh{+A; J arrival timeXh/ JXh4 JslackXhW@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu(\@}A{+ApvþF;@p@A=А=W@6Q]>(>֣H@5^:?p?)??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXh6Q]>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh{+A; J arrival timeXh/ JXh4 JslackXhW@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR""RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X67Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu(\@}A{+ApvþF;@p@A=А=W@6Q]>(>֣H@5^:?p?)??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh` @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C JFDCEXhzr> Jclock pessimismXh6Q]>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh{+A; J arrival timeXh/ JXh4 JslackXhW@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!)y@1y @9Ay@Iy @e@hq}_>d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuJs>}juo=?u?_>D=\B>G>Z$?µ>2L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh\B> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhd?/ JXh4 JslackXh_>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuJs>}juo=?u?_>D=\B>G>Z$?µ>2L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh\B> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhd?/ JXh4 JslackXh_>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuJs>}juo=?u?_>D=\B>G>Z$?µ>2L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh\B> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhd?/ JXh4 JslackXh_>RRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu}>}@RgfMR=?gf?D>59H=K>G>S#?µ>G?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhs?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh5 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh@R; J arrival timeXhԨ?/ JXh4 JslackXhD>d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuƋ>}gՓȦT=?Ȧ?E>(D=fff>G>Z$?µ>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhgՓ; J arrival timeXhE?/ JXh4 JslackXhE>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuƋ>}gՓȦT=?Ȧ?E>(D=fff>G>Z$?µ>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhgՓ; J arrival timeXhE?/ JXh4 JslackXhE>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuƋ>}gՓȦT=?Ȧ?E>(D=fff>G>Z$?µ>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhgՓ; J arrival timeXhE?/ JXh4 JslackXhE>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuƋ>}gՓȦT=?Ȧ?E>(D=fff>G>Z$?µ>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhgՓ; J arrival timeXhE?/ JXh4 JslackXhE>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuƋ>}gՓȦT=?Ȧ?E>(D=fff>G>Z$?µ>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhgՓ; J arrival timeXhE?/ JXh4 JslackXhE>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuƋ>}gՓȦT=?Ȧ?E>(D=fff>G>Z$?µ>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhgՓ; J arrival timeXhE?/ JXh4 JslackXhE>Rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuV~@}A 0A(Ą_9@(@A=А=@g>X>+g@9?$?&1(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh)\@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 0A; J arrival timeXh2/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuV~@}A 0A(Ą_9@(@A=А=@g>X>+g@9?$?&1(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh)\@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 0A; J arrival timeXh2/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuV~@}A 0A(Ą_9@(@A=А=@g>X>+g@9?$?&1(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh)\@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 0A; J arrival timeXh2/ JXh4 JslackXh@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu,}@}A0A:(ߵ!_9@:(@A=А=@g>X>+f@9?$?&1(?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhd;@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhF/ JXh4 JslackXh@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu,}@}A0A:(ߵ!_9@:(@A=А=@g>X>+f@9?$?&1(?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhd;@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhF/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuw@}Ap0A+'_9@+'@A=А= -@g>X>`@9?$?&1(?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh- @X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhp0A; J arrival timeXh9/ JXh4 JslackXh -@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuw@}Ap0A+'_9@+'@A=А= -@g>X>`@9?$?&1(?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh- @X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhp0A; J arrival timeXh9/ JXh4 JslackXh -@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuw@}Ap0A+'_9@+'@A=А= -@g>X>`@9?$?&1(?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh- @X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhp0A; J arrival timeXh9/ JXh4 JslackXh -@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsux@}Aj0A%): _9@%)@A=А=&@g>X>a@9?$?&1(? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhP@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhj0A; J arrival timeXhG/ JXh4 JslackXh&@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsux@}Aj0A%): _9@%)@A=А=&@g>X>a@9?$?&1(? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\'@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhP@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhg>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhj0A; J arrival timeXhG/ JXh4 JslackXh&@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!)y@1y @9Ay@Iy @e*@hq}V&>d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsunm>}Fd"8=|?"?V&>D=j<>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhj<> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh/?/ JXh4 JslackXhV&>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsunm>}Fd"8=|?"?V&>D=j<>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhj<> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh/?/ JXh4 JslackXhV&>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu`>}Fd"8=|?"?9L>D=Mb>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh?/ JXh4 JslackXh9L>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu`>}Fd"8=|?"?9L>D=Mb>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh?/ JXh4 JslackXh9L>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu`>}Fd"8=|?"?9L>D=Mb>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh?/ JXh4 JslackXh9L>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu`>}Fd"8=|?"?9L>D=Mb>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh?/ JXh4 JslackXh9L>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu`>}Fd"8=|?"?9L>D=Mb>G> 0?µ>&Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhFd; J arrival timeXh?/ JXh4 JslackXh9L>R'73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu>}iPRD=A?i?# T>ij9D=Y>G>1?µ>V?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhY>` .*SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y8 (CLOCK_ROOT)^ ,(SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhij9w *&SFP_GEN[17].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh8?/ JXh4 JslackXh# T>4d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuS>} <󭿭=|??w_> D=$>G> 0?µ>V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh$> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh <; J arrival timeXh+?/ JXh4 JslackXhw_>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuS>} <󭿭=|??w_> D=$>G> 0?µ>V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh$> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh <; J arrival timeXh+?/ JXh4 JslackXhw_>RSg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuts@}A1A}?-n<\:@}?-@A=А=*@h>n>&a@9??'?D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh / JXh4 JslackXh*@ Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuts@}A1A}?-n<\:@}?-@A=А=*@h>n>&a@9??'?D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh / JXh4 JslackXh*@ Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuts@}A1A}?-n<\:@}?-@A=А=*@h>n>&a@9??'?D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh / JXh4 JslackXh*@ Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuts@}A1A}?-n<\:@}?-@A=А=*@h>n>&a@9??'?D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh / JXh4 JslackXh*@ Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu{n@}A͖1AF+U\:@F+@A=А=ێ@h>n>[@9??'?֣?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhq=@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh͖1A; J arrival timeXhQ/ JXh4 JslackXhێ@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsui@}Ap1A,R-J<\:@,@A=А=>s@h>n>W@9??'??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhp1A; J arrival timeXhE/ JXh4 JslackXh>s@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsui@}Ap1A,R-J<\:@,@A=А=>s@h>n>W@9??'??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhp1A; J arrival timeXhE/ JXh4 JslackXh>s@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsui@}Ap1A,R-J<\:@,@A=А=>s@h>n>W@9??'??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhS@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhp1A; J arrival timeXhE/ JXh4 JslackXh>s@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu7i@}A?1A,h)<\:@,@A=А=3@h>n>e;W@9??'?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh33@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh?1A; J arrival timeXhJ / JXh4 JslackXh3@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1*X4Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu`h@}AĿ1AZ,;\:@Z,@A=А=*ő@h>n>V@9??'??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh04@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhH@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhĿ1A; J arrival timeXh^/ JXh4 JslackXh*ő@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2!)y@1y @9Ay@Iy @eО@hq}$>d rise - rise rise - rise  73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu"y>}1{hȟ=gff?h?$>4 D=9H>>Z?">S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_p?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXh4 { .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1{; J arrival timeXhn?/ JXh4 JslackXh$>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu"y>}1{hȟ=gff?h?$>4 D=9H>>Z?">S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_p?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh4 | .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1{; J arrival timeXhn?/ JXh4 JslackXh$>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu>}Ds=gff??/>@D=Zd>>Z?">l'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXh@{ .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhT?/ JXh4 JslackXh/>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu>}Ds=gff??/>@D=Zd>>Z?">l'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh@| .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhT?/ JXh4 JslackXh/>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu>}Ds=gff??/>@D=Zd>>Z?">l'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh@{ .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhT?/ JXh4 JslackXh/>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu>}Ds=gff??/>@D=Zd>>Z?">l'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzr> Jclock pessimismXh@| .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhT?/ JXh4 JslackXh/>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu>}Ds=gff??/>@D=Zd>>Z?">l'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXh@{ .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhT?/ JXh4 JslackXh/>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu>}Ds=gff??/>@D=Zd>>Z?">l'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr> Jclock pessimismXh@| .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhT?/ JXh4 JslackXh/>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuZd>}&psi!<=gff?i? 30>h#D=433>>Z?">S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh433>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhap?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXhh#| .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh&ps; J arrival timeXhw?/ JXh4 JslackXh 30>473SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuZd>}&psi!<=gff?i? 30>h#D=433>>Z?">S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh433>d 2.SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhap?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXhh#| .*SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh&ps; J arrival timeXhw?/ JXh4 JslackXh 30>4&g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu+=@}AE*AP>"-@P@A=А=О@|W>5^>ff&@v??ף? ף?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhA?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh(?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C JFDCEXhzr> Jclock pessimismXh|W>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhE*A; J arrival timeXh]/ JXh4 JslackXhО@ 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu+=@}AE*AP>"-@P@A=А=О@|W>5^>ff&@v??ף? ף?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhA?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh(?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C JFDCEXhzr> Jclock pessimismXh|W>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhE*A; J arrival timeXh]/ JXh4 JslackXhО@ &g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu+=@}AE*AP>"-@P@A=А=О@|W>5^>ff&@v??ף? ף?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhA?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh(?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C JFDCEXhzr> Jclock pessimismXh|W>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhE*A; J arrival timeXh]/ JXh4 JslackXhО@ &g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu+=@}AE*AP>"-@P@A=А=О@|W>5^>ff&@v??ף? ף?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhA?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh(?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/C JFDCEXhzr> Jclock pessimismXh|W>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhE*A; J arrival timeXh]/ JXh4 JslackXhО@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu8@}As*A}-@@A=А=@*V>n>?5&@v??ף?¥?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/I0 JXhzr fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh-? UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhz?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh*V>@ Jclock uncertaintyXh QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhs*A; J arrival timeXh"/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu8@}As*A}-@@A=А=@*V>n>?5&@v??ף?¥?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/I0 JXhzr fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh-? ZVg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhz?X4Y3 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh*V>@ Jclock uncertaintyXh VRg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhs*A; J arrival timeXh"/ JXh4 JslackXh@ 2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu2@}AJ-*A+,-@+@A=А= @3W>5^>t@v??ף?o?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhjT?} KGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)XhZd?X4Y3 (CLOCK_ROOT){ IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C JFDCEXhzr> Jclock pessimismXh3W>@ Jclock uncertaintyXh GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhJ-*A; J arrival timeXhA/ JXh4 JslackXh @ &g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu2@}AJ-*A+,-@+@A=А= @3W>5^>t@v??ף?o?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhjT?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)XhZd?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C JFDCEXhzr> Jclock pessimismXh3W>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhJ-*A; J arrival timeXhA/ JXh4 JslackXh @ 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR"#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X79Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu2@}AJ-*A+,-@+@A=А= @3W>5^>t@v??ף?o?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhjT?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)XhZd?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/C JFDCEXhzr> Jclock pessimismXh3W>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhJ-*A; J arrival timeXhA/ JXh4 JslackXh @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>q=@v??ף?k?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh)\@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)XhV?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhb*A; J arrival timeXh㥫/ JXh4 JslackXh!@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!)y@1y @9Ay@Iy @e&o@hq}͈>d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>5^>}(Sk=53s?S?͈>Ġ>?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh1,> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhRd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>5^>}(Sk=53s?S?͈>Ġ>?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh1,> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXhRd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>5^>}(Sk=53s?S?͈>Ġ>?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh1,> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhRd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>5^>}(Sk=53s?S?͈>Ġ>?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh1,> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhRd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>5^>}(Sk=53s?S?͈>Ġ>?µ>8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh1,> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhRRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuV>}6z=_p?z?>>Ġ>M?µ> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh~j> fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh!R?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhS~?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh>d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuo>}dMOy=53s?M?B>4Z9H=S>Ġ>?µ>|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhS> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh4Z g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh6^?/ JXh4 JslackXhB>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuo>}dMOy=53s?M?B>4Z9H=S>Ġ>?µ>|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhS> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh4Z g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh6^?/ JXh4 JslackXhB>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuo>}dMOy=53s?M?B>4Z9H=S>Ġ>?µ>|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhS> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh4Z g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh6^?/ JXh4 JslackXhB>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuo>}dMOy=53s?M?B>4Z9H=S>Ġ>?µ>|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhS> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh4Z g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh6^?/ JXh4 JslackXhB>Rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu+6@}A0A&+KD@&@A=А=&o@_>V>ˡ-@5^:?A5?(?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xhˡ-@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg/C JFDCEXhzr> Jclock pessimismXh_>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_regRecov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhO/ JXh4 JslackXh&o@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu0@}A0A)\'ED@)\'@A=А=ڡ@W>V>'@5^:?A5?(?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh'@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)XhT @X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhM/ JXh4 JslackXhڡ@ 2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Clhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu,@}A1AP'O BD@P'@A=А=孩@S>V>F#@5^:?A5?(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhF#@ lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh{@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhZ/ JXh4 JslackXh孩@ 2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Clhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu,@}A1AP'O BD@P'@A=А=孩@S>V>F#@5^:?A5?(??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhF#@ lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh{@X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhZ/ JXh4 JslackXh孩@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu(,@}A0Al'YDD@l'@A=А=ש@V>V>C#@5^:?A5?(?l?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhC#@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]Recov_GFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh / JXh4 JslackXhש@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu(,@}A0Al'YDD@l'@A=А=ש@V>V>C#@5^:?A5?(?l?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhC#@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh / JXh4 JslackXhש@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu(,@}A0Al'YDD@l'@A=А=ש@V>V>C#@5^:?A5?(?l?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhC#@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh / JXh4 JslackXhש@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuV @}A<+A/ZD@/@A=А=K@xl>V>(@5^:?A5?(?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/AS[0] Jnet (fo=32, routed)Xh(@ gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhxl>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh<+A; J arrival timeXhu/ JXh4 JslackXhK@ Rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu< @}A+AjD@j@A=А=L@Cl>V>I?5^:?A5?(?rh?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhI? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C JFDCEXhzr> Jclock pessimismXhCl>@ Jclock uncertaintyXh plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhh/ JXh4 JslackXhL@ Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR""RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X67Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu< @}A+AjD@j@A=А=L@Cl>V>I?5^:?A5?(?rh?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhI? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh.%@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)XhT?X4Y8 (CLOCK_ROOT) rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C JFDCEXhzr> Jclock pessimismXhCl>@ Jclock uncertaintyXh plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhh/ JXh4 JslackXhL@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!)y@1y @9Ay@Iy @e@hq}1t>>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu>}Rž~<=g?̌?1t>>9H=V>>ˡ?">!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhxI?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(\o?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzr> Jclock pessimismXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhRz; J arrival timeXh/ݔ?/ JXh4 JslackXh1t>>d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^>}S{-5=g?-?}C>9H=Ga>>T?">#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS{; J arrival timeXhff?/ JXh4 JslackXh}C>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^>}S{-5=g?-?}C>9H=Ga>>T?">#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS{; J arrival timeXhff?/ JXh4 JslackXh}C>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^>}S{-5=g?-?}C>9H=Ga>>T?">#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS{; J arrival timeXhff?/ JXh4 JslackXh}C>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^>}S{-5=g?-?}C>9H=Ga>>T?">#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS{; J arrival timeXhff?/ JXh4 JslackXh}C>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^>}S{-5=g?-?}C>9H=Ga>>T?">#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS{; J arrival timeXhff?/ JXh4 JslackXh}C>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^>}S{-5=g?-?}C>9H=Ga>>T?">#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS{; J arrival timeXhff?/ JXh4 JslackXh}C>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu>}}RA=g?R?S>@9H=$y>>T?">ʡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh$y> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33s?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXhx?/ JXh4 JslackXhS>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu>}}RA=g?R?S>@9H=$y>>T?">ʡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh$y> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33s?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXhx?/ JXh4 JslackXhS>RRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuOb>}Rž~<=g?̌?W>9H=n>>ˡ?">!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhn> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhxI?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(\o?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhRz; J arrival timeXh?/ JXh4 JslackXhW>g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsum@}Au(*AvJP ?@v@A=А=@v-a>V>- @v?]?ף??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/AS[0] Jnet (fo=32, routed)Xh- @ gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhv-a>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhu(*A; J arrival timeXhX/ JXh4 JslackXh@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsua@}A,*A+k ?@+@A=А=}@*a>V>@v?]?ף?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 Jnet (fo=32, routed)Xh@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]/C JFDCEXhzr> Jclock pessimismXh*a>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,*A; J arrival timeXhA/ JXh4 JslackXh}@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsua@}A,*A+k ?@+@A=А=}@*a>V>@v?]?ף?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 Jnet (fo=32, routed)Xh@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]/C JFDCEXhzr> Jclock pessimismXh*a>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,*A; J arrival timeXhA/ JXh4 JslackXh}@  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ca]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsua@}A,*A+k ?@+@A=А=}@*a>V>@v?]?ף?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 Jnet (fo=32, routed)Xh@ a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/C JFDCEXhzr> Jclock pessimismXh*a>@ Jclock uncertaintyXh ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,*A; J arrival timeXhA/ JXh4 JslackXh}@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu9@}A*A&N?@&@A=А=|@]`>n>?v?]?ף?< ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhA? fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh9? TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(\?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh]`>@ Jclock uncertaintyXh PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh(/ JXh4 JslackXh|@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu9@}A*A&N?@&@A=А=|@]`>n>?v?]?ף?< ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhA? fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh9? YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(\?X4Y8 (CLOCK_ROOT) WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh]`>@ Jclock uncertaintyXh UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh(/ JXh4 JslackXh|@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cd`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/PRE"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuE@}AU*A+ ?@+@A=А=w@a>V>B`@v?]?ף?o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 Jnet (fo=32, routed)XhB`@ d`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/PRE JFDPEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)XhZd?X4Y8 (CLOCK_ROOT) b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_invRecov_DFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXhU*A; J arrival timeXh/ JXh4 JslackXhw@ Ug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu @}AL*A= _ ?@= @A=А=@a>V>@v?]?ף?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 Jnet (fo=32, routed)Xh@ tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)Xh"?X4Y8 (CLOCK_ROOT) rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhL*A; J arrival timeXhR/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C_[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuX @}Ay*Aw>?@w@A=А=;x@ `>V>r@v?]?ף?W9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> \Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 Jnet (fo=32, routed)Xhr@ _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK Jnet (fo=674, routed)XhC?X4Y8 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXh `>@ Jclock uncertaintyXh [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_regRecov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhy*A; J arrival timeXhz/ JXh4 JslackXh;x@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C_[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuX @}Ay*Aw>?@w@A=А=;x@ `>V>r@v?]?ף?W9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/AS[0] Jnet (fo=32, routed)Xhr@ _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhL7!@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> SOg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/CLK Jnet (fo=674, routed)XhC?X4Y8 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh `>@ Jclock uncertaintyXh [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_regRecov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhy*A; J arrival timeXhz/ JXh4 JslackXh;x@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!)y@1y @9Ay@Iy @e{@hq}V>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsux>}p󍿭<g??V>|29H=F>$>?>/$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhF> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh^I?X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh|2 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXho?/ JXh4 JslackXhV>-d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuQ>}1{i,=f?i?;h><9H=ˡ>$>B`?>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhˡ> tpg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhap?X4Y9 (CLOCK_ROOT) rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh< plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1{; J arrival timeXh ?/ JXh4 JslackXh;h>RRd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuQ>}1{i,=f?i?;h><9H=ˡ>$>B`?>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhˡ> }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhap?X4Y9 (CLOCK_ROOT) {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh< yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1{; J arrival timeXh ?/ JXh4 JslackXh;h>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuQ>}1{i,=f?i?;h><9H=ˡ>$>B`?>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhˡ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhap?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh1{; J arrival timeXh ?/ JXh4 JslackXh;h>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuw>}qu@5p%X=f?@5?mU>!9H=ҍ>$>B`?>B`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhҍ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhqu; J arrival timeXhV?/ JXh4 JslackXhmU>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuw>}qu@5p%X=f?@5?mU>!9H=ҍ>$>B`?>B`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhҍ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhqu; J arrival timeXhV?/ JXh4 JslackXhmU>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsux>}}uV=\=f?V?a>!9H=Mb>$>B`?>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}u; J arrival timeXh-?/ JXh4 JslackXha>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsux>}}uV=\=f?V?a>!9H=Mb>$>B`?>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhMb> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}u; J arrival timeXh-?/ JXh4 JslackXha>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}wyj͎=f?j?>9H= ף>$>B`?>!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh ף> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhwy; J arrival timeXh\?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}wyj͎=f?j?>9H= ף>$>B`?>!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh ף> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhrH?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhwy; J arrival timeXh\?/ JXh4 JslackXh>R~73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsul#@}AX)A fF;@ @A=А={@C]>V> @?I?{?(\?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh @d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr> Jclock pessimismXhC]>@ Jclock uncertaintyXh{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhX)A; J arrival timeXhί/ JXh4 JslackXh{@473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsul#@}AX)A fF;@ @A=А={@C]>V> @?I?{?(\?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh @d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr> Jclock pessimismXhC]>@ Jclock uncertaintyXh| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhX)A; J arrival timeXhί/ JXh4 JslackXh{@4~73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsul#@}AX)A fF;@ @A=А={@C]>V> @?I?{?(\?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh @d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXhC]>@ Jclock uncertaintyXh{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhX)A; J arrival timeXhί/ JXh4 JslackXh{@473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsul#@}AX)A fF;@ @A=А={@C]>V> @?I?{?(\?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh @d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXhC]>@ Jclock uncertaintyXh| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhX)A; J arrival timeXhί/ JXh4 JslackXh{@4~73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}AF3*Ay) F;@y@A=А=K@\>V>@?I?{? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhF3*A; J arrival timeXh/ JXh4 JslackXhK@473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}AF3*Ay) F;@y@A=А=K@\>V>@?I?{? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhF3*A; J arrival timeXh/ JXh4 JslackXhK@4~73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}AF3*Ay) F;@y@A=А=K@\>V>@?I?{? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhF3*A; J arrival timeXh/ JXh4 JslackXhK@473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}AF3*Ay) F;@y@A=А=K@\>V>@?I?{? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhF3*A; J arrival timeXh/ JXh4 JslackXhK@4~73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}AF3*Ay) F;@y@A=А=K@\>V>@?I?{? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhF3*A; J arrival timeXh/ JXh4 JslackXhK@473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR"#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP*X4Y92#RCLK_CLE_M_L_X79Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}AF3*Ay) F;@y@A=А=K@\>V>@?I?{? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhF3*A; J arrival timeXh/ JXh4 JslackXhK@4D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!)y@1y @9Ay@Iy @eE@hq}l >d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}㋿V„=G?V?l >r9H= 0>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXhi?/ JXh4 JslackXhl >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}㋿V„=G?V?l >r9H= 0>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXhi?/ JXh4 JslackXhl >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}㋿V„=G?V?l >r9H= 0>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXhi?/ JXh4 JslackXhl >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}㋿V„=G?V?l >r9H= 0>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXhi?/ JXh4 JslackXhl >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}㋿V„=G?V?l >r9H= 0>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXhi?/ JXh4 JslackXhl >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb>}㋿V„=G?V?l >r9H= 0>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXhi?/ JXh4 JslackXhl >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsulg>}%O=G?O?|>>p9H=}?5>ʡ>t?ȶ>4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?5> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh>p g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXh@5?/ JXh4 JslackXh|>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsulg>}%O=G?O?|>>p9H=}?5>ʡ>t?ȶ>4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?5> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh>p g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXh@5?/ JXh4 JslackXh|>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsulg>}%O=G?O?|>>p9H=}?5>ʡ>t?ȶ>4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?5> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh>p g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh%; J arrival timeXh@5?/ JXh4 JslackXh|>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuv>}㋿V„=G?V?!>r9H=D>ʡ>t?ȶ>z4?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhD> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZd?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㋿; J arrival timeXh ?/ JXh4 JslackXh!>RRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu[@}A.A!<E.@!@A=А=E@Z>)\>33?t8?t?&1(?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh.A; J arrival timeXh~j/ JXh4 JslackXhE@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu^@}AM.A d=;E.@ @A=А=F@[>)\>6?t8?t?&1(?~?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh6? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhM.A; J arrival timeXh/ JXh4 JslackXhF@RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/CLR"$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X66Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu^@}AM.A d=;E.@ @A=А=F@[>)\>6?t8?t?&1(?~?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh6? gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhK@X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhM.A; J arrival timeXh/ JXh4 JslackXhF@D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!)y@1y @9Ay@Iy @e(@hq}>d rise - rise rise - rise  %73SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuA`>}c"y=ҍ?"?>/BD=/>l>r=*?J >VN?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) 73SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[24].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/>` .*SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh}?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[24].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)^ ,(SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh/Bw *&SFP_GEN[24].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhc; J arrival timeXh#۩?/ JXh4 JslackXh>4d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}'1=#ۉ?'1?]0>D=@5^>l>M"?J >rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhƫ?/ JXh4 JslackXh]0>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}'1=#ۉ?'1?]0>D=@5^>l>M"?J >rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhƫ?/ JXh4 JslackXh]0>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}'1=#ۉ?'1?]0>D=@5^>l>M"?J >rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhƫ?/ JXh4 JslackXh]0>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}'1=#ۉ?'1?]0>D=@5^>l>M"?J >rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhƫ?/ JXh4 JslackXh]0>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu>}'1=#ۉ?'1?]0>D=@5^>l>M"?J >rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhƫ?/ JXh4 JslackXh]0>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuq=>}ەQ͵=#ۉ?Q?u4>D=Sc>l>M"?J >:H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/ݔ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhە; J arrival timeXhj?/ JXh4 JslackXhu4>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuq=>}ەQ͵=#ۉ?Q?u4>D=Sc>l>M"?J >:H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/ݔ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhە; J arrival timeXhj?/ JXh4 JslackXhu4>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuq=>}ەQ͵=#ۉ?Q?u4>D=Sc>l>M"?J >:H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/ݔ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhە; J arrival timeXhj?/ JXh4 JslackXhu4>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuq=>}ەQ͵=#ۉ?Q?u4>D=Sc>l>M"?J >:H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/ݔ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhە; J arrival timeXhj?/ JXh4 JslackXhu4>Rg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}AmX/Az$^l21@z$@A=А=(@L>xi>v@6? -?A`%?$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(\@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23/OProp_C6LUT_SLICEL_I0_O JLUT2XhzfX9= WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)Xh> TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh~j @X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhmX/A; J arrival timeXh/ JXh4 JslackXh(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}AmX/Az$^l21@z$@A=А=(@L>xi>v@6? -?A`%?$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(\@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23/OProp_C6LUT_SLICEL_I0_O JLUT2XhzfX9= WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)Xh> YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh~j @X1Y2 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhmX/A; J arrival timeXh/ JXh4 JslackXh(@ %g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}Aq/A/$V<1@/$@A=А=:@L>im>zt@6? -?A`%?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhq/A; J arrival timeXh/ JXh4 JslackXh:@ %g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}Aq/A/$V<1@/$@A=А=:@L>im>zt@6? -?A`%?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhq/A; J arrival timeXh/ JXh4 JslackXh:@ %g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsup@}Al/A$1@$@A=А=6k@L>im>2t@6? -?A`%??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj @X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhl/A; J arrival timeXhn/ JXh4 JslackXh6k@ Qg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuO@}Aݕ/Ap%f;1@p%@A=А=݄@L>im>s@6? -?A`%?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA` @X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhݕ/A; J arrival timeXhM/ JXh4 JslackXh݄@ &g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuO@}Aݕ/Ap%f;1@p%@A=А=݄@L>im>s@6? -?A`%?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA` @X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhݕ/A; J arrival timeXhM/ JXh4 JslackXh݄@ Eg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuO@}Aݕ/Ap%f;1@p%@A=А=݄@L>im>s@6? -?A`%?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA` @X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhݕ/A; J arrival timeXhM/ JXh4 JslackXh݄@ %g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}Ađ/AB`%K;1@B`%@A=А= @L>im>Ss@6? -?A`%??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO @X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhđ/A; J arrival timeXh{/ JXh4 JslackXh @ Fg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1*X1Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@}Ađ/AB`%K;1@B`%@A=А= @L>im>Ss@6? -?A`%??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhnR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO @X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhđ/A; J arrival timeXh{/ JXh4 JslackXh @ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!)y@1y @9Ay@Iy @ew @hq}Ro >d rise - rise rise - rise  eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuGa>}KIs=C?K?Ro >D= 0>c>,?>>O?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh 0> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhRo >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C~zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu>}ǖQA=C?Q?41>uD=(\>c>,?>Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh(\> ~zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh/ݔ?X1Y4 (CLOCK_ROOT) |xg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhu zvg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhǖ; J arrival timeXh?/ JXh4 JslackXh41>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuo>}ߕl̈́=C?l?C1>ID=T>c>,?> P?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhT> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhI g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhߕ; J arrival timeXh1?/ JXh4 JslackXhC1>R|g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuZ@}Awd/A$<,=.@$@A=А=w @,G>>m@'?S?K??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh-R?} KGg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT){ IEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhwd/A; J arrival timeXhw/ JXh4 JslackXhw @ pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuZ@}Awd/A$<,=.@$@A=А=w @,G>>m@'?S?K??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh-R?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhwd/A; J arrival timeXhw/ JXh4 JslackXhw @ Pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@>#i@'?S?K??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhE?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhp/A; J arrival timeXh/ JXh4 JslackXhĈ@ Pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@>#i@'?S?K??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhE?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhp/A; J arrival timeXh/ JXh4 JslackXhĈ@ Pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@>#i@'?S?K??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhE?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhp/A; J arrival timeXh/ JXh4 JslackXhĈ@ Qg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@>L7i@'?S?K?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh\B?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh/A; J arrival timeXh/ JXh4 JslackXh_@ pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuZt@}Ah/AW%-U0=.@W%@A=А=?@,G>>`@'?S?K?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh ?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh/A; J arrival timeXhh/ JXh4 JslackXh?@ pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuZt@}Ah/AW%-U0=.@W%@A=А=?@,G>>`@'?S?K?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh ?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh/A; J arrival timeXhh/ JXh4 JslackXh?@ qg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuZt@}Ah/AW%-U0=.@W%@A=А=?@,G>>`@'?S?K?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh ?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh/A; J arrival timeXhh/ JXh4 JslackXh?@ qg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1*X1Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuZt@}Ah/AW%-U0=.@W%@A=А=?@,G>>`@'?S?K?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh ?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr> Jclock pessimismXh,G>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh/A; J arrival timeXhh/ JXh4 JslackXh?@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!)y@1y @9Ay@Iy @e@hq}/>d rise - rise rise - rise  _eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cuqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuMb>}3=Kw??/>&D=&1>A`>y?|>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh&1> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh& qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh/>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuMb>}3=Kw??/>&D=&1>A`>y?|>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh&1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh& g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh/>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuMb>}3=Kw??/>&D=&1>A`>y?|>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh&1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh& g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh/>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuMb>}3=Kw??/>&D=&1>A`>y?|>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh&1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh& g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh/>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuMb>}3=Kw??/>&D=&1>A`>y?|>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh&1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh& g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh/>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuMb>}3=Kw??/>&D=&1>A`>y?|>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh&1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhY?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh& g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh/>R-73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuGa>}GrFLȇ=Q?F?D>>D= 0>A`>A ?|>@?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh 0>` .*SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X1Y4 (CLOCK_ROOT)^ ,(SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh>w *&SFP_GEN[35].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhGr; J arrival timeXhz?/ JXh4 JslackXhD>4SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu>}{ˡ=u?ˡ?C4>4)9H=bX>A`>B`?|>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhcX?X1Y4 (CLOCK_ROOT) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]/C JFDCEXhzr> Jclock pessimismXh4) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXh(?/ JXh4 JslackXhC4>SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu>}{ˡ=u?ˡ?C4>4)9H=bX>A`>B`?|>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhcX?X1Y4 (CLOCK_ROOT) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]/C JFDCEXhzr> Jclock pessimismXh4) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXh(?/ JXh4 JslackXhC4>SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu>}{ˡ=u?ˡ?C4>4)9H=bX>A`>B`?|>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhcX?X1Y4 (CLOCK_ROOT) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]/C JFDCEXhzr> Jclock pessimismXh4) c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXh(?/ JXh4 JslackXhC4>73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuT5@}A/Az$:@z$@A=А=@Ub>V>,@F3?ɡ?M"??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh,@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j @X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXhUb>@ Jclock uncertaintyXh{ .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhj/ JXh4 JslackXh@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuT5@}A/Az$:@z$@A=А=@Ub>V>,@F3?ɡ?M"??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh,@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j @X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]/C JFDCEXhzr> Jclock pessimismXhUb>@ Jclock uncertaintyXh| .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhj/ JXh4 JslackXh@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu?5@}A*Aq=:ݾ:@q=@A=А=@P>V>O @F3?ɡ?M"?43?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhO @d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh{ .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXht/ JXh4 JslackXh@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu?5@}A*Aq=:ݾ:@q=@A=А=@P>V>O @F3?ɡ?M"?43?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhO @d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh| .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXht/ JXh4 JslackXh@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!@}Ag*AA߾:@@A=А=i*@HP>V>@F3?ɡ?M"?!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh{ .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg*A; J arrival timeXhef/ JXh4 JslackXhi*@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!@}Ag*AA߾:@@A=А=i*@HP>V>@F3?ɡ?M"?!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh| .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg*A; J arrival timeXhef/ JXh4 JslackXhi*@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!@}Ag*AA߾:@@A=А=i*@HP>V>@F3?ɡ?M"?!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh{ .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg*A; J arrival timeXhef/ JXh4 JslackXhi*@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!@}Ag*AA߾:@@A=А=i*@HP>V>@F3?ɡ?M"?!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh| .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg*A; J arrival timeXhef/ JXh4 JslackXhi*@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!@}Ag*AA߾:@@A=А=i*@HP>V>@F3?ɡ?M"?!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh{ .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg*A; J arrival timeXhef/ JXh4 JslackXhi*@473SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1*X1Y423RCLK_RCLK_BRAM_L_AUXCLMP_FT_X22Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!@}Ag*AA߾:@@A=А=i*@HP>V>@F3?ɡ?M"?!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv@X1Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh| .*SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg*A; J arrival timeXhef/ JXh4 JslackXhi*@4D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!)y@1y @9Ay@Iy @e0@hq}`6>d rise - rise rise - rise  373SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuhff>}薿:"="?:?`6>yD=}?5>> +?->thQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) 73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[25].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh}?5>c 1-SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhvx?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~??X1Y2 (CLOCK_ROOT)a /+SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhyz -)SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh薿; J arrival timeXh?/ JXh4 JslackXh`6>4373SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuhff>}薿:"="?:?`6>yD=}?5>> +?->thQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) 73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[25].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh}?5>c 1-SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhvx?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~??X1Y2 (CLOCK_ROOT)a /+SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhyz -)SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh薿; J arrival timeXh?/ JXh4 JslackXh`6>4(73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuhff>}薿:"="?:?`6>yD=}?5>> +?->thQ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) 73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[25].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh}?5>` .*SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhvx?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~??X1Y2 (CLOCK_ROOT)^ ,(SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhyx *&SFP_GEN[25].ngCCM_gbt/pwr_good_pre_regRemov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh薿; J arrival timeXh?/ JXh4 JslackXh`6>4RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuq=>}=Յ}?М=v?}??@>p9H=Mb>>1 ?->~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]/C JFDCEXhzr> Jclock pessimismXhp c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=Յ; J arrival timeXh?/ JXh4 JslackXh@>g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu_@}A*A넾)\/@@A=А=0@>>5^>G@*??5^?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhj$@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhI ? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhd;/ JXh4 JslackXh0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu_@}A*A넾)\/@@A=А=0@>>5^>G@*??5^?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhj$@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhI ? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhd;/ JXh4 JslackXh0@ 2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu S@}Ar*Ap|)\/@@A=А=K;@>>5^>C<@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh+?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhr*A; J arrival timeXh/ JXh4 JslackXhK;@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu S@}Ar*Ap|)\/@@A=А=K;@>>5^>C<@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh+?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhr*A; J arrival timeXh/ JXh4 JslackXhK;@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu S@}Ar*Ap|)\/@@A=А=K;@>>5^>C<@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh+?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhr*A; J arrival timeXh/ JXh4 JslackXhK;@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu23S@}AV*A c~)\/@ @A=А=|@4>>5^>l;@*??5^?_?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xhy?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C JFDCEXhzr> Jclock pessimismXh4>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV*A; J arrival timeXhG/ JXh4 JslackXh|@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu23S@}AV*A c~)\/@ @A=А=|@4>>5^>l;@*??5^?_?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xhy?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C JFDCEXhzr> Jclock pessimismXh4>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV*A; J arrival timeXhG/ JXh4 JslackXh|@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsulO@}A +A(+t)\/@(@A=А=m@>>5^> 8@*??5^? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh(1?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh +A; J arrival timeXhYd/ JXh4 JslackXhm@ ]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuxN@}A*AЗw)\/@@A=А=ږ@׭>>5^>7@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @{ IEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C JFDCEXhzr> Jclock pessimismXh׭>>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh"/ JXh4 JslackXhږ@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1*X1Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuN@}A+A1Dv)\/@1@A=А=!@8>>5^>|7@*??5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C JFDCEXhzr> Jclock pessimismXh8>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhn/ JXh4 JslackXh!@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!)y@1y @9Ay@Iy @e0@hq}M>d rise - rise rise - rise  d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuc>}IO=v??M>D=أp>S>?>̡%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhأp> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhI; J arrival timeXhe;?/ JXh4 JslackXhM>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuc>}IO=v??M>D=أp>S>?>̡%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhأp> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhI; J arrival timeXhe;?/ JXh4 JslackXhM>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuu>}=v??6O>'D=D>S>?>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhD> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh' g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh_?/ JXh4 JslackXh6O>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}aˡ=v?ˡ?R>D=v>S>?>U%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhv> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXha; J arrival timeXh?/ JXh4 JslackXhR>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}aˡ=v?ˡ?R>D=v>S>?>U%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhv> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXha; J arrival timeXh?/ JXh4 JslackXhR>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}aˡ=v?ˡ?R>D=v>S>?>U%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhv> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQX?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXha; J arrival timeXh?/ JXh4 JslackXhR>RRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}odn=أp?n?BS>o9H=q>S>G?>|?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhq> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhR?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh}?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]/C JFDCEXhzr> Jclock pessimismXho c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhod; J arrival timeXh̜?/ JXh4 JslackXhBS>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}odn=أp?n?BS>o9H=q>S>G?>|?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhq> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhR?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh}?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]/C JFDCEXhzr> Jclock pessimismXho c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhod; J arrival timeXh̜?/ JXh4 JslackXhBS>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}odn=أp?n?BS>o9H=q>S>G?>|?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhq> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhR?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh}?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]/C JFDCEXhzr> Jclock pessimismXho c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhod; J arrival timeXh̜?/ JXh4 JslackXhBS>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}odn=أp?n?BS>o9H=q>S>G?>|?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhq> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhR?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh}?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]/C JFDCEXhzr> Jclock pessimismXho c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhod; J arrival timeXh̜?/ JXh4 JslackXhBS>x73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)a /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXhz -)SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4y73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)a /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXh{ -)SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4|73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@d 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXh{ .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4}73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@d 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXh| .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4|73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@d 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXh{ .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4}73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@d 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXh| .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4x73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)a /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXhz -)SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4y73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuA @}A+Afb>@@A=А=0@#bJ>V>)\@2?p?"?ˡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh)\@c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= ?X1Y2 (CLOCK_ROOT)a /+SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXh#bJ>@ Jclock uncertaintyXh{ -)SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXht/ JXh4 JslackXh0@4|73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsue;@}AU+A5F뾵>@@A=А=@38J>V>V@2?p?"??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV@d 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh38J>@ Jclock uncertaintyXh{ .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhU+A; J arrival timeXh/ JXh4 JslackXh@4}73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsue;@}AU+A5F뾵>@@A=А=@38J>V>V@2?p?"??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfV>n *&SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV@d 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht#@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXh38J>@ Jclock uncertaintyXh| .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhU+A; J arrival timeXh/ JXh4 JslackXh@4D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!)y@1y @9Ay@Iy @eз@hq};=d rise - rise rise - rise  73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@H>}Ga堿 =43?a?;= D=P>>y?Z>;(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhP>` .*SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:h?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp?X1Y2 (CLOCK_ROOT)^ ,(SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh w *&SFP_GEN[27].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhG; J arrival timeXhI?/ JXh4 JslackXh;=4d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsurh>}QM~/i=Ԉ?M?)>z9H=E6>>-?Z> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhَ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhz g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhQ; J arrival timeXhT?/ JXh4 JslackXh)>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsurh>}QM~/i=Ԉ?M?)>z9H=E6>>-?Z> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhَ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhz g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhQ; J arrival timeXhT?/ JXh4 JslackXh)>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsurh>}QM~/i=Ԉ?M?)>z9H=E6>>-?Z> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhَ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXhz g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhQ; J arrival timeXhT?/ JXh4 JslackXh)>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsurh>}QM~/i=Ԉ?M?)>z9H=E6>>-?Z> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhَ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXhz g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhQ; J arrival timeXhT?/ JXh4 JslackXh)>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu'1>}ӒZ@=Ԉ?Z?uk@>P9H=@5^>>-?Z>/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhP g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӒ; J arrival timeXhH?/ JXh4 JslackXhuk@>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu'1>}ӒZ@=Ԉ?Z?uk@>P9H=@5^>>-?Z>/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhP g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӒ; J arrival timeXhH?/ JXh4 JslackXhuk@>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu'1>}ӒZ@=Ԉ?Z?uk@>P9H=@5^>>-?Z>/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhP g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӒ; J arrival timeXhH?/ JXh4 JslackXhuk@>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsǔ>}z=Ԉ?z?H>P9H=lg>>-?Z> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXhP g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh1?/ JXh4 JslackXhH>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsǔ>}z=Ԉ?z?H>P9H=lg>>-?Z> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhP g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh1?/ JXh4 JslackXhH>R1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu($@}A ,An9@n@A=А=з@P>5^>. @M??t8?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXho/ JXh4 JslackXhз@ 2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu($@}A ,An9@n@A=А=з@P>5^>. @M??t8?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXho/ JXh4 JslackXhз@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu($@}A ,An9@n@A=А=з@P>5^>. @M??t8?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXho/ JXh4 JslackXhз@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu($@}A ,An9@n@A=А=з@P>5^>. @M??t8?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXho/ JXh4 JslackXhз@ 2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu($@}A ,An9@n@A=А=з@P>5^>. @M??t8?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXho/ JXh4 JslackXhз@ =g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu4^"@}A,A9@@A=А=L@ P>5^>o @M??t8?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh^@X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C JFDCEXhzr> Jclock pessimismXh P>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh-/ JXh4 JslackXhL@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu4^"@}A,A9@@A=А=L@ P>5^>o @M??t8?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh^@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C JFDCEXhzr> Jclock pessimismXh P>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh-/ JXh4 JslackXhL@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A-,A~H{9@~@A=А= @HP>5^>I@M??t8?u?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhn@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh-,A; J arrival timeXhȪ/ JXh4 JslackXh @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A-,A~H{9@~@A=А= @HP>5^>I@M??t8?u?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhn@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh-,A; J arrival timeXhȪ/ JXh4 JslackXh @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR"#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT*X1Y22#RCLK_CLE_M_L_X31Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A-,A~H{9@~@A=А= @HP>5^>I@M??t8?u?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhĠ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhn@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C JFDCEXhzr> Jclock pessimismXhHP>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh-,A; J arrival timeXhȪ/ JXh4 JslackXh @ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3!)y@1y @9Ay@Iy @e@hq}%c=d rise - rise rise - rise  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuF>}#tQ=W9?t?%c=!9H=z>^ ???K "?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhz> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh#; J arrival timeXhV?/ JXh4 JslackXh%c=Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuF>}#tQ=W9?t?%c=!9H=z>^ ???K "?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhz> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh#; J arrival timeXhV?/ JXh4 JslackXh%c=Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuF>}#tQ=W9?t?%c=!9H=z>^ ???K "?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhz> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh#; J arrival timeXhV?/ JXh4 JslackXh%c=Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuF>}#tQ=W9?t?%c=!9H=z>^ ???K "?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhz> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh#; J arrival timeXhV?/ JXh4 JslackXh%c=Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuF>}#tQ=W9?t?%c=!9H=z>^ ???K "?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhz> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh#; J arrival timeXhV?/ JXh4 JslackXh%c=Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuJs>}=W9??ǹ>!9H=7A>^ ???M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh7A> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXhǹ>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuJs>}=W9??ǹ>!9H=7A>^ ???M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh7A> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXhǹ>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuJs>}=W9??ǹ>!9H=7A>^ ???M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh7A> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXhǹ>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuJs>}=W9??ǹ>!9H=7A>^ ???M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh7A> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXhǹ>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuJs>}=W9??ǹ>!9H=7A>^ ???M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh7A> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXhǹ>R(g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu`@}A13AJ 2+'}?m@J 2@A=А=@EB>|>uH@?w??&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @?x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xht@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C JFDCEXhzr> Jclock pessimismXhEB>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhH/ JXh4 JslackXh@ )g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu`@}A13AJ 2+'}?m@J 2@A=А=@EB>|>uH@?w??&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @?x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xht@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C JFDCEXhzr> Jclock pessimismXhEB>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhH/ JXh4 JslackXh@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu`@}A13AJ 2+'}?m@J 2@A=А=@EB>|>uH@?w??&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @?x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xht@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzr> Jclock pessimismXhEB>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhH/ JXh4 JslackXh@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu`@}A13AJ 2+'}?m@J 2@A=А=@EB>|>uH@?w??&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @?x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xht@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C JFDCEXhzr> Jclock pessimismXhEB>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh13A; J arrival timeXhH/ JXh4 JslackXh@ 4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuk\@}A3Ax1s)}?m@x1@A=А=s@N>|>D@?w???y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXhs@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu\@}A3AX1Z)}?m@X1@A=А=%@P>|>(D@?w??w?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh;@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A; J arrival timeXh / JXh4 JslackXh%@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu\@}A3AX1Z)}?m@X1@A=А=%@P>|>(D@?w??w?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh;@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A; J arrival timeXh / JXh4 JslackXh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu*\W@}A3Ash1{)}?m@sh1@A=А=w'@^O>|>l?@?w??;ߟ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C JFDCEXhzr> Jclock pessimismXh^O>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A; J arrival timeXhM/ JXh4 JslackXhw'@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuSV@}A3AG1>6*}?m@G1@A=А=+i@Q>|>>@?w???y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXh+i@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1*X3Y123RCLK_RCLK_BRAM_L_AUXCLMP_FT_X54Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuSV@}A3AG1>6*}?m@G1@A=А=+i@Q>|>>@?w???y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhN@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A; J arrival timeXh/ JXh4 JslackXh+i@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!)y@1y @9Ay@Iy @e@hq}2>d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu$>})\= ?)\?2>ʊ9H=K>1 ?U ?*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh ׃?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhʊ c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_regRemov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh2>kd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuC>}&žshތ=?sh? "=>QD=A`e>K> ?U ?.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhA`e> }yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) {wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhQ yug_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh&ž; J arrival timeXhgf?/ JXh4 JslackXh "=>R73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}ϨC=I ??wR>LD=> W>K>*?U ?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr> Jclock pessimismXhL{ .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhϨ; J arrival timeXho?/ JXh4 JslackXhwR>473SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}ϨC=I ??wR>LD=> W>K>*?U ?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXhL| .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhϨ; J arrival timeXho?/ JXh4 JslackXhwR>473SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}ϨC=I ??wR>LD=> W>K>*?U ?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzr> Jclock pessimismXhL{ .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhϨ; J arrival timeXho?/ JXh4 JslackXhwR>473SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}ϨC=I ??wR>LD=> W>K>*?U ?O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXhL| .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhϨ; J arrival timeXho?/ JXh4 JslackXhwR>4Fd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuA5>}^%KX=?%?f>XD=ˡ>K> ?U ?}.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhˡ> tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhi?X1Y2 (CLOCK_ROOT) rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhX plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh^; J arrival timeXh"?/ JXh4 JslackXhf>R73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}Ի?=I ??v>LD=Iz>K>*?U ?)\O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhIz>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXhL{ .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhP?/ JXh4 JslackXhv>473SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}Ի?=I ??v>LD=Iz>K>*?U ?)\O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhIz>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXhL| .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhP?/ JXh4 JslackXhv>473SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}Ի?=I ??v>LD=Iz>K>*?U ?)\O?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhIz>d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXhL{ .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhP?/ JXh4 JslackXhv>4g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu?@}A%1Ap-N@p-@A=А=@c>Cl>&1@?5?;?I ?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)XhA`@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%1A; J arrival timeXhK/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu?@}A%1Ap-N@p-@A=А=@c>Cl>&1@?5?;?I ?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)XhA`@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%1A; J arrival timeXhK/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu9@}A2A.,N@.@A=А=Q@*c>Cl>H*@?5?;?I ?#۩?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C JFDCEXhzr> Jclock pessimismXh*c>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh(/ JXh4 JslackXhQ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu9@}A2A.,N@.@A=А=Q@*c>Cl>H*@?5?;?I ?#۩?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C JFDCEXhzr> Jclock pessimismXh*c>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh(/ JXh4 JslackXhQ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuM*@}A1A/-ÙN@/-@A=А=H@>d>5^> @?5?;?I ?'1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhj? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh333? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh>d>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhz/ JXh4 JslackXhH@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuM*@}A1A/-ÙN@/-@A=А=H@>d>5^> @?5?;?I ?'1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhj? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh333? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh>d>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhz/ JXh4 JslackXhH@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu;(@}Az 2A-N@-@A=А=f@c>Cl>@?5?;?I ?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhz 2A; J arrival timeXh/ JXh4 JslackXhf@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu;(@}Az 2A-N@-@A=А=f@c>Cl>@?5?;?I ?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xht3@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhz 2A; J arrival timeXh/ JXh4 JslackXhf@ |73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu+@}A^0A(,ObxY@(,@A=А=Rj@t>V>E@?5?V?I ?$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE@d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE>@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXht>@ Jclock uncertaintyXh{ .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^0A; J arrival timeXhQ/ JXh4 JslackXhRj@4}73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR""RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X19Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu+@}A^0A(,ObxY@(,@A=А=Rj@t>V>E@?5?V?I ?$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE@d 2.SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE>@X1Y2 (CLOCK_ROOT)i 73SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr> Jclock pessimismXht>@ Jclock uncertaintyXh| .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^0A; J arrival timeXhQ/ JXh4 JslackXhRj@4D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!)y@1y @9Ay@Iy @eԞ@hq}>d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsurh>}g`=??>_9H=E6>>?Z>r=*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhE6> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhxi?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh_ c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXhأ?/ JXh4 JslackXh>d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuGa>})\q:=43?)\? >o*9H=/>>y?Z>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh/> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:h?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXho* g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh*\?/ JXh4 JslackXh >Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuGa>})\q:=43?)\? >o*9H=/>>y?Z>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh/> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:h?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXho* g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh*\?/ JXh4 JslackXh >R73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsunm>} )\M<=o?)\?T>/D=j<>>?Z>ˡ%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhj<>d 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXh/| .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhĠ?/ JXh4 JslackXhT>473SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsunm>} )\M<=o?)\?T>/D=j<>>?Z>ˡ%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhj<>d 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh/| .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhĠ?/ JXh4 JslackXhT>473SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsunm>} )\M<=o?)\?T>/D=j<>>?Z>ˡ%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhj<>d 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXh/| .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhĠ?/ JXh4 JslackXhT>473SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsunm>} )\M<=o?)\?T>/D=j<>>?Z>ˡ%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhj<>` .*SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)^ ,(SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh/w *&SFP_GEN[29].ngCCM_gbt/pwr_good_pre_regRemov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhĠ?/ JXh4 JslackXhT>473SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu k>}8-ҝ/o=o?ҝ?Ӯ">LD=5^:>>?Z>]"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh5^:>d 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6^?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXhL{ .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh8-; J arrival timeXh?/ JXh4 JslackXhӮ">473SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuD`e>}U+`堿n=o?`?$>2D=X94>>?Z>9(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhX94>d 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh2{ .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhU+; J arrival timeXhw?/ JXh4 JslackXh$>473SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuD`e>}U+`堿n=o?`?$>2D=X94>>?Z>9(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhX94>d 2.SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXh2| .*SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhU+; J arrival timeXhw?/ JXh4 JslackXh$>4g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuV=@}A,AL7i7@L7@A=А=Ԟ@mQ>(>8)@M?J ?t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh&@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C JFDCEXhzr> Jclock pessimismXhmQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh5^/ JXh4 JslackXhԞ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuV=@}A,AL7i7@L7@A=А=Ԟ@mQ>(>8)@M?J ?t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh&@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhmQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh5^/ JXh4 JslackXhԞ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuQ8@}A&y,A9 7@9@A=А=L@Q>(>$@M?J ?t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhף@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh&y,A; J arrival timeXh/ JXh4 JslackXhL@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuQ8@}A&y,A9 7@9@A=А=L@Q>(>$@M?J ?t8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhף@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh&y,A; J arrival timeXh/ JXh4 JslackXhL@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu;7@}A q,Au7@u@A=А=l@Q>(>Z$@M?J ?t8?k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh q,A; J arrival timeXhƷ/ JXh4 JslackXhl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu;7@}A q,Au7@u@A=А=l@Q>(>Z$@M?J ?t8?k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh q,A; J arrival timeXhƷ/ JXh4 JslackXhl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu;7@}A q,Au7@u@A=А=l@Q>(>Z$@M?J ?t8?k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/C JFDCEXhzr> Jclock pessimismXhQ>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh q,A; J arrival timeXhƷ/ JXh4 JslackXhl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu|7@}Ah,Ar7@r@A=А=Y<@*Q>>m#@M?J ?t8?z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf)> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhF? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhNb@X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh*Q>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh,A; J arrival timeXh/ JXh4 JslackXhY<@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu|7@}Ah,Ar7@r@A=А=Y<@*Q>>m#@M?J ?t8?z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf)> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhF? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhNb@X1Y3 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh*Q>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhh,A; J arrival timeXh/ JXh4 JslackXhY<@ =g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR"#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT*X1Y32#RCLK_CLE_M_L_X31Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuC3@}Am,A$7@$@A=А=@uQ>(>w@M?J ?t8?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C JFDCEXhzr> Jclock pessimismXhuQ>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhm,A; J arrival timeXhx/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!)y@1y @9Ay@Iy @elm@hq}>d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]/C JFDCEXhzr> Jclock pessimismXhE c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]/C JFDCEXhzr> Jclock pessimismXhE c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]/C JFDCEXhzr> Jclock pessimismXhE c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]/C JFDCEXhzr> Jclock pessimismXhE b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]/C JFDCEXhzr> Jclock pessimismXhE c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]/C JFDCEXhzr> Jclock pessimismXhE c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]/C JFDCEXhzr> Jclock pessimismXhE c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuأp>}1ˡF=q?ˡ?>E9H=v>>>y?->C+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]/C JFDCEXhzr> Jclock pessimismXhE b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXhy?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuJs>}sT㕿=q?T?>9H=7A>>y?->+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh7A> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhs; J arrival timeXhK?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuJs>}sT㕿=q?T?>9H=7A>>y?->+?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh7A> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhs; J arrival timeXhK?/ JXh4 JslackXh>Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu33+@}A+*A"DQ/@"@A=А=lm@f>>rh>@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh$?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C JFDCEXhzr> Jclock pessimismXhf>>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+*A; J arrival timeXh&/ JXh4 JslackXhlm@ Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu33+@}A+*A"DQ/@"@A=А=lm@f>>rh>@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh$?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C JFDCEXhzr> Jclock pessimismXhf>>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+*A; J arrival timeXh&/ JXh4 JslackXhlm@ Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu33+@}A+*A"DQ/@"@A=А=lm@f>>rh>@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh$?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhf>>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+*A; J arrival timeXh&/ JXh4 JslackXhlm@ Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu33+@}A+*A"DQ/@"@A=А=lm@f>>rh>@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh$?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/C JFDCEXhzr> Jclock pessimismXhf>>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+*A; J arrival timeXh&/ JXh4 JslackXhlm@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu'@}A*A T/@ @A=А='@>>xi>%@*?n?5^?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhX9? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfE= WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhT?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh)\/ JXh4 JslackXh'@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu'@}A*A T/@ @A=А='@>>xi>%@*?n?5^?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhX9? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfE= WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhT?X1Y3 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh)\/ JXh4 JslackXh'@ 3g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuR&@}AT*AS}/@S@A=А=0ê@>>rh>'1@*?n?5^?X?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT*A; J arrival timeXhy/ JXh4 JslackXh0ê@ 3g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu{&@}A9*A43/@43@A=А=@>>rh>P@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhE?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh9*A; J arrival timeXh/ JXh4 JslackXh@ Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu{&@}A9*A43/@43@A=А=@>>rh>P@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhE?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh9*A; J arrival timeXh/ JXh4 JslackXh@ Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1*X1Y324RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu{&@}A9*A43/@43@A=А=@>>rh>P@*?n?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhm@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhE?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh9*A; J arrival timeXh/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!)y@1y @9Ay@Iy @eĚ@hq}X4>d rise - rise rise - rise  73SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu$>}fߕ'1s=H?'1?X4>ìD="[>S>ff&?> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) 73SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[31].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh"[>` .*SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhbx?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X1Y3 (CLOCK_ROOT)^ ,(SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhìw *&SFP_GEN[31].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhfߕ; J arrival timeXhj?/ JXh4 JslackXhX4>4RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu9>}gD}?YÓ=v?}?? hB>h9H=e;_>S>l?>%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhe;_> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]/C JFDCEXhzr> Jclock pessimismXhh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhgD; J arrival timeXhh?/ JXh4 JslackXh hB>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu9>}gD}?YÓ=v?}?? hB>h9H=e;_>S>l?>%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhe;_> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]/C JFDCEXhzr> Jclock pessimismXhh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhgD; J arrival timeXhh?/ JXh4 JslackXh hB>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu9>}gD}?YÓ=v?}?? hB>h9H=e;_>S>l?>%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhe;_> fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]/C JFDCEXhzr> Jclock pessimismXhh b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhgD; J arrival timeXhh?/ JXh4 JslackXh hB>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu9>}gD}?YÓ=v?}?? hB>h9H=e;_>S>l?>%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhe;_> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]/C JFDCEXhzr> Jclock pessimismXhh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhgD; J arrival timeXhh?/ JXh4 JslackXh hB>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu9>}gD}?YÓ=v?}?? hB>h9H=e;_>S>l?>%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhe;_> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]/C JFDCEXhzr> Jclock pessimismXhh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhgD; J arrival timeXhh?/ JXh4 JslackXh hB>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu9>}gD}?YÓ=v?}?? hB>h9H=e;_>S>l?>%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhe;_> fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]/C JFDCEXhzr> Jclock pessimismXhh b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhgD; J arrival timeXhh?/ JXh4 JslackXh hB>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuq=>}D2=v??kC>9H=Mb>S>l?>̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXh?/ JXh4 JslackXhkC>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuq=>}D2=v??kC>9H=Mb>S>l?>̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXh?/ JXh4 JslackXhkC>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuq=>}D2=v??kC>9H=Mb>S>l?>̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXh?/ JXh4 JslackXhkC>/g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuC@}A*A1q=2@@A=А=Ě@y @>>t+@2??"?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXhy @>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhĚ@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuC@}A*A1q=2@@A=А=Ě@y @>>t+@2??"?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C JFDCEXhzr> Jclock pessimismXhy @>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhĚ@ /g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuC@}A*A1q=2@@A=А=Ě@y @>>t+@2??"?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhy @>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhĚ@ /g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuC@}A*A1q=2@@A=А=Ě@y @>>t+@2??"?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh+?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C JFDCEXhzr> Jclock pessimismXhy @>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhĚ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu@@}A/+AW9['q=2@W9@A=А=Ŏ@?>>r(@2??"?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C JFDCEXhzr> Jclock pessimismXh?>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/+A; J arrival timeXh/ JXh4 JslackXhŎ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu@@}A/+AW9['q=2@W9@A=А=Ŏ@?>>r(@2??"?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C JFDCEXhzr> Jclock pessimismXh?>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/+A; J arrival timeXh/ JXh4 JslackXhŎ@ ;g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu^@@}A!+A(q=2@(@A=А=ێ@~?>>Mb(@2??"?Ȧ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh(1?X1Y3 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C JFDCEXhzr> Jclock pessimismXh~?>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh!+A; J arrival timeXhg/ JXh4 JslackXhێ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuQ@@}A +A*q=2@@A=А=xМ@?>>'@2??"??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhb?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C JFDCEXhzr> Jclock pessimismXh?>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh +A; J arrival timeXhG/ JXh4 JslackXhxМ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu?@}A/+AW9['q=2@W9@A=А=2@?>>+'@2??"?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ 7?p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh?>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/+A; J arrival timeXh/ JXh4 JslackXh2@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR""RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X19Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu?@}A/+AW9['q=2@W9@A=А=2@?>>+'@2??"?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ 7?p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C JFDCEXhzr> Jclock pessimismXh?>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/+A; J arrival timeXh/ JXh4 JslackXh2@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!)y@1y @9Ay@Iy @eN@hq}o>d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsup=>}'1=?'1?o>@9H=C >G>9(?5^>IL?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh33?/ JXh4 JslackXho>73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsunm>}fr=1?r?d>D=j<>G>^)?5^>L?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhj<>c 1-SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)a /+SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhz -)SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhf; J arrival timeXh_?/ JXh4 JslackXhd>473SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsunm>}fr=1?r?d>D=j<>G>^)?5^>L?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhj<>c 1-SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)a /+SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh{ -)SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhf; J arrival timeXh_?/ JXh4 JslackXhd>4RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuhff>}St+۵=?+?>u9H=X94>G>9(?5^>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX94> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xho?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]/C JFDCEXhzr> Jclock pessimismXhu c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhSt; J arrival timeXhQ?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuhff>}St+۵=?+?>u9H=X94>G>9(?5^>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX94> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xho?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]/C JFDCEXhzr> Jclock pessimismXhu c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhSt; J arrival timeXhQ?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuw>}}PB=?P?(>|9H=ˡE>G>9(?5^> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/C JFDCEXhzr> Jclock pessimismXh| c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh~?/ JXh4 JslackXh(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuw>}}PB=?P?(>|9H=ˡE>G>9(?5^> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]/C JFDCEXhzr> Jclock pessimismXh| c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh~?/ JXh4 JslackXh(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuw>}}PB=?P?(>|9H=ˡE>G>9(?5^> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXh| c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh~?/ JXh4 JslackXh(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuw>}}PB=?P?(>|9H=ˡE>G>9(?5^> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/C JFDCEXhzr> Jclock pessimismXh| c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh~?/ JXh4 JslackXh(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuw>}}PB=?P?(>|9H=ˡE>G>9(?5^> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhXy?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]/C JFDCEXhzr> Jclock pessimismXh| c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh~?/ JXh4 JslackXh(>g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuԄ@}A/Aˡ%w>;1@ˡ%@A=А=N@H>>zv@/??|?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhpM@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf +> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh\"? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhh @X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhN@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuԄ@}A/Aˡ%w>;1@ˡ%@A=А=N@H>>zv@/??|?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhpM@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf +> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh\"? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhh @X1Y4 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhN@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsui@}AM*AS41@S@A=А=@A>V>`@/??|?Ȧ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> UQg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/AS[0] Jnet (fo=32, routed)Xh`@ gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh+?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhA>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhM*A; J arrival timeXh/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuSe@}A/A&<1@&@A=А=oc@H>>S@/??|?(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhoc@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuSe@}A/A&<1@&@A=А=oc@H>>S@/??|?(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhoc@ ,g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsupe@}An/A%c<1@%@A=А=@H>>33S@/??|?1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)XhT @X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhn/A; J arrival timeXhF/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsud@}A/AE&S<1@E&@A=А=v@H>>\R@/??|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?5@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhZd/ JXh4 JslackXhv@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsud@}A/AE&S<1@E&@A=А=v@H>>\R@/??|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?5@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhZd/ JXh4 JslackXhv@ 8g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsujd@}A/AE&S<1@E&@A=А=@@H>>-R@/??|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?5@X1Y4 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh33/ JXh4 JslackXh@@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu(d@}A/A$&2<1@$&@A=А=P@H>>Q@/??|?j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'10@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh{@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C JFDCEXhzr> Jclock pessimismXhH>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXho/ JXh4 JslackXhP@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!)y@1y @9Ay@Iy @e@hq}>>d rise - rise rise - rise  73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu^d;>}U$=bx?$?>>:0D=q= >G>^ ?5^>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhq= >` .*SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!?X1Y4 (CLOCK_ROOT)^ ,(SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh:0w *&SFP_GEN[33].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhU; J arrival timeXht?/ JXh4 JslackXh>>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuMb>}=bx??>:5>#D=&1>G>^ ?5^>z&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh&1>c 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y4 (CLOCK_ROOT)a /+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh#z -)SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXh>:5>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuMb>}=bx??>:5>#D=&1>G>^ ?5^>z&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh&1>c 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y4 (CLOCK_ROOT)a /+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh#{ -)SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXh>:5>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuMb>}=bx??>:5>#D=&1>G>^ ?5^>z&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh&1>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXh#{ .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXh>:5>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuMb>}=bx??>:5>#D=&1>G>^ ?5^>z&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh&1>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh#| .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXh>:5>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsulg>}燁A`{=bx?A`?n;>#D=E6>G>^ ?5^>&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE6>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh#{ .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh燁; J arrival timeXh?/ JXh4 JslackXhn;>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuC>}n$A.=bx?$?WQC>CD=A`e>G>^ ?5^>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhA`e>c 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!?X1Y4 (CLOCK_ROOT)a /+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXhCz -)SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhn; J arrival timeXhٞ?/ JXh4 JslackXhWQC>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuC>}n$A.=bx?$?WQC>CD=A`e>G>^ ?5^>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhA`e>c 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!?X1Y4 (CLOCK_ROOT)a /+SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXhC{ -)SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhn; J arrival timeXhٞ?/ JXh4 JslackXhWQC>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu>}+KnZ=bx?K?YS>k#D=@5^>G>^ ?5^>~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ׃?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhk#{ .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh+; J arrival timeXh?/ JXh4 JslackXhYS>473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu>}+KnZ=bx?K?YS>k#D=@5^>G>^ ?5^>~*?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^Z?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ׃?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXhk#| .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh+; J arrival timeXh?/ JXh4 JslackXhYS>4/g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsun*@}AF*A> 1@@A=А=@'RA>|>~@/??|?A`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/C JFDCEXhzr> Jclock pessimismXh'RA>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF*A; J arrival timeXh­/ JXh4 JslackXh@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsun*@}AF*A> 1@@A=А=@'RA>|>~@/??|?A`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/C JFDCEXhzr> Jclock pessimismXh'RA>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF*A; J arrival timeXh­/ JXh4 JslackXh@ /g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsun*@}AF*A> 1@@A=А=@'RA>|>~@/??|?A`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C JFDCEXhzr> Jclock pessimismXh'RA>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF*A; J arrival timeXh­/ JXh4 JslackXh@ /g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu)@}A)*A~1@~@A=А=ͧ@eWA>|>I @/??|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh/?X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzr> Jclock pessimismXheWA>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)*A; J arrival timeXh8/ JXh4 JslackXhͧ@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu)@}A)*A~1@~@A=А=ͧ@eWA>|>I @/??|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh/?X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C JFDCEXhzr> Jclock pessimismXheWA>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)*A; J arrival timeXh8/ JXh4 JslackXhͧ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu'@}A*Ar1@@A=А=]@*A>n>ˡ@/??|?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhsh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhF? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh= ?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh*A>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXh]@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu'@}A*Ar1@@A=А=]@*A>n>ˡ@/??|?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhsh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhF? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh= ?X1Y4 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh*A>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXh]@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu̡%@}A8*A]1@]@A=А=F@TA>|>- @/??|?~??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C JFDCEXhzr> Jclock pessimismXhTA>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh8*A; J arrival timeXh*\/ JXh4 JslackXhF@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu̡%@}A8*A]1@]@A=А=F@TA>|>- @/??|?~??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C JFDCEXhzr> Jclock pessimismXhTA>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh8*A; J arrival timeXh*\/ JXh4 JslackXhF@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR""RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X19Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu̡%@}A8*A]1@]@A=А=F@TA>|>- @/??|?~??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhU@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C JFDCEXhzr> Jclock pessimismXhTA>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh8*A; J arrival timeXh*\/ JXh4 JslackXhF@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!)y@1y @9Ay@Iy @ez0@hq}|=d rise - rise rise - rise  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu@>}j^?=㥛?^?|='9H=V>C ?V?A ?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xȟ?X1Y6 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhE?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhF?/ JXh4 JslackXh|=Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu@>}j^?=㥛?^?|='9H=V>C ?V?A ?I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xȟ?X1Y6 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhE?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhF?/ JXh4 JslackXh|=RRNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuu>}t&=?t?i>Z$9H=C>C ??A ?)?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]/C JFDCEXhzr> Jclock pessimismXhZ$ d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhi>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuq>}'c=?c?=>a$9H=|?>C ??A ?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|?> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]/C JFDCEXhzr> Jclock pessimismXha$ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh'; J arrival timeXh+?/ JXh4 JslackXh=>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuq>}'c=?c?=>a$9H=|?>C ??A ?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|?> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]/C JFDCEXhzr> Jclock pessimismXha$ d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh'; J arrival timeXh+?/ JXh4 JslackXh=>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuq>}'c=?c?=>a$9H=|?>C ??A ?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|?> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]/C JFDCEXhzr> Jclock pessimismXha$ d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh'; J arrival timeXh+?/ JXh4 JslackXh=>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuq>}'c=?c?=>a$9H=|?>C ??A ?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|?> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]/C JFDCEXhzr> Jclock pessimismXha$ d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh'; J arrival timeXh+?/ JXh4 JslackXh=>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuq>}'c=?c?=>a$9H=|?>C ??A ?(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|?> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]/C JFDCEXhzr> Jclock pessimismXha$ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh'; J arrival timeXh+?/ JXh4 JslackXh=>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuw>}r`=?r?y%>\$9H=ˡE>C ??A ?_)?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]/C JFDCEXhzr> Jclock pessimismXh\$ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhy%>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuw>}r`=?r?y%>\$9H=ˡE>C ??A ?_)?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]/C JFDCEXhzr> Jclock pessimismXh\$ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhy%>%g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<@}AZr3A~2ܘT@~2@A=А=z0@{#s>>D$@?u?(?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C JFDCEXhzr> Jclock pessimismXh{#s>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZr3A; J arrival timeXh:/ JXh4 JslackXhz0@ &g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<@}AZr3A~2ܘT@~2@A=А=z0@{#s>>D$@?u?(?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C JFDCEXhzr> Jclock pessimismXh{#s>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZr3A; J arrival timeXh:/ JXh4 JslackXhz0@ %g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<@}AZr3A~2ܘT@~2@A=А=z0@{#s>>D$@?u?(?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C JFDCEXhzr> Jclock pessimismXh{#s>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZr3A; J arrival timeXh:/ JXh4 JslackXhz0@ %g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<@}AZr3A~2ܘT@~2@A=А=z0@{#s>>D$@?u?(?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C JFDCEXhzr> Jclock pessimismXh{#s>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZr3A; J arrival timeXh:/ JXh4 JslackXhz0@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu9@}A\)3AX1T@X1@A=А=a@Rs>>$!@?u?(?ff?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG@X1Y6 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXhRs>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh\)3A; J arrival timeXh/ JXh4 JslackXha@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu2@}Ahv3A[2 [T@[2@A=А= @ s>>H@?u?(?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C JFDCEXhzr> Jclock pessimismXh s>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhhv3A; J arrival timeXh</ JXh4 JslackXh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu2@}Ahv3A[2 [T@[2@A=А= @ s>>H@?u?(?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C JFDCEXhzr> Jclock pessimismXh s>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhhv3A; J arrival timeXh</ JXh4 JslackXh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu2@}Ahv3A[2 [T@[2@A=А= @ s>>H@?u?(?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C JFDCEXhzr> Jclock pessimismXh s>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhhv3A; J arrival timeXh</ JXh4 JslackXh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu2@}Ahv3A[2 [T@[2@A=А= @ s>>H@?u?(?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/C JFDCEXhzr> Jclock pessimismXh s>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhhv3A; J arrival timeXh</ JXh4 JslackXh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR"#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT*X1Y62#RCLK_CLE_M_L_X31Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu.@}A93A1T@1@A=А=ʸ@/Hs>>@?u?(?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf!r> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh9@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C JFDCEXhzr> Jclock pessimismXh/Hs>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh93A; J arrival timeXh^/ JXh4 JslackXhʸ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!)y@1y @9Ay@Iy @eՉq@hq}W>d rise - rise rise - rise  }eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C~zg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu;ߏ>}VȦ=?Ȧ?W>9H=im>Т>'?j>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhim> ~zg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhS?X1Y9 (CLOCK_ROOT) |xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh zvg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhV; J arrival timeXh|?/ JXh4 JslackXhW>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsut>}+O=?+?"[>.9H=kt>Т>'?j>L7I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhkt> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXh"[>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsut>}+O=?+?"[>.9H=kt>Т>'?j>L7I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhkt> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXh"[>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsut>}+O=?+?"[>.9H=kt>Т>'?j>L7I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhkt> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXh"[>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsut>}+O=?+?"[>.9H=kt>Т>'?j>L7I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhkt> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXh"[>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu >}%@lr=?l?)]>9H=x>Т>'?j>_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhx> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%@; J arrival timeXha?/ JXh4 JslackXh)]>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu >}%@lr=?l?)]>9H=x>Т>'?j>_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhx> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%@; J arrival timeXha?/ JXh4 JslackXh)]>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu >}%@lr=?l?)]>9H=x>Т>'?j>_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhx> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%@; J arrival timeXha?/ JXh4 JslackXh)]>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu >}%@lr=?l?)]>9H=x>Т>'?j>_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhx> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%@; J arrival timeXha?/ JXh4 JslackXh)]>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu >}%@lr=?l?)]>9H=x>Т>'?j>_I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhx> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%@; J arrival timeXha?/ JXh4 JslackXh)]>Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsud;@}A/AK'z=w/@K'@A=А=Չq@E>>@n2? jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho[@ gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45/I0 JXhzr fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf"y> XTg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh+? UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhՉq@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0*X1Y92"RCLK_DSP_L_X19Y569/CLK_VDISTR_TOP0:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsud;@}A/AK'z=w/@K'@A=А=Չq@E>>@n2? jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho[@ gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45/I0 JXhzr fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf"y> XTg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh+? ZVg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT) XTg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh VRg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXhՉq@ -g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhp=?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh+@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh)t@ ,g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhp=?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh+@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh)t@ ,g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>Q~@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh)\@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhr/ JXh4 JslackXhy~@ ,g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>Q~@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh)\@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhr/ JXh4 JslackXhy~@ ,g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>Q~@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh)\@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhr/ JXh4 JslackXhy~@ ,g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>z~@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhNb?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXh}@ -g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>z~@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhNb?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXh}@ ,g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>z~@n2? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhY@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhNb?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXhE>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXh}@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!)y@1y @9Ay@Iy @eVh@hq}O2>d rise - rise rise - rise  73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr> Jclock pessimismXh;{ .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>4 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh;| .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>473SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzr> Jclock pessimismXh;{ .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>4 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh;| .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>473SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr> Jclock pessimismXh;{ .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>4 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr> Jclock pessimismXh;| .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>473SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}SK7ُ=-?K7?O2>;D=N>M>E,?Zd>M?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhN>d 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXh;{ .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhS; J arrival timeXh.?/ JXh4 JslackXhO2>4SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuSc>}Vq=`+={?q=?$]3>o69H=&1>M>O-?Zd> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhv~?X1Y9 (CLOCK_ROOT) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhȖ?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXho6 d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhV; J arrival timeXh~?/ JXh4 JslackXh$]3>SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}]q=]V={?q=?C=>9H=/]>M>O-?Zd> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhv~?X1Y9 (CLOCK_ROOT) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhȖ?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh]; J arrival timeXh?/ JXh4 JslackXhC=>SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}]q=]V={?q=?C=>9H=/]>M>O-?Zd> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhv~?X1Y9 (CLOCK_ROOT) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhȖ?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]/C JFDCEXhzr> Jclock pessimismXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh]; J arrival timeXh?/ JXh4 JslackXhC=>Pg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}A^ 0A'No=ˡ-@'@A=А=Vh@C>H>sh@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhjT?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^ 0A; J arrival timeXhm/ JXh4 JslackXhVh@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>Z@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhIL?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhi/A; J arrival timeXh/ JXh4 JslackXhxi@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>Z@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhIL?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhi/A; J arrival timeXh/ JXh4 JslackXhxi@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>1@`0?j? ?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh^I?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8/A; J arrival timeXh+/ JXh4 JslackXhRj@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>1@`0?j? ?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh^I?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8/A; J arrival timeXh+/ JXh4 JslackXhRj@ Qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuF@}A8/A< '۴=ˡ-@< '@A=А=Rj@C>H>1@`0?j? ?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh^I?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8/A; J arrival timeXh+/ JXh4 JslackXhRj@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>Zd@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^ 0A; J arrival timeXhT/ JXh4 JslackXh^l@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>Zd@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^ 0A; J arrival timeXhT/ JXh4 JslackXh^l@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>Zd@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^ 0A; J arrival timeXhT/ JXh4 JslackXh^l@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@H>Zd@`0?j? ??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhˡ]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhD?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhn@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C JFDCEXhzr> Jclock pessimismXhC>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh^ 0A; J arrival timeXhT/ JXh4 JslackXh^l@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!)y@1y @9Ay@Iy @e@hq}[>d rise - rise rise - rise  73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}Rҭ=ʑ?ҭ?[> !9D=> W>K>q= ? ?'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6^?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXh !9{ .*SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhR; J arrival timeXhв?/ JXh4 JslackXh[>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}Rҭ=ʑ?ҭ?[> !9D=> W>K>q= ? ?'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6^?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXh !9| .*SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhR; J arrival timeXhв?/ JXh4 JslackXh[>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}Rҭ=ʑ?ҭ?[> !9D=> W>K>q= ? ?'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6^?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXh !9{ .*SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhR; J arrival timeXhв?/ JXh4 JslackXh[>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}Rҭ=ʑ?ҭ?[> !9D=> W>K>q= ? ?'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh> W>d 2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh6^?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXh !9| .*SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhR; J arrival timeXhв?/ JXh4 JslackXh[>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu> >}W!}=ʑ??Di>D=|>K>q= ? ?̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y6 (CLOCK_ROOT)a /+SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhz -)SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXhP?/ JXh4 JslackXhDi>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu> >}W!}=ʑ??Di>D=|>K>q= ? ?̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y6 (CLOCK_ROOT)a /+SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh{ -)SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXhP?/ JXh4 JslackXhDi>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu> >}W!}=ʑ??Di>D=|>K>q= ? ?̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y6 (CLOCK_ROOT)a /+SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXhz -)SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXhP?/ JXh4 JslackXhDi>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu> >}W!}=ʑ??Di>D=|>K>q= ? ?̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y6 (CLOCK_ROOT)a /+SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXh{ -)SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXhP?/ JXh4 JslackXhDi>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu> >}W!}=ʑ??Di>D=|>K>q= ? ?̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>d 2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXhP?/ JXh4 JslackXhDi>473SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu> >}W!}=ʑ??Di>D=|>K>q= ? ?̡%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>d 2.SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXhP?/ JXh4 JslackXhDi>4=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu [@}A"u1A+dA`M@+@A=А=@rsc>~j>ZL@{?E??|??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xht@X1Y6 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C JFDCEXhzr> Jclock pessimismXhrsc>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh"u1A; J arrival timeXh&1/ JXh4 JslackXh@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu5Y@}Aw1Al+A`M@l+@A=А=2@cc>~j>HJ@{?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C JFDCEXhzr> Jclock pessimismXhcc>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhw1A; J arrival timeXht/ JXh4 JslackXh2@ 2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu5Y@}Aw1Al+A`M@l+@A=А=2@cc>~j>HJ@{?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C JFDCEXhzr> Jclock pessimismXhcc>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhw1A; J arrival timeXht/ JXh4 JslackXh2@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu5Y@}Aw1Al+A`M@l+@A=А=2@cc>~j>HJ@{?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzr> Jclock pessimismXhcc>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhw1A; J arrival timeXht/ JXh4 JslackXh2@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu5Y@}Aw1Al+A`M@l+@A=А=2@cc>~j>HJ@{?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C JFDCEXhzr> Jclock pessimismXhcc>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhw1A; J arrival timeXht/ JXh4 JslackXh2@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuV@}A1A1,EA`M@1,@A=А=@v^c>~j> H@{?E??E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C JFDCEXhzr> Jclock pessimismXhv^c>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhz/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuV@}A1A1,EA`M@1,@A=А=@v^c>~j> H@{?E??E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C JFDCEXhzr> Jclock pessimismXhv^c>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhz/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuV@}A1A1,EA`M@1,@A=А=@v^c>~j> H@{?E??E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C JFDCEXhzr> Jclock pessimismXhv^c>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhz/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuVV@}Aw1Al+A`M@l+@A=А=?@cc>~j>G@{?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C JFDCEXhzr> Jclock pessimismXhcc>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhw1A; J arrival timeXh"/ JXh4 JslackXh?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR"$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X18Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuVV@}Aw1Al+A`M@l+@A=А=?@cc>~j>G@{?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_B6LUT_SLICEL_I0_O JLUT3XhzfE= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh-2@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C JFDCEXhzr> Jclock pessimismXhcc>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhw1A; J arrival timeXh"/ JXh4 JslackXh?@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4!)y@1y @9Ay@Iy @e}@hq}Ө=d rise - rise rise - rise  62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu@H>}N17=S?1?Ө==D=P>>??+'?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhP>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr> Jclock pessimismXh=z -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXhΧ?/ JXh4 JslackXhӨ=462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXhx@z -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXhx@{ -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXhx@z -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXhx@{ -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXhx@z -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhx@{ -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr> Jclock pessimismXhx@z -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuKl>}5cm竿p=S?m?64>x@D=Zd;>>??z&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȖ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr> Jclock pessimismXhx@{ -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5c; J arrival timeXhI?/ JXh4 JslackXh64>462SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuأp>}Bƫ(_=S?ƫ?U>CD=|?>>??&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|?>c 1-SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXhCz -)SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhB; J arrival timeXh̬?/ JXh4 JslackXhU>4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu~?e@}A2A+4$pe@+@A=А=}@(]>Cl>vV@1?%@c;?A`?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh~@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/C JFDCEXhzr> Jclock pessimismXh(]>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhX/ JXh4 JslackXh}@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu~?e@}A2A+4$pe@+@A=А=}@(]>Cl>vV@1?%@c;?A`?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh~@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C JFDCEXhzr> Jclock pessimismXh(]>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhX/ JXh4 JslackXh}@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu~?e@}A2A+4$pe@+@A=А=}@(]>Cl>vV@1?%@c;?A`?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh~@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/C JFDCEXhzr> Jclock pessimismXh(]>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhX/ JXh4 JslackXh}@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsud@}A2A +$pe@ +@A=А=N~@_>Cl>U@1?%@c;??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh5^@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C JFDCEXhzr> Jclock pessimismXh_>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh&/ JXh4 JslackXhN~@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsud@}A2A +$pe@ +@A=А=N~@_>Cl>U@1?%@c;??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh5^@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C JFDCEXhzr> Jclock pessimismXh_>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh&/ JXh4 JslackXhN~@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsud@}A2A+d$pe@+@A=А=~@a>Cl>OU@1?%@c;??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)XhM@X3Y1 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh/ JXh4 JslackXh~@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsud@}A2A+d$pe@+@A=А=~@a>Cl>OU@1?%@c;??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)XhM@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh/ JXh4 JslackXh~@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsud@}A2A+d$pe@+@A=А=~@a>Cl>OU@1?%@c;??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)XhM@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXh/ JXh4 JslackXh~@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsutc@}A 2A+*y%pe@+@A=А=,E@c>Cl> T@1?%@c;?j?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh-@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhr/ JXh4 JslackXh,E@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR"#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT*X3Y12#RCLK_CLE_M_L_X63Y149/CLK_VDISTR_BOT:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsutc@}A 2A+*y%pe@+@A=А=,E@c>Cl> T@1?%@c;?j?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh|/@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh> G@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh-@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 2A; J arrival timeXhr/ JXh4 JslackXh,E@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!)y@1y @9Ay@Iy @eNt@hq},N>d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu>}~SW= p?S?,N>-0$9H== W>S>?>G!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh= W> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhnR?X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhw?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh-0$ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXhL7?/ JXh4 JslackXh,N>d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu->}xz=53s?z?V>u.D=l{>S> ?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhu. g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhe;?/ JXh4 JslackXhV>R73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu>}uYZɂ=zt?Z?Sb>#D=%>S>?>S#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh%>c 1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y7 (CLOCK_ROOT)a /+SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh#z -)SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhuY; J arrival timeXhأ?/ JXh4 JslackXhSb>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu>}uYZɂ=zt?Z?Sb>#D=%>S>?>S#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh%>c 1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y7 (CLOCK_ROOT)a /+SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh#{ -)SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhuY; J arrival timeXhأ?/ JXh4 JslackXhSb>4/g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuJ@}An*AM0@M@A=А=Nt@9{@>t>A8@2??"?o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)Xhz?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C JFDCEXhzr> Jclock pessimismXh9{@>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn*A; J arrival timeXh½/ JXh4 JslackXhNt@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuJ@}An*AM0@M@A=А=Nt@9{@>t>A8@2??"?o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)Xhz?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C JFDCEXhzr> Jclock pessimismXh9{@>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn*A; J arrival timeXh½/ JXh4 JslackXhNt@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuJ@}An*AM0@M@A=А=Nt@9{@>t>A8@2??"?o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)Xhz?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C JFDCEXhzr> Jclock pessimismXh9{@>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn*A; J arrival timeXh½/ JXh4 JslackXhNt@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuH J@}AR*A-@0@-@A=А=@v@>t>7@2??"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhX9?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C JFDCEXhzr> Jclock pessimismXhv@>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXhp/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuH J@}AR*A-@0@-@A=А=@v@>t>7@2??"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhX9?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C JFDCEXhzr> Jclock pessimismXhv@>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXhp/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuH J@}AR*A-@0@-@A=А=@v@>t>7@2??"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhX9?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C JFDCEXhzr> Jclock pessimismXhv@>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXhp/ JXh4 JslackXh@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuH J@}AR*A-@0@-@A=А=@v@>t>7@2??"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhX9?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C JFDCEXhzr> Jclock pessimismXhv@>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXhp/ JXh4 JslackXh@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuH J@}AR*A-@0@-@A=А=@v@>t>7@2??"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhX9?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzr> Jclock pessimismXhv@>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXhp/ JXh4 JslackXh@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuH J@}AR*A-@0@-@A=А=@v@>t>7@2??"?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhX9?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C JFDCEXhzr> Jclock pessimismXhv@>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]Recov_FFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXhp/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR""RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0*X1Y72"RCLK_DSP_L_X19Y509/CLK_VDISTR_BOT0:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuTE@}Aa*Aq=z}0@q=@A=А=ҙ@}@>t>t3@2??"??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhˡ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhZ?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C JFDCEXhzr> Jclock pessimismXh}@>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha*A; J arrival timeXh)\/ JXh4 JslackXhҙ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!)y@1y @9Ay@Iy @eRz@hq}@">d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuxi>}5Z2=bx?Z?@">u9H=K7>>O ?->:(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhK7> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh5^Z?X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xha?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhu c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXhL7?/ JXh4 JslackXh@">d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq=>}҅}? =kt?}??8>D=Sc>> ?->~*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhSc> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh҅; J arrival timeXh?/ JXh4 JslackXh8>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsud;>}'䇿K!=kt?K?BGR>[D=>> ?->.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ׃?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh[ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh'䇿; J arrival timeXh-?/ JXh4 JslackXhBGR>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsud;>}'䇿K!=kt?K?BGR>[D=>> ?->.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ׃?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh[ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh'䇿; J arrival timeXh-?/ JXh4 JslackXhBGR>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsud;>}'䇿K!=kt?K?BGR>[D=>> ?->.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ׃?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh[ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh'䇿; J arrival timeXh-?/ JXh4 JslackXhBGR>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu>}b=kt??1f>v$D=!r>> ?->2,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh!r> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh]?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhv$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhٞ?/ JXh4 JslackXh1f>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuth>}Ձ•opZ=kt?•?g>$D=q>> ?->+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhq> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhՁ; J arrival timeXhS?/ JXh4 JslackXhg>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuth>}Ձ•opZ=kt?•?g>$D=q>> ?->+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhq> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhՁ; J arrival timeXhS?/ JXh4 JslackXhg>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuth>}Ձ•opZ=kt?•?g>$D=q>> ?->+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhq> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhՁ; J arrival timeXhS?/ JXh4 JslackXhg>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuth>}Ձ•opZ=kt?•?g>$D=q>> ?->+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhq> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh> W?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhՁ; J arrival timeXhS?/ JXh4 JslackXhg>RSg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuu@}A*A z󄾵P/@ @A=А=Rz@M>>n>n@*?S?5^?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhT?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C JFDCEXhzr> Jclock pessimismXhM>>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhZ/ JXh4 JslackXhRz@ Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuu@}A*A z󄾵P/@ @A=А=Rz@M>>n>n@*?S?5^?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhT?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C JFDCEXhzr> Jclock pessimismXhM>>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhZ/ JXh4 JslackXhRz@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuu@}A*A z󄾵P/@ @A=А=Rz@M>>n>n@*?S?5^?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhT?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzr> Jclock pessimismXhM>>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhZ/ JXh4 JslackXhRz@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuu@}A*A z󄾵P/@ @A=А=Rz@M>>n>n@*?S?5^?:?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhT?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C JFDCEXhzr> Jclock pessimismXhM>>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhZ/ JXh4 JslackXhRz@ Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuu@}A*AZd聾P/@Zd@A=А=B @>>n>tc@*?S?5^?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhB @ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuxo@}A(*AtgP/@t@A=А=k@>>n>p]@*?S?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(*A; J arrival timeXh/ JXh4 JslackXhk@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu+o@}AR*AP/@@A=А=zx@>>n>/\@*?S?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXh*\/ JXh4 JslackXhzx@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu+o@}AR*AP/@@A=А=zx@>>n>/\@*?S?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh+?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhR*A; J arrival timeXh*\/ JXh4 JslackXhzx@ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuSn@}AE*AcP/@@A=А=@>>n>j\@*?S?5^?"۩?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh= ?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhE*A; J arrival timeXh"/ JXh4 JslackXh@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1*X1Y724RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuj@}A`*AF1~P/@F@A=А=ֵ@u>>n>rX@*?S?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh33;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzf+> @p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhZ@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhK?X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXhu>>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh`*A; J arrival timeXh&/ JXh4 JslackXhֵ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!)y@1y @9Ay@Iy @e2@hq}>>d rise - rise rise - rise  73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/]>}}PE=D?P?>>?D=1,>M>r=*?Zd>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh1,>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh[d{?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh?{ .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh'1?/ JXh4 JslackXh>>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/]>}}PE=D?P?>>?D=1,>M>r=*?Zd>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh1,>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh[d{?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh?| .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh'1?/ JXh4 JslackXh>>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/]>}}PE=D?P?>>?D=1,>M>r=*?Zd>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh1,>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh[d{?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXh?{ .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh'1?/ JXh4 JslackXh>>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/]>}}PE=D?P?>>?D=1,>M>r=*?Zd>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh1,>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh[d{?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh?| .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh'1?/ JXh4 JslackXh>>4RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuhff>}5=I??>3>79H=X94>M>^)?Zd>OM?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX94> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhGz?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXh7 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh>3>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuhff>}5=I??>3>79H=X94>M>^)?Zd>OM?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX94> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhGz?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]/C JFDCEXhzr> Jclock pessimismXh7 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh>3>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuCl>}dXezB=I?X?6>79H=5^:>M>^)?Zd>|N?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhGz?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/C JFDCEXhzr> Jclock pessimismXh7 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh"۩?/ JXh4 JslackXh6>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuCl>}dXezB=I?X?6>79H=5^:>M>^)?Zd>|N?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhGz?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/C JFDCEXhzr> Jclock pessimismXh7 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh"۩?/ JXh4 JslackXh6>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuCl>}dXezB=I?X?6>79H=5^:>M>^)?Zd>|N?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhGz?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]/C JFDCEXhzr> Jclock pessimismXh7 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh"۩?/ JXh4 JslackXh6>RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuCl>}dXezB=I?X?6>79H=5^:>M>^)?Zd>|N?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh5^:> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhGz?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/C JFDCEXhzr> Jclock pessimismXh7 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh"۩?/ JXh4 JslackXh6>g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsun@}A/A&L=$.@&@A=А=2@6E>$>+V@&1?O?$!??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf!r> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhR@X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhgf/ JXh4 JslackXh2@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsun@}A/A&L=$.@&@A=А=2@6E>$>+V@&1?O?$!??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf!r> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhR@X1Y8 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhgf/ JXh4 JslackXh2@ ?g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsud@}A/A?5&4=$.@?5&@A=А=0@6E>/>rP@&1?O?$!??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh$@X1Y8 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh/ JXh4 JslackXh0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuC[@}A/A&L=$.@&@A=А=@6E>/>G@&1?O?$!??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhR@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh9/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuZ@}AZ/A&܊=$.@&@A=А=g&@6E>/>F@&1?O?$!? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ/A; J arrival timeXhMb/ JXh4 JslackXhg&@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuZ@}AZ/A&܊=$.@&@A=А=g&@6E>/>F@&1?O?$!? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ/A; J arrival timeXhMb/ JXh4 JslackXhg&@ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuZ@}AZ/A&܊=$.@&@A=А=g&@6E>/>F@&1?O?$!? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhZ/A; J arrival timeXhMb/ JXh4 JslackXhg&@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/>Y9<@&1?O?$!?W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXh<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/>Y9<@&1?O?$!?W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXh<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR"$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X18Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/>Y9<@&1?O?$!?W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C JFDCEXhzr> Jclock pessimismXh6E>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh / JXh4 JslackXh<@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!)y@1y @9Ay@Iy @eTŅ@hq}k>d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuGa>}> Ԩ-=C?Ԩ?k>t9H=/>>+?->Q?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh/> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXht c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh> ; J arrival timeXhl?/ JXh4 JslackXhk>373SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}pE=^?E?-$>;D=9H>>9(?->DL?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>c 1-SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y8 (CLOCK_ROOT)a /+SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXh;z -)SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXh?/ JXh4 JslackXh-$>4473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}pE=^?E?-$>;D=9H>>9(?->DL?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>c 1-SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y8 (CLOCK_ROOT)a /+SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh;{ -)SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXh?/ JXh4 JslackXh-$>4773SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}=^??b*>D=9H>>9(?-> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhb*>4873SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}=^??b*>D=9H>>9(?-> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhb*>4773SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}=^??b*>D=9H>>9(?-> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhb*>4873SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}=^??b*>D=9H>>9(?-> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhb*>4773SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}=^??b*>D=9H>>9(?-> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhb*>4873SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu&y>}=^??b*>D=9H>>9(?-> K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhb*>4773SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuxi>}¥j+=^?¥?b9>f5D=Q8>>9(?->K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhQ8>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXhf5{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhy?/ JXh4 JslackXhb9>43g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A/AT%=,@T%@A=А=TŅ@SG>>s@*??5?5^?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhp/ JXh4 JslackXhTŅ@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A˒/A%=,@%@A=А=@SG>> s@*??5?5^??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh- @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh˒/A; J arrival timeXh/ JXh4 JslackXh@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A˒/A%=,@%@A=А=@SG>> s@*??5?5^??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh- @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh˒/A; J arrival timeXh/ JXh4 JslackXh@ Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A˒/A%=,@%@A=А=@SG>> s@*??5?5^??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh- @X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh˒/A; J arrival timeXh/ JXh4 JslackXh@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu"ہ@}A/A%Ĭ=,@%@A=А= @SG>>xq@*??5?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhT @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhZ/ JXh4 JslackXh @ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu"ہ@}A/A%Ĭ=,@%@A=А= @SG>>xq@*??5?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhT @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhZ/ JXh4 JslackXh @ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu"ہ@}A/A%Ĭ=,@%@A=А= @SG>>xq@*??5?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhT @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhZ/ JXh4 JslackXh @ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu"ہ@}A/A%Ĭ=,@%@A=А= @SG>>xq@*??5?5^??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhT @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhZ/ JXh4 JslackXh @ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu7@}A/A%J=,@%@A=А=%@SG>>p@*??5?5^?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXh1/ JXh4 JslackXh%@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1*X1Y824RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu9@}Al/A&p=,@&@A=А=}@SG>>+o@*??5?5^?Nb?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/E@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C JFDCEXhzr> Jclock pessimismXhSG>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhl/A; J arrival timeXh33/ JXh4 JslackXh}@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!)y@1y @9Ay@Iy @eڴ@hq}>d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuX9>}~{<v??>29H=+>S>?>/$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh+> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhQX?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh2 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXh-?/ JXh4 JslackXh>Pd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuSc>}|-WV={n?-?D(>#D=-2>S>p>>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh-2> }yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNbP?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhp}?X1Y8 (CLOCK_ROOT) {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh# yug_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXht?/ JXh4 JslackXhD(>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuSc>}|-WV={n?-?D(>#D=-2>S>p>>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh-2> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNbP?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh# g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXht?/ JXh4 JslackXhD(>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuSc>}|-WV={n?-?D(>#D=-2>S>p>>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh-2> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNbP?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh# g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXht?/ JXh4 JslackXhD(>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuSc>}|-WV={n?-?D(>#D=-2>S>p>>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh-2> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNbP?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh# g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXht?/ JXh4 JslackXhD(>R73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK >}dFč=ap?F?2*>UD=R>S>8?>J "?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33S?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXhU{ .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh?/ JXh4 JslackXh2*>473SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK >}dFč=ap?F?2*>UD=R>S>8?>J "?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33S?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXhU| .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh?/ JXh4 JslackXh2*>473SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK >}dFč=ap?F?2*>UD=R>S>8?>J "?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33S?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXhU{ .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh?/ JXh4 JslackXh2*>473SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK >}dFč=ap?F?2*>UD=R>S>8?>J "?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33S?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr> Jclock pessimismXhU| .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh?/ JXh4 JslackXh2*>473SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK >}dFč=ap?F?2*>UD=R>S>8?>J "?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33S?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXhU{ .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhd; J arrival timeXh?/ JXh4 JslackXh2*>42g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Clhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsud@}AL@*A&%e;'@@A=А=ڴ@EB>)\>@2??"??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xhsh?X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhEB>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhL@*A; J arrival timeXh䥟/ JXh4 JslackXhڴ@ 2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Clhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsud@}AL@*A&%e;'@@A=А=ڴ@EB>)\>@2??"??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xhsh?X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhEB>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhL@*A; J arrival timeXh䥟/ JXh4 JslackXhڴ@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu @}A*AAB-e;'@A@A=А=v߶@ZB>)\>\ @2??"??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> UQg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/AS[0] Jnet (fo=32, routed)Xh\ @ gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK Jnet (fo=674, routed)XhNb?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhZB>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXhB`/ JXh4 JslackXhv߶@ Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsua@}A08*Aأ-'e;'@أ@A=А=_@2KB>)\>@2??"?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C JFDCEXhzr> Jclock pessimismXh2KB>@ Jclock uncertaintyXh plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh08*A; J arrival timeXhc/ JXh4 JslackXh_@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsua@}A08*Aأ-'e;'@أ@A=А=_@2KB>)\>@2??"?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C JFDCEXhzr> Jclock pessimismXh2KB>@ Jclock uncertaintyXh plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh08*A; J arrival timeXhc/ JXh4 JslackXh_@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsua@}A08*Aأ-'e;'@أ@A=А=_@2KB>)\>@2??"?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/C JFDCEXhzr> Jclock pessimismXh2KB>@ Jclock uncertaintyXh plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh08*A; J arrival timeXhc/ JXh4 JslackXh_@ Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsua@}A08*Aأ-'e;'@أ@A=А=_@2KB>)\>@2??"?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/C JFDCEXhzr> Jclock pessimismXh2KB>@ Jclock uncertaintyXh plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh08*A; J arrival timeXhc/ JXh4 JslackXh_@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsua@}A08*Aأ-'e;'@أ@A=А=_@2KB>)\>@2??"?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh@ tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/C JFDCEXhzr> Jclock pessimismXh2KB>@ Jclock uncertaintyXh plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh08*A; J arrival timeXhc/ JXh4 JslackXh_@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cd`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv/PRE""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuA@}A0*A4)e;'@@A=А=@wPB>)\>K@2??"?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)XhK@ d`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv/PRE JFDPEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXhwPB>@ Jclock uncertaintyXh `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_invRecov_HFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh0*A; J arrival timeXhw/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C_[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg/CLR""RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X19Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu @}AYD*A#$e;'@@A=А=@VCB>)\>!@2??"? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 Jnet (fo=32, routed)Xh!@ _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1 @X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK Jnet (fo=674, routed)Xh8?X1Y8 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXhVCB>@ Jclock uncertaintyXh [Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_regRecov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhYD*A; J arrival timeXhp/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!)y@1y @9Ay@Iy @e@hq}d1>d rise - rise rise - rise  73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsui;_>} 􅿍,!=A??d1>^1D=|.>>&?Z>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|.>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXh^1{ .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh 􅿐; J arrival timeXh(?/ JXh4 JslackXhd1>473SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsui;_>} 􅿍,!=A??d1>^1D=|.>>&?Z>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|.>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXh^1| .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh 􅿐; J arrival timeXh(?/ JXh4 JslackXhd1>473SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsui;_>} 􅿍,!=A??d1>^1D=|.>>&?Z>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|.>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXh^1{ .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh 􅿐; J arrival timeXh(?/ JXh4 JslackXhd1>473SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsui;_>} 􅿍,!=A??d1>^1D=|.>>&?Z>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|.>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXh^1| .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh 􅿐; J arrival timeXh(?/ JXh4 JslackXhd1>4d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu]>}Nb 5=X9?Nb??R>4D=S>>?Z>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhS> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh4 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh/ݤ?/ JXh4 JslackXh?R>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuc>}iލ|=X9?|?D=֣p>>?Z>T%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh֣p> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhiލ; J arrival timeXhr?/ JXh4 JslackXhRd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuc>}iލ|=X9?|?D=֣p>>?Z>T%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh֣p> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhiލ; J arrival timeXhr?/ JXh4 JslackXhR-d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuŸ>}9d;=X9?d;?}(j>D=I >>?Z>B`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhI > tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhƋ?X1Y8 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh plg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh9; J arrival timeXhI?/ JXh4 JslackXh}(j>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu->}Ud;=X9?d;?z>K4D=l{>>?Z>B`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhƋ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhK4 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhU; J arrival timeXh#۩?/ JXh4 JslackXhz>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuZd>}A|=X9?A?ŵ>D=Т>>?Z>l'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhТ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xȟ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXho?/ JXh4 JslackXhŵ>Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuT@}A",A(\9@(\@A=А=@eQ>K>>@M??t8?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfA`> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhB`E? TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXheQ>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh",A; J arrival timeXhK/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuT@}A",A(\9@(\@A=А=@eQ>K>>@M??t8?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfA`> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhB`E? YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXheQ>@ Jclock uncertaintyXh UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh",A; J arrival timeXhK/ JXh4 JslackXh@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuQG@}A:,A&^9@&@A=А=͌@rQ>>O5@M??t8?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXhrQ>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh:,A; J arrival timeXh/ JXh4 JslackXh͌@ 2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuQG@}A:,A&^9@&@A=А=͌@rQ>>O5@M??t8?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C JFDCEXhzr> Jclock pessimismXhrQ>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh:,A; J arrival timeXh/ JXh4 JslackXh͌@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuQG@}A:,A&^9@&@A=А=͌@rQ>>O5@M??t8?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhrQ>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh:,A; J arrival timeXh/ JXh4 JslackXh͌@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuQG@}A:,A&^9@&@A=А=͌@rQ>>O5@M??t8?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C JFDCEXhzr> Jclock pessimismXhrQ>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh:,A; J arrival timeXh/ JXh4 JslackXh͌@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu9A@}Ac,AMb9@Mb@A=А=-@;Q>>K/@M??t8?Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhQ@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh;Q>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhc,A; J arrival timeXh/ JXh4 JslackXh-@ 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu9A@}Ac,AMb9@Mb@A=А=-@;Q>>K/@M??t8?Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhQ@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh;Q>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhc,A; J arrival timeXh/ JXh4 JslackXh-@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsui=@}A,Ax9@x@A=А=M@YQ>>S+@M??t8?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xhrh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C JFDCEXhzr> Jclock pessimismXhYQ>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhM@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT*X1Y82#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsui=@}A,Ax9@x@A=А=M@YQ>>S+@M??t8?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhv@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xhrh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C JFDCEXhzr> Jclock pessimismXhYQ>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhM@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!)y@1y @9Ay@Iy @ee@hq}ϰ >d rise - rise rise - rise  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuGa>}ij M=? ?ϰ >9H=/>>n2?->V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh/> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhP?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhij; J arrival timeXh?/ JXh4 JslackXhϰ >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuA`>}9(E͞=??0 > 9H=|.>>n2?->U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh|.> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh9(; J arrival timeXh?/ JXh4 JslackXh0 >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuA`>}9(E͞=??0 > 9H=|.>>n2?->U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh|.> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh9(; J arrival timeXh?/ JXh4 JslackXh0 >RRNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuQ8>}/=/??M>AD=+>>/?->33S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF2_SLICEM_C_Q JFDPEXhzfD= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh+> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh |?X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh$?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhA c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_regRemov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh/; J arrival timeXhX9?/ JXh4 JslackXhM>d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuD>}Cƫ !=?ƫ?l9>O5A9H=n>>n2?->OW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhn> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhO5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC; J arrival timeXh+?/ JXh4 JslackXhl9>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuD>}Cƫ !=?ƫ?l9>O5A9H=n>>n2?->OW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhn> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhO5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC; J arrival timeXh+?/ JXh4 JslackXhl9>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuD>}Cƫ !=?ƫ?l9>O5A9H=n>>n2?->OW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhn> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXhO5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC; J arrival timeXh+?/ JXh4 JslackXhl9>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuD>}Cƫ !=?ƫ?l9>O5A9H=n>>n2?->OW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhn> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhO5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC; J arrival timeXh+?/ JXh4 JslackXhl9>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuD>}Cƫ !=?ƫ?l9>O5A9H=n>>n2?->OW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhn> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhO5A g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC; J arrival timeXh+?/ JXh4 JslackXhl9>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu k>}L7=?L7?h#>9H=X9>>n2?->nR?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX9> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh•?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh1?/ JXh4 JslackXhh#>RSg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu{@}A /Aˡ%=,@ˡ%@A=А=e@jD>~j>@~*?E??z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhh @X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh /A; J arrival timeXh / JXh4 JslackXhe@ Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu{@}A /Aˡ%=,@ˡ%@A=А=e@jD>~j>@~*?E??z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhh @X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh /A; J arrival timeXh / JXh4 JslackXhe@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu{@}A /Aˡ%=,@ˡ%@A=А=e@jD>~j>@~*?E??z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhh @X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh /A; J arrival timeXh / JXh4 JslackXhe@ Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu•@}Ay/A%Ӷ=,@%@A=А=If@jD>~j>n@~*?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhp @X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhy/A; J arrival timeXh/ JXh4 JslackXhIf@ Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu•@}Ay/A%Ӷ=,@%@A=А=If@jD>~j>n@~*?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhp @X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhy/A; J arrival timeXh/ JXh4 JslackXhIf@ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsur@}A-]/AW%%}=,@W%@A=А=vp@jD>~j>@~*?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-]/A; J arrival timeXh~/ JXh4 JslackXhvp@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsur@}A-]/AW%%}=,@W%@A=А=vp@jD>~j>@~*?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-]/A; J arrival timeXh~/ JXh4 JslackXhvp@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsur@}A-]/AW%%}=,@W%@A=А=vp@jD>~j>@~*?E???z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-]/A; J arrival timeXh~/ JXh4 JslackXhvp@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuX9@}AT/A$yd=,@$@A=А=p@jD>~j>a@~*?E?? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh/ @X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhT/A; J arrival timeXhE/ JXh4 JslackXhp@ _g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1*X1Y924RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X18Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuף@}Ah~j>O@~*?E??l?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhN@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xha@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhz @X1Y9 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhjD>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhhd rise - rise rise - rise  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu>}cJҝP=A?ҝ?بG>4c9H=u>>&?Z>]"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh6^?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh4c g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhcJ; J arrival timeXh~??/ JXh4 JslackXhبG>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu>}cJҝP=A?ҝ?بG>4c9H=u>>&?Z>]"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh6^?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh4c g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhcJ; J arrival timeXh~??/ JXh4 JslackXhبG>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu>}cJҝP=A?ҝ?بG>4c9H=u>>&?Z>]"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh6^?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh4c g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhcJ; J arrival timeXh~??/ JXh4 JslackXhبG>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu~>}ІD6f==A?D?J>E29H=L>>&?Z> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhE2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhІ; J arrival timeXh ?/ JXh4 JslackXhJ>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu~>}ІD6f==A?D?J>E29H=L>>&?Z> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhE2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhІ; J arrival timeXh ?/ JXh4 JslackXhJ>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu~>}ІD6f==A?D?J>E29H=L>>&?Z> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhE2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhІ; J arrival timeXh ?/ JXh4 JslackXhJ>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu> >}W?5m=A??5? J>]9H=l{>>&?Z>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXh?/ JXh4 JslackXh J>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu> >}W?5m=A??5? J>]9H=l{>>&?Z>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhl{> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhW; J arrival timeXh?/ JXh4 JslackXh J>R73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuŸ>}|=M?|?W>D=I >>?Z>T%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhI >d 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhyf?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhW>473SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuŸ>}|=M?|?W>D=I >>?Z>T%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhI >d 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhyf?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhW>4eWSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuu@}AT-AB`-@@A=А=^@T>o>Nb?OM?.?b8?rh?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > QMg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s Jnet (fo=1, routed)Xh\? WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__44/I1 JXhzr VRg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__44/OProp_A6LUT_SLICEM_I1_O JLUT2Xhzfx> MIg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s0 Jnet (fo=1, routed)Xh? TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE JFDPEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh-@X1Y9 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhp?X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXhT>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_regRecov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXhT-A; J arrival timeXh/ JXh4 JslackXh^@~73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu -@}A,Ak2+/@@A=А=4b@uP>V>\?OM?G?b8?ʡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\?d 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)i 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXhuP>@ Jclock uncertaintyXh{ .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh4b@473SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu -@}A,Ak2+/@@A=А=4b@uP>V>\?OM?G?b8?ʡ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\?d 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)i 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXhuP>@ Jclock uncertaintyXh| .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh4b@4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu{?}A,Ay <w/@y@A=А=k@ڎP>5^>Q?OM?n?b8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhv~? fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh-? TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh,?X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhڎP>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhk@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu{?}A,Ay <w/@y@A=А=k@ڎP>5^>Q?OM?n?b8??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhv~? fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh-? YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh,?X1Y9 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhڎP>@ Jclock uncertaintyXh UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhk@  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuZ9?}A+Ai-@@A=А= @=P>V>n?OM?|?b8?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhn? hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh6^@X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhp?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]/C JFDCEXhzr> Jclock pessimismXh=P>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ד/ JXh4 JslackXh @ RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuZ9?}A+Ai-@@A=А= @=P>V>n?OM?|?b8?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhn? hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh6^@X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhp?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/C JFDCEXhzr> Jclock pessimismXh=P>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ד/ JXh4 JslackXh @ RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuZ9?}A+Ai-@@A=А= @=P>V>n?OM?|?b8?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhn? hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh6^@X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhp?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]/C JFDCEXhzr> Jclock pessimismXh=P>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ד/ JXh4 JslackXh @RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsum?}A+AQi-@Q@A=А=sb@P>V>G?OM?|?b8?G?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh6^@X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhO?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhP/ JXh4 JslackXhsb@RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]/CLR"#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP*X1Y92#RCLK_CLE_M_L_X31Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsum?}A+AQi-@Q@A=А=sb@P>V>G?OM?|?b8?G?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh6^@X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhO?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]/C JFDCEXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhP/ JXh4 JslackXhsb@B **async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5!)y@1y @9Ay@Iy @es^@hq}?>d rise - rise rise - rise  Gd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu k>}1>=b???>i5D9H=X9>y?  ??(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhX9> tpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhNb?X3Y1 (CLOCK_ROOT) rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhi5D plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXh?/ JXh4 JslackXh?>Rld`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu k>}1>=b???>i5D9H=X9>y?  ??(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhX9> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhNb?X3Y1 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhi5D yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1; J arrival timeXh?/ JXh4 JslackXh?>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu9>}]B`Er=b?B`?A>E9H=e;_>y?  ??;(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhe;_> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhE g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh]; J arrival timeXhp=?/ JXh4 JslackXhA>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu9>}]B`Er=b?B`?A>E9H=e;_>y?  ??;(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhe;_> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXhE g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh]; J arrival timeXhp=?/ JXh4 JslackXhA>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu9>}]B`Er=b?B`?A>E9H=e;_>y?  ??;(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhe;_> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhE g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh]; J arrival timeXhp=?/ JXh4 JslackXhA>R%62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu>}SB=?S?m`K>")BD=y?0??$?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhc 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXh")Bz -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhm`K>4&62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu>}SB=?S?m`K>")BD=y?0??$?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhc 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr> Jclock pessimismXh")B{ -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhm`K>4!62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsur>}FN=?F?]M>kBD=T>y?0??B`%?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhT>b 0,SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)` .*SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhkBy ,(SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhµ?/ JXh4 JslackXh]M>4"62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsur>}FN=?F?]M>kBD=T>y?0??B`%?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhT>b 0,SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)` .*SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhkBz ,(SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhµ?/ JXh4 JslackXh]M>4%62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsur>}FN=?F?]M>kBD=T>y?0??B`%?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhT>c 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXhkBz -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhµ?/ JXh4 JslackXh]M>4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuO}@}Ac4AX94?A`u@X94@A=А=s^@:>>d@~?^ @D??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXh:>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc4A; J arrival timeXhX/ JXh4 JslackXhs^@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuO}@}Ac4AX94?A`u@X94@A=А=s^@:>>d@~?^ @D??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXh:>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc4A; J arrival timeXhX/ JXh4 JslackXhs^@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuO}@}Ac4AX94?A`u@X94@A=А=s^@:>>d@~?^ @D??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C JFDCEXhzr> Jclock pessimismXh:>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc4A; J arrival timeXhX/ JXh4 JslackXhs^@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu |@}A[4A4F)@A`u@4@A=А=a_@>>(d@~?^ @D?:?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh[4A; J arrival timeXh%/ JXh4 JslackXha_@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuw@}Ac4AX94?A`u@X94@A=А=|_d@:>>K_@~?^ @D??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C JFDCEXhzr> Jclock pessimismXh:>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc4A; J arrival timeXh/ JXh4 JslackXh|_d@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuw@}Ac4AX94?A`u@X94@A=А=|_d@:>>K_@~?^ @D??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXh:>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc4A; J arrival timeXh/ JXh4 JslackXh|_d@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuw@}Ac4AX94?A`u@X94@A=А=|_d@:>>K_@~?^ @D??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXh:>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc4A; J arrival timeXh/ JXh4 JslackXh|_d@ 6g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu+w@}A[4A4F)@A`u@4@A=А=d@>>^@~?^ @D?:?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh[4A; J arrival timeXhE/ JXh4 JslackXhd@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu+w@}A[4A4F)@A`u@4@A=А=d@>>^@~?^ @D?:?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh[4A; J arrival timeXhE/ JXh4 JslackXhd@ *g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1*X3Y124RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X50Y149/CLK_VDISTR_BOT1:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu+w@}A[4A4F)@A`u@4@A=А=d@>>^@~?^ @D?:?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh+7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh[4A; J arrival timeXhE/ JXh4 JslackXhd@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6!)y@1y @9Ay@Iy @e$@hq}>d rise - rise rise - rise  62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuT>}#۩=?#۩?>D= #>(>h-? >thQ?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh #>b 0,SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXhy ,(SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhP?/ JXh4 JslackXh>4 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuT>}#۩=?#۩?>D= #>(>h-? >thQ?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh #>b 0,SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXhz ,(SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhP?/ JXh4 JslackXh>4RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuˡ>}F Ԩ=5^?Ԩ?->~\9H=Y>(>r(? >)\O?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhY> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh+v?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhF?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXh~\ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhF ; J arrival timeXhƫ?/ JXh4 JslackXh->62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C-)SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu>}~\=?~?{6>D=(\>(>h-? >"R?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh(\>_ -)SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X4Y2 (CLOCK_ROOT)] +'SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhv )%SFP_GEN[4].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh{6>4Dd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu`>}`+2=C?+?oJ>n9H=Ga>(>p=*? >2L?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhGa> tpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQx?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT) rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhn plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh`; J arrival timeXh-?/ JXh4 JslackXhoJ>Rid`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu`>}`+2=C?+?oJ>n9H=Ga>(>p=*? >2L?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhGa> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQx?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhn yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh`; J arrival timeXh-?/ JXh4 JslackXhoJ>R#62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu+>} Χ4o=?Χ?jM> =D=/]>(>h-? >OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/]>c 1-SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXh =z -)SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhR?/ JXh4 JslackXhjM>4$62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu+>} Χ4o=?Χ?jM> =D=/]>(>h-? >OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/]>c 1-SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXh ={ -)SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhR?/ JXh4 JslackXhjM>4RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu>}4P+I=5^?+?U>139H="[>(>r(? >2L?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh+v?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]/C JFDCEXhzr> Jclock pessimismXh13 b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh4P; J arrival timeXh1?/ JXh4 JslackXhU>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu->}j㔿=5^??X>t9H=Gz>(>r(? >XM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhGz> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh+v?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh]?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXht c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhj㔿; J arrival timeXh?/ JXh4 JslackXhX>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuB`@}A 1AJ *x9@J *@A=А=$@e>>p=j@7?q=?+'?h?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xht@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXh$@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu~@}A-1Aq=*]x9@q=*@A=А=?9@e>>Ef@7?q=?+'??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-1A; J arrival timeXh / JXh4 JslackXh?9@ )g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu~@}A-1Aq=*]x9@q=*@A=А=?9@e>>Ef@7?q=?+'??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-1A; J arrival timeXh / JXh4 JslackXh?9@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu~@}A-1Aq=*]x9@q=*@A=А=?9@e>>Ef@7?q=?+'??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh-1A; J arrival timeXh / JXh4 JslackXh?9@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuV~@}A$1A*}x9@*@A=А=4b@e>>e@7?q=?+'?-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh$1A; J arrival timeXhl/ JXh4 JslackXh4b@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu$~@}A$1A*}x9@*@A=А=z@e>>ʡe@7?q=?+'?-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh$1A; J arrival timeXh/ JXh4 JslackXhz@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu$~@}A$1A*}x9@*@A=А=z@e>>ʡe@7?q=?+'?-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh$1A; J arrival timeXh/ JXh4 JslackXhz@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu$~@}A$1A*}x9@*@A=А=z@e>>ʡe@7?q=?+'?-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh$1A; J arrival timeXh/ JXh4 JslackXhz@ 4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu,}@}A1A)Fx9@)@A=А=@e>>/e@7?q=?+'?p?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh@ (g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR"3RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1*X4Y223RCLK_RCLK_BRAM_L_AUXCLMP_FT_X70Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu,}@}A1A)Fx9@)@A=А=@e>>/e@7?q=?+'?p?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C JFDCEXhzr> Jclock pessimismXhe>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7!)y@1y @9Ay@Iy @e@hq}3>d rise - rise rise - rise  62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C-)SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuA`>}.P=&?.?3> <D=/> ף>-2?X>zT?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/>_ -)SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT)] +'SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh <v )%SFP_GEN[5].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh/?/ JXh4 JslackXh3>4%62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu>}B^=&??N;>D=@5^> ף>-2?X>EV?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>c 1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXhz -)SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXho?/ JXh4 JslackXhN;>4&62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu>}B^=&??N;>D=@5^> ף>-2?X>EV?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>c 1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXh{ -)SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXho?/ JXh4 JslackXhN;>4!62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu>}.=&?.?e>YD=> ף>-2?X>zT?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>b 0,SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhYy ,(SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhe>4"62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu>}.=&?.?e>YD=> ף>-2?X>zT?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>b 0,SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhYz ,(SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhe>4%62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu>}.=&?.?e>YD=> ף>-2?X>zT?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>c 1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]/C JFDCEXhzr> Jclock pessimismXhYz -)SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXhe>4d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu >}˙̬ZԠ=?̬?R\>A'9H=> > ף>z.?X>!R?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXhA' g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh˙; J arrival timeXh"?/ JXh4 JslackXhR\>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu7^>}@e;&=?e;?/Ņ>9H=G> ף>z.?X>PW?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhG> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh@; J arrival timeXh-?/ JXh4 JslackXh/Ņ>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu%۹>}=??J>9H=Ġ> ף>z.?X>? W?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhĠ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh#ۙ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhh?/ JXh4 JslackXhJ>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu%۹>}=??J>9H=Ġ> ף>z.?X>? W?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhĠ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh#ۙ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhh?/ JXh4 JslackXhJ>R*g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu-Z@}A1Ak,~?=@k,@A=А=@*og>(>F@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhG/ JXh4 JslackXh@ +g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu-Z@}A1Ak,~?=@k,@A=А=@*og>(>F@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhG/ JXh4 JslackXh@ *g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu-Z@}A1Ak,~?=@k,@A=А=@*og>(>F@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhG/ JXh4 JslackXh@ *g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu-Z@}A1Ak,~?=@k,@A=А=@*og>(>F@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhG/ JXh4 JslackXh@ *g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu0L@}A91AI,?~?=@I,@A=А=^@*og>(>X9@Yd;??q=*??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh91A; J arrival timeXhW/ JXh4 JslackXh^@ +g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu0L@}A91AI,?~?=@I,@A=А=^@*og>(>X9@Yd;??q=*??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh91A; J arrival timeXhW/ JXh4 JslackXh^@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuNbH@}A1Ak,~?=@k,@A=А=Ԡ@*og>(>/4@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhԠ@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuNbH@}A1Ak,~?=@k,@A=А=Ԡ@*og>(>/4@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhԠ@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuNbH@}A1Ak,~?=@k,@A=А=Ԡ@*og>(>/4@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhԠ@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1*X4Y224RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X66Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuNbH@}A1Ak,~?=@k,@A=А=Ԡ@*og>(>/4@Yd;??q=*?sh?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh'1@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)XhC@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C JFDCEXhzr> Jclock pessimismXh*og>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhԠ@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8!)y@1y @9Ay@Iy @e˙@hq}z->d rise - rise rise - rise  #d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu"/]>}x(=̌?x?z->M-;D=1,>M>r=*?Q>CL?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh1,> tpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhZ?X4Y2 (CLOCK_ROOT) rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhM-; plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXhz->RRNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuo>}斖#۩=-?#۩?>>@9H=S>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh斖; J arrival timeXhv?/ JXh4 JslackXh>>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuo>}斖#۩=-?#۩?>>@9H=S>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh斖; J arrival timeXhv?/ JXh4 JslackXh>>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuo>}斖#۩=-?#۩?>>@9H=S>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh斖; J arrival timeXhv?/ JXh4 JslackXh>>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuo>}斖#۩=-?#۩?>>@9H=S>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh斖; J arrival timeXhv?/ JXh4 JslackXh>>62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C-)SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuˡ>}"嗿"j=?"?}D>6 D=Z>M>.?Q>_ -)SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)] +'SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh6 v )%SFP_GEN[6].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh"嗿; J arrival timeXh?/ JXh4 JslackXh}D>4RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu>}#۩=-?#۩?9H>CC9H=/]>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh/]> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhCC c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_regRemov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh9H>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu>}#۩=-?#۩?9H>CC9H=/]>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh/]> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr> Jclock pessimismXhCC c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh9H>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu>}#۩=-?#۩?9H>CC9H=/]>M>1,?Q>OM?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh/]> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzr> Jclock pessimismXhCC c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh9H>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu>}l񕿍L7ls=-?L7?UK>M9H="[>M>1,?Q>2L?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]/C JFDCEXhzr> Jclock pessimismXhM b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhl񕿐; J arrival timeXh*\?/ JXh4 JslackXhUK>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsul\@}Am1Aj,}J=,6@j,@A=А=˙@pe>(>L7I@5^:?p?)?a?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhm1A; J arrival timeXh̡/ JXh4 JslackXh˙@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu)\W@}A1A,Co=,6@,@A=А=Ó@pe>(> C@5^:?p?)?G?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh"@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhÓ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu)\W@}A1A,Co=,6@,@A=А=Ó@pe>(> C@5^:?p?)?G?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh"@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhÓ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu)\W@}A1A,Co=,6@,@A=А=Ó@pe>(> C@5^:?p?)?G?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh"@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhÓ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuq=R@}A1AD, c=,6@D,@A=А=@pe>(>R>@5^:?p?)?&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhNb/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuq=R@}A1AD, c=,6@D,@A=А=@pe>(>R>@5^:?p?)?&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xho@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhNb/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuQ@}A1Az,V=,6@z,@A=А=L@pe>(>E>@5^:?p?)?%?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh(/ JXh4 JslackXhL@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuQ@}A1Az,V=,6@z,@A=А=L@pe>(>E>@5^:?p?)?%?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh(/ JXh4 JslackXhL@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuQ@}A1Az,V=,6@z,@A=А=L@pe>(>E>@5^:?p?)?%?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh(/ JXh4 JslackXhL@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X67Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuRN@}Aٝ1A1,nv=,6@1,@A=А=@pe>㥛>C;@5^:?p?)? ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__5/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__5/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf(> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhm? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh\@X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhpe>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhٝ1A; J arrival timeXh/ JXh4 JslackXh@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9!)y@1y @9Ay@Iy @eϲ@hq}ga>d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuA`e>}T-==m?-?ga>< 9H=433>c>?>"?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]/C JFDCEXhzr> Jclock pessimismXh<  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXhga>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsurh>}1끿nޥ=m?n?d>9 9H=E6>c>?>S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhE6> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXh9  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1끿; J arrival timeXh?/ JXh4 JslackXhd>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsurh>}1끿nޥ=m?n?d>9 9H=E6>c>?>S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhE6> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhO?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]/C JFDCEXhzr> Jclock pessimismXh9  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1끿; J arrival timeXh?/ JXh4 JslackXhd>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuVE@}AW+AZ"i5@Z@A=А=ϲ@0Y>X>T-@h-?Q?-?y?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh0Y>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhW+A; J arrival timeXhO/ JXh4 JslackXhϲ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuD@}A;y+AX9%i5@X9@A=А=ۙ@5Y>X>p-@h-?Q?-??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C JFDCEXhzr> Jclock pessimismXh5Y>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;y+A; J arrival timeXh/ JXh4 JslackXhۙ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuD@}A;y+AX9%i5@X9@A=А=ۙ@5Y>X>p-@h-?Q?-??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh5Y>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;y+A; J arrival timeXh/ JXh4 JslackXhۙ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuD@}A;y+AX9%i5@X9@A=А=ۙ@5Y>X>p-@h-?Q?-??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh5Y>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;y+A; J arrival timeXh/ JXh4 JslackXhۙ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu:@}A+A~?X i5@~?@A=А=2@ Y>X>#@h-?Q?-?;?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhP?X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C JFDCEXhzr> Jclock pessimismXh Y>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhA/ JXh4 JslackXh2@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuM:@}A+A i5@@A=А=ct@HY>X>"#@h-?Q?-?r?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK?X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C JFDCEXhzr> Jclock pessimismXhHY>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhct@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu{6@}A+A/i5@/@A=А=,@Y>X>y@h-?Q?-?u?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xhl?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhҵ/ JXh4 JslackXh,@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu{6@}A+A/i5@/@A=А=,@Y>X>y@h-?Q?-?u?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xhl?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhҵ/ JXh4 JslackXh,@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu{6@}A+A/i5@/@A=А=,@Y>X>y@h-?Q?-?u?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xhl?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhҵ/ JXh4 JslackXh,@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR"#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X79Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu{6@}A+A/i5@/@A=А=,@Y>X>y@h-?Q?-?u?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhC? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh+@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xhl?X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhҵ/ JXh4 JslackXh,@  **async_default**rxoutclk_out[0]rxoutclk_out[0]!)6 @16@9A6 @I6@e@hq}mh>d rise - rise rise - risei_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsuGa>}@5. =p= ?.?mh>*\9H=/>q=#۹>=>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xh/> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh@5; J arrival timeXh[B?/ JXh4 JslackXhmh>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsuGa>}@5. =p= ?.?mh>*\9H=/>q=#۹>=>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xh/> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh@5; J arrival timeXh[B?/ JXh4 JslackXhmh>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsua;_>}p|.1\=p= ?|.?n>*\9H=V->q=#۹>=G>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)XhV-> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh ?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhI B?/ JXh4 JslackXhn>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsua;_>}p|.1\=p= ?|.?n>*\9H=V->q=#۹>=G>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)XhV-> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh ?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhI B?/ JXh4 JslackXhn>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsua;_>}p|.1\=p= ?|.?n>*\9H=V->q=#۹>=G>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)XhV-> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh ?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhI B?/ JXh4 JslackXhn>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsua;_>}p|.1\=p= ?|.?n>*\9H=V->q=#۹>=G>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)XhV-> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh ?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhI B?/ JXh4 JslackXhn>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsua;_>}p|.1\=p= ?|.?n>*\9H=V->q=#۹>=G>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)XhV-> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh ?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhI B?/ JXh4 JslackXhn>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000nsua;_>}p|.1\=p= ?|.?n>*\9H=V->q=#۹>=G>h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})e(removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Fast**async_default**rxoutclk_out[0]rxoutclk_out[0](DCD - SCD - CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)XhV-> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xht< i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xhb>X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh)\= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh ?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/C JFDCEXhzr> Jclock pessimismXh*\ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhI B?/ JXh4 JslackXhn>i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu;?}@@Zd?Zd?@=А=@=V>u>x=Gz?=aX?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xhu> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh_p?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhNb/ JXh4 JslackXh@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu;?}@@Zd?Zd?@=А=@=V>u>x=Gz?=aX?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xhu> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh_p?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhNb/ JXh4 JslackXh@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu;?}@@Zd?Zd?@=А=@=V>u>x=Gz?=aX?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xhu> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh_p?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhNb/ JXh4 JslackXh@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu;?}@@Zd?Zd?@=А=@=V>u>x=Gz?=aX?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xhu> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh_p?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhNb/ JXh4 JslackXh@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu;?}@@Zd?Zd?@=А=@=V>u>x=Gz?=aX?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xhu> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh_p?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhNb/ JXh4 JslackXh@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsu;?}@@Zd?Zd?@=А=@=V>u>x=Gz?=aX?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xhu> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh_p?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhNb/ JXh4 JslackXh@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsuMb?}@@1N?1?@=А=*ֲ@=V>>x=Gz?=XY?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh -r?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh*ֲ@i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Ci_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR"/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT*X5Y02/GTH_R_X94Y0/CLK_BUFG_GT_WITH_OPTINVS_12_CLK_OUT:X5Y0BJZj;rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000nsuMb?}@@1N?1?@=А=*ֲ@=V>>x=Gz?=XY?h(rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})f(recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns})Slow**async_default**rxoutclk_out[0]rxoutclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out Jnet (fo=8, routed)Xh> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR JFDCEXhzf S J!(clock rxoutclk_out[0] rise edge)Xhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)Xh5^= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out Jnet (fo=617, routed)Xh1?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C JFDCEXhzr S J!(clock rxoutclk_out[0] rise edge)Xhzr@ i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in Jnet (fo=2, routed)XhT= i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 Jnet (fo=617, routed)Xh -r?X5Y0 (CLOCK_ROOT) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh*ֲ@ **async_default** tx_wordclk tx_wordclk!)M@1M @9AM@IM @e2>hq}V,=Vd rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu?O>}~oÿֿ̯=η??,=9H=->/>/}?~j>y?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh-> }yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhη?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/C JFDCEXhzr> Jclock pessimismXh yug_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~oÿ; J arrival timeXh?/ JXh4 JslackXh,= RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuK>}q¿տ=η??=f9H=>/>/}?~j>gf?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh> }yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhη?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]/C JFDCEXhzr> Jclock pessimismXhf yug_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhq¿; J arrival timeXhG?/ JXh4 JslackXh= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Ckgg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuD>}Z˿ =G?? =y9H=n>/> p?~j>D?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xhn> kgg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh?X2Y4 (CLOCK_ROOT) ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]/C JFDCEXhzr> Jclock pessimismXhy gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXh$?/ JXh4 JslackXh = RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C~zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuQ>}fNÿTտ^=η?T?>=)9H=w>/>/}?~j>Ȗ?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xhw> ~zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhη?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhT?X2Y4 (CLOCK_ROOT) |xg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]/C JFDCEXhzr> Jclock pessimismXh) zvg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhfNÿ; J arrival timeXhJ ?/ JXh4 JslackXh>= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuJ>}|2̿j=G?2?3$=ft9H=t>/> p?~j>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xht> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh2?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]/C JFDCEXhzr> Jclock pessimismXhft yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXh?/ JXh4 JslackXh3$= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuJ>}|2̿j=G?2?3$=ft9H=t>/> p?~j>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xht> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh2?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]/C JFDCEXhzr> Jclock pessimismXhft yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXh?/ JXh4 JslackXh3$= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C|xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuJ>}|2̿j=G?2?3$=ft9H=t>/> p?~j>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xht> |xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh2?X2Y4 (CLOCK_ROOT) zvg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]/C JFDCEXhzr> Jclock pessimismXhft xtg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXh?/ JXh4 JslackXh3$= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuJ>}|2̿j=G?2?3$=ft9H=t>/> p?~j>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xht> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh2?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]/C JFDCEXhzr> Jclock pessimismXhft yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXh?/ JXh4 JslackXh3$= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuJ>}|2̿j=G?2?3$=ft9H=t>/> p?~j>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xht> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh2?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]/C JFDCEXhzr> Jclock pessimismXhft yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXh?/ JXh4 JslackXh3$= RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsumt>}WϽ{ο!==G?{?%>G9H=[B>/> p?~j>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh[B> }yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhG?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh{?X2Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]/C JFDCEXhzr> Jclock pessimismXhG yug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhWϽ; J arrival timeXh RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuv@}oA\>8A!RA@Ą@!R@oA=А=$WN>2>=V>@?p=B@S?%@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh@ d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhĄ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh!R@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] b^g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh\>8A; J arrival timeXh1/ JXh4 JslackXh2>*RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oA-a=Ad;g(ܾĄ@d;g@oA=А=$WN>>=V>4^@?p=B@S?h%@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/gbt_txreset_s[0] Jnet (fo=227, routed)Xh4^@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhĄ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhd;g@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]Recov_DFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh-a=A; J arrival timeXh5/ JXh4 JslackXh>&RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]/PRE"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oA-a=Ad;g(ܾĄ@d;g@oA=А=$WN>>=V>4^@?p=B@S?h%@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/gbt_txreset_s[0] Jnet (fo=227, routed)Xh4^@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhĄ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27445, routed)Xhd;g@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]Recov_CFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh-a=A; J arrival timeXh5/ JXh4 JslackXh> RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu @}oAJ8AHR|?Ą@HR@oA=А=$WN>f]?=V>@?p=B@S?L7@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh@ ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhĄ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhHR@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhJ8A; J arrival timeXhr*/ JXh4 JslackXhf]? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu @}oAJ8AHR|?Ą@HR@oA=А=$WN>f]?=V>@?p=B@S?L7@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh@ ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhĄ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhHR@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhJ8A; J arrival timeXhr*/ JXh4 JslackXhf]? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu @}oAJ8AHR|?Ą@HR@oA=А=$WN>f]?=V>@?p=B@S?L7@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh@ ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)XhĄ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhHR@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhJ8A; J arrival timeXhr*/ JXh4 JslackXhf]? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oA+5AOGed;@OG@oA=А=$WN>F?_9=)\>O@?+?@S?T@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)XhO@ ~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhd;@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhOG@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]/C JFDCEXhzr> Jclock pessimismXh_9=@ Jclock uncertaintyXhڽ zvg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+5A; J arrival timeXh"/ JXh4 JslackXhF? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oA05AG/dd;@G@oA=А=$WN>F?_9=)\>X@?+?@S?@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)XhX@ }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhd;@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)XhG@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/C JFDCEXhzr> Jclock pessimismXh_9=@ Jclock uncertaintyXhڽ yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh05A; J arrival timeXh+"/ JXh4 JslackXhF? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsul@}oAP5A Hbd;@ H@oA=А=$WN>?_9=)\>l@?+?@S?v@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xhl@ ~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhd;@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh H@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]/C JFDCEXhzr> Jclock pessimismXh_9=@ Jclock uncertaintyXhڽ zvg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhP5A; J arrival timeXhh!/ JXh4 JslackXh? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]/CLR"4RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0*X2Y424RCLK_RCLK_BRAM_L_BRAMCLMP_FT_X34Y329/CLK_VDISTR_BOT0:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oAT5A&1H]bd;@&1H@oA=А=$WN>?_9=)\>t@?+?@S?+@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xht@ }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27445, routed)Xhd;@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27445, routed)Xh&1H@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]/C JFDCEXhzr> Jclock pessimismXh_9=@ Jclock uncertaintyXhڽ yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhT5A; J arrival timeXh!/ JXh4 JslackXh?"FF_RX_PRESENTn[0]FF_RX_PRESENTn[1]FF_RX_PRESENTn[2]FF_RX_PRESENTn[3] FF_RX_SCL[0] FF_RX_SCL[1] FF_RX_SCL[2] FF_RX_SCL[3] FF_RX_SDA[0] FF_RX_SDA[1] FF_RX_SDA[2] FF_RX_SDA[3]FF_TX_PRESENTn[0]FF_TX_PRESENTn[1]FF_TX_PRESENTn[2]FF_TX_PRESENTn[3] FF_TX_SCL[0] FF_TX_SCL[1] FF_TX_SCL[2] FF_TX_SCL[3] FF_TX_SDA[0] FF_TX_SDA[1] FF_TX_SDA[2] FF_TX_SDA[3] Si_LOLb Si_SCL Si_SDA board_id[0] board_id[1] board_id[2] board_id[3] board_id[4] board_id[5] board_id[6]FF_RX_RESETn[0]FF_RX_RESETn[1]FF_RX_RESETn[2]FF_RX_RESETn[3] FF_RX_SCL[0] FF_RX_SCL[1] FF_RX_SCL[2] FF_RX_SCL[3] FF_RX_SDA[0] FF_RX_SDA[1] FF_RX_SDA[2] FF_RX_SDA[3]FF_TX_RESETn[0]FF_TX_RESETn[1]FF_TX_RESETn[2]FF_TX_RESETn[3] FF_TX_SCL[0] FF_TX_SCL[1] FF_TX_SCL[2] FF_TX_SCL[3] FF_TX_SDA[0] FF_TX_SDA[1] FF_TX_SDA[2] FF_TX_SDA[3] Si_IN_SEL[0] Si_IN_SEL[1] Si_SCL Si_SDA